Lines Matching refs:hwc
210 struct hw_perf_event *hwc = &event->hw;
228 hwc->conf = event->attr.config;
229 hwc->conf1 = event->attr.config1;
242 struct hw_perf_event *hwc = &ev->hw;
243 u8 bank = hwc->iommu_bank;
244 u8 cntr = hwc->iommu_cntr;
247 reg = GET_CSOURCE(hwc);
250 reg = GET_DEVID_MASK(hwc);
251 reg = GET_DEVID(hwc) | (reg << 32);
256 reg = GET_PASID_MASK(hwc);
257 reg = GET_PASID(hwc) | (reg << 32);
262 reg = GET_DOMID_MASK(hwc);
263 reg = GET_DOMID(hwc) | (reg << 32);
272 struct hw_perf_event *hwc = &event->hw;
275 amd_iommu_pc_set_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr,
281 struct hw_perf_event *hwc = &event->hw;
283 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
286 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
287 hwc->state = 0;
304 amd_iommu_pc_set_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr,
314 struct hw_perf_event *hwc = &event->hw;
317 if (amd_iommu_pc_get_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr,
333 struct hw_perf_event *hwc = &event->hw;
335 if (hwc->state & PERF_HES_UPTODATE)
343 hwc->state |= PERF_HES_UPTODATE;
346 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
347 hwc->state |= PERF_HES_STOPPED;
369 struct hw_perf_event *hwc = &event->hw;
377 hwc->iommu_bank, hwc->iommu_cntr);