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Searched refs:guc (Results 1 – 25 of 32) sorted by relevance

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/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_ads.c84 static u32 guc_ads_regset_size(struct intel_guc *guc) in guc_ads_regset_size() argument
86 GEM_BUG_ON(!guc->ads_regset_size); in guc_ads_regset_size()
87 return guc->ads_regset_size; in guc_ads_regset_size()
90 static u32 guc_ads_golden_ctxt_size(struct intel_guc *guc) in guc_ads_golden_ctxt_size() argument
92 return PAGE_ALIGN(guc->ads_golden_ctxt_size); in guc_ads_golden_ctxt_size()
95 static u32 guc_ads_waklv_size(struct intel_guc *guc) in guc_ads_waklv_size() argument
97 return PAGE_ALIGN(guc->ads_waklv_size); in guc_ads_waklv_size()
100 static u32 guc_ads_capture_size(struct intel_guc *guc) in guc_ads_capture_size() argument
102 return PAGE_ALIGN(guc->ads_capture_size); in guc_ads_capture_size()
105 static u32 guc_ads_private_data_size(struct intel_guc *guc) in guc_ads_private_data_size() argument
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H A Dintel_guc_rc.c13 static bool __guc_rc_supported(struct intel_guc *guc) in __guc_rc_supported() argument
16 return guc->submission_supported && in __guc_rc_supported()
17 GRAPHICS_VER(guc_to_i915(guc)) >= 12; in __guc_rc_supported()
20 static bool __guc_rc_selected(struct intel_guc *guc) in __guc_rc_selected() argument
22 if (!intel_guc_rc_is_supported(guc)) in __guc_rc_selected()
25 return guc->submission_selected; in __guc_rc_selected()
28 void intel_guc_rc_init_early(struct intel_guc *guc) in intel_guc_rc_init_early() argument
30 guc->rc_supported = __guc_rc_supported(guc); in intel_guc_rc_init_early()
31 guc->rc_selected = __guc_rc_selected(guc); in intel_guc_rc_init_early()
34 static int guc_action_control_gucrc(struct intel_guc *guc, bool enable) in guc_action_control_gucrc() argument
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H A Dintel_guc_capture.c292 guc_capture_alloc_steered_lists(struct intel_guc *guc, in guc_capture_alloc_steered_lists() argument
295 struct intel_gt *gt = guc_to_gt(guc); in guc_capture_alloc_steered_lists()
307 if (!list || guc->capture->extlists) in guc_capture_alloc_steered_lists()
347 guc_dbg(guc, "capture found %d ext-regs.\n", num_tot_regs); in guc_capture_alloc_steered_lists()
348 guc->capture->extlists = extlists; in guc_capture_alloc_steered_lists()
352 guc_capture_get_device_reglist(struct intel_guc *guc) in guc_capture_get_device_reglist() argument
354 struct drm_i915_private *i915 = guc_to_i915(guc); in guc_capture_get_device_reglist()
368 guc_capture_alloc_steered_lists(guc, lists); in guc_capture_get_device_reglist()
412 guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid, in guc_capture_list_init() argument
416 const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists; in guc_capture_list_init()
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H A Dintel_guc_submission.h16 void intel_guc_submission_init_early(struct intel_guc *guc);
17 int intel_guc_submission_init(struct intel_guc *guc);
18 int intel_guc_submission_enable(struct intel_guc *guc);
19 void intel_guc_submission_disable(struct intel_guc *guc);
20 void intel_guc_submission_fini(struct intel_guc *guc);
21 int intel_guc_preempt_work_create(struct intel_guc *guc);
22 void intel_guc_preempt_work_destroy(struct intel_guc *guc);
24 void intel_guc_submission_print_info(struct intel_guc *guc,
26 void intel_guc_submission_print_context_info(struct intel_guc *guc,
36 int intel_guc_wait_for_pending_msg(struct intel_guc *guc,
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H A Dintel_guc_rc.h11 void intel_guc_rc_init_early(struct intel_guc *guc);
13 static inline bool intel_guc_rc_is_supported(struct intel_guc *guc) in intel_guc_rc_is_supported() argument
15 return guc->rc_supported; in intel_guc_rc_is_supported()
18 static inline bool intel_guc_rc_is_wanted(struct intel_guc *guc) in intel_guc_rc_is_wanted() argument
20 return guc->submission_selected && intel_guc_rc_is_supported(guc); in intel_guc_rc_is_wanted()
23 static inline bool intel_guc_rc_is_used(struct intel_guc *guc) in intel_guc_rc_is_used() argument
25 return intel_guc_submission_is_used(guc) && intel_guc_rc_is_wanted(guc); in intel_guc_rc_is_used()
28 int intel_guc_rc_enable(struct intel_guc *guc);
29 int intel_guc_rc_disable(struct intel_guc *guc);
H A Dintel_guc_ads.h16 int intel_guc_ads_create(struct intel_guc *guc);
17 void intel_guc_ads_destroy(struct intel_guc *guc);
18 void intel_guc_ads_init_late(struct intel_guc *guc);
19 void intel_guc_ads_reset(struct intel_guc *guc);
20 void intel_guc_ads_print_policy_info(struct intel_guc *guc,
23 u32 intel_guc_engine_usage_offset(struct intel_guc *guc);
H A Dintel_guc_capture.h26 void intel_guc_capture_process(struct intel_guc *guc);
27 int intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
29 int intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
31 int intel_guc_capture_getnullheader(struct intel_guc *guc, void **outptr, size_t *size);
32 void intel_guc_capture_destroy(struct intel_guc *guc);
33 int intel_guc_capture_init(struct intel_guc *guc);
H A Dintel_uc.h33 struct intel_guc guc; member
89 uc_state_checkers(guc, guc);
91 uc_state_checkers(guc, guc_submission);
92 uc_state_checkers(guc, guc_slpc);
93 uc_state_checkers(guc, guc_rc);
101 return intel_guc_wait_for_idle(&uc->guc, timeout); in intel_uc_wait_for_idle()
H A Dintel_guc_fw.h11 int intel_guc_fw_upload(struct intel_guc *guc);
H A Dintel_guc_debugfs.h12 void intel_guc_debugfs_register(struct intel_guc *guc, struct dentry *root);
/linux/drivers/gpu/drm/xe/
H A Dxe_guc_submit.c52 static int guc_submit_reset_prepare(struct xe_guc *guc);
57 return &q->gt->uc.guc; in exec_queue_to_guc()
79 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_REGISTERED; in exec_queue_registered()
84 atomic_or(EXEC_QUEUE_STATE_REGISTERED, &q->guc->state); in set_exec_queue_registered()
89 atomic_and(~EXEC_QUEUE_STATE_REGISTERED, &q->guc->state); in clear_exec_queue_registered()
94 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_ENABLED; in exec_queue_enabled()
99 atomic_or(EXEC_QUEUE_STATE_ENABLED, &q->guc->state); in set_exec_queue_enabled()
104 atomic_and(~EXEC_QUEUE_STATE_ENABLED, &q->guc->state); in clear_exec_queue_enabled()
109 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_ENABLE; in exec_queue_pending_enable()
114 atomic_or(EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state); in set_exec_queue_pending_enable()
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H A Dxe_guc_capture.c356 struct xe_guc *guc = &gt->uc.guc; in xe_guc_capture_get_reg_desc_list() local
358 reglists = guc->capture->extlists; in xe_guc_capture_get_reg_desc_list()
426 static void guc_capture_alloc_steered_lists(struct xe_guc *guc) in guc_capture_alloc_steered_lists() argument
428 struct xe_gt *gt = guc_to_gt(guc); in guc_capture_alloc_steered_lists()
431 const struct __guc_mmio_reg_descr_group *lists = guc->capture->reglists; in guc_capture_alloc_steered_lists()
466 if (!list || guc->capture->extlists) in guc_capture_alloc_steered_lists()
475 guc_capture_get_steer_reg_num(guc_to_xe(guc)); in guc_capture_alloc_steered_lists()
508 xe_gt_dbg(guc_to_gt(guc), "capture found %d ext-regs.\n", total); in guc_capture_alloc_steered_lists()
509 guc->capture->extlists = extlists; in guc_capture_alloc_steered_lists()
513 guc_capture_list_init(struct xe_guc *guc, u32 owner, u32 type, in guc_capture_list_init() argument
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H A Dxe_uc.c40 ret = xe_guc_init_noalloc(&uc->guc); in xe_uc_init_noalloc()
60 ret = xe_guc_init(&uc->guc); in xe_uc_init()
81 ret = xe_guc_min_load_for_hwconfig(&uc->guc); in xe_uc_init()
109 err = xe_guc_init_post_hwconfig(&uc->guc); in xe_uc_init_post_hwconfig()
125 ret = xe_guc_reset(&uc->guc); in uc_reset()
137 xe_guc_sanitize(&uc->guc); in xe_uc_sanitize()
155 err = xe_guc_enable_communication(&uc->guc); in vf_uc_load_hw()
163 err = xe_guc_opt_in_features_enable(&uc->guc); in vf_uc_load_hw()
167 err = xe_guc_submit_enable(&uc->guc); in vf_uc_load_hw()
197 ret = xe_guc_upload(&uc->guc); in xe_uc_load_hw()
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H A Dxe_guc_hwconfig.h14 int xe_guc_hwconfig_init(struct xe_guc *guc);
15 u32 xe_guc_hwconfig_size(struct xe_guc *guc);
16 void xe_guc_hwconfig_copy(struct xe_guc *guc, void *dst);
17 void xe_guc_hwconfig_dump(struct xe_guc *guc, struct drm_printer *p);
18 int xe_guc_hwconfig_lookup_u32(struct xe_guc *guc, u32 attribute, u32 *val);
H A Dxe_wopcm.c141 u32 base = wopcm->guc.base; in __wopcm_init_regs()
142 u32 size = wopcm->guc.size; in __wopcm_init_regs()
214 u32 guc_fw_size = xe_uc_fw_get_upload_size(&gt->uc.guc.fw); in xe_wopcm_init()
273 wopcm->guc.base = guc_wopcm_base; in xe_wopcm_init()
274 wopcm->guc.size = guc_wopcm_size; in xe_wopcm_init()
275 XE_WARN_ON(!wopcm->guc.base); in xe_wopcm_init()
276 XE_WARN_ON(!wopcm->guc.size); in xe_wopcm_init()
H A Dxe_gt_sriov_pf_monitor.c32 gt->sriov.pf.vfs[vfid].monitor.guc.events[e] = 0; in xe_gt_sriov_pf_monitor_flr()
41 gt->sriov.pf.vfs[vfid].monitor.guc.events[e]++; in pf_update_event_counter()
132 if (data->guc.events[e]) in xe_gt_sriov_pf_monitor_print_events()
141 #define __value(TAG, NAME, ...) , #NAME, data->guc.events[MAKE_XE_GUC_KLV_THRESHOLD_INDEX(TAG)] in xe_gt_sriov_pf_monitor_print_events()
H A Dxe_gt_sriov_pf_migration.c154 static int guc_action_vf_save_restore(struct xe_guc *guc, u32 vfid, u32 opcode, in guc_action_vf_save_restore() argument
168 return xe_guc_ct_send_block(&guc->ct, request, ARRAY_SIZE(request)); in guc_action_vf_save_restore()
176 ret = guc_action_vf_save_restore(&gt->uc.guc, vfid, GUC_PF_OPCODE_VF_SAVE, 0, 0); in pf_send_guc_query_vf_mig_data_size()
185 struct xe_guc *guc = &gt->uc.guc; in pf_send_guc_save_vf_mig_data() local
186 CLASS(xe_guc_buf, buf)(&guc->buf, ndwords); in pf_send_guc_save_vf_mig_data()
198 ret = guc_action_vf_save_restore(guc, vfid, GUC_PF_OPCODE_VF_SAVE, in pf_send_guc_save_vf_mig_data()
215 struct xe_guc *guc = &gt->uc.guc; in pf_send_guc_restore_vf_mig_data() local
216 CLASS(xe_guc_buf_from_data, buf)(&guc->buf, src, size); in pf_send_guc_restore_vf_mig_data()
225 ret = guc_action_vf_save_restore(guc, vfid, GUC_PF_OPCODE_VF_RESTORE, in pf_send_guc_restore_vf_mig_data()
1029 if (!GUC_FIRMWARE_VER_AT_LEAST(&gt->uc.guc, 70, 54)) in pf_gt_migration_check_support()
H A Dxe_pmu.c287 val = xe_guc_engine_activity_active_ticks(&gt->uc.guc, hwe, function_id); in read_engine_events()
289 val = xe_guc_engine_activity_total_ticks(&gt->uc.guc, hwe, function_id); in read_engine_events()
308 return xe_guc_pc_get_act_freq(&gt->uc.guc.pc); in __xe_pmu_event_read()
310 return xe_guc_pc_get_cur_freq_fw(&gt->uc.guc.pc); in __xe_pmu_event_read()
517 if (xe_guc_engine_activity_supported(&gt->uc.guc)) { in set_supported_events()
H A Dxe_gt_sriov_pf_monitor_types.h19 } guc; member
H A Dxe_guc_debugfs.h12 void xe_guc_debugfs_register(struct xe_guc *guc, struct dentry *parent);
H A Dxe_wopcm_types.h23 } guc; member
H A Dxe_guc_log.c104 return container_of(log, struct xe_gt, uc.guc.log); in log_to_gt()
192 struct xe_guc *guc = log_to_guc(log); in xe_guc_log_snapshot_capture() local
221 snapshot->ver_found = guc->fw.versions.found[XE_UC_FW_VER_RELEASE]; in xe_guc_log_snapshot_capture()
222 snapshot->ver_want = guc->fw.versions.wanted; in xe_guc_log_snapshot_capture()
223 snapshot->path = guc->fw.path; in xe_guc_log_snapshot_capture()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt.h102 static inline struct intel_gt *guc_to_gt(struct intel_guc *guc) in guc_to_gt() argument
104 return container_of(guc, struct intel_gt, uc.guc); in guc_to_gt()
122 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) in guc_to_i915() argument
124 return guc_to_gt(guc)->i915; in guc_to_i915()
129 return &gt->uc.guc; in gt_to_guc()
/linux/drivers/gpu/drm/i915/selftests/
H A Dintel_scheduler_helpers.c70 err = intel_guc_global_policies_update(&engine->gt->uc.guc); in intel_selftest_modify_policy()
89 return intel_guc_global_policies_update(&engine->gt->uc.guc); in intel_selftest_restore_policy()
/linux/drivers/gpu/drm/xe/tests/
H A Dxe_guc_relay_test.c41 relay = &xe_device_get_gt(xe, 0)->uc.guc.relay; in relay_test_init()
479 struct xe_guc_relay *relay = &xe_device_get_gt(xe, 0)->uc.guc.relay; in xe_drops_guc2pf_if_not_ready()
489 struct xe_guc_relay *relay = &xe_device_get_gt(xe, 0)->uc.guc.relay; in xe_drops_guc2vf_if_not_ready()
499 struct xe_guc_relay *relay = &xe_device_get_gt(xe, 0)->uc.guc.relay; in xe_rejects_send_if_not_ready()

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