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Searched refs:gt (Results 1 – 25 of 201) sorted by relevance

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/linux/drivers/gpu/drm/xe/
H A Dxe_gt.c76 struct xe_gt *gt; in xe_gt_alloc() local
78 gt = drmm_kzalloc(drm, sizeof(*gt), GFP_KERNEL); in xe_gt_alloc()
79 if (!gt) in xe_gt_alloc()
82 gt->tile = tile; in xe_gt_alloc()
91 gt->ordered_wq = ordered_wq; in xe_gt_alloc()
93 return gt; in xe_gt_alloc()
96 void xe_gt_sanitize(struct xe_gt *gt) in xe_gt_sanitize() argument
102 xe_guc_submit_disable(&gt->uc.guc); in xe_gt_sanitize()
105 static void xe_gt_enable_host_l2_vram(struct xe_gt *gt) in xe_gt_enable_host_l2_vram() argument
109 if (!XE_GT_WA(gt, 16023588340)) in xe_gt_enable_host_l2_vram()
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H A Dxe_gt_sriov_pf_migration.c32 static struct xe_gt_sriov_migration_data *pf_pick_gt_migration(struct xe_gt *gt, unsigned int vfid) in pf_pick_gt_migration() argument
34 xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt))); in pf_pick_gt_migration()
35 xe_gt_assert(gt, vfid != PFID); in pf_pick_gt_migration()
36 xe_gt_assert(gt, vfid <= xe_sriov_pf_get_totalvfs(gt_to_xe(gt))); in pf_pick_gt_migration()
38 return &gt->sriov.pf.vfs[vfid].migration; in pf_pick_gt_migration()
41 static void pf_dump_mig_data(struct xe_gt *gt, unsigned int vfid, in pf_dump_mig_data() argument
46 struct drm_printer p = xe_gt_dbg_printer(gt); in pf_dump_mig_data()
54 static ssize_t pf_migration_ggtt_size(struct xe_gt *gt, unsigned int vfid) in pf_migration_ggtt_size() argument
56 if (!xe_gt_is_main_type(gt)) in pf_migration_ggtt_size()
59 return xe_gt_sriov_pf_config_ggtt_save(gt, vfid, NULL, 0); in pf_migration_ggtt_size()
[all …]
H A Dxe_gt_ccs_mode.c19 static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines) in __xe_gt_apply_ccs_mode() argument
22 int num_slices = hweight32(CCS_INSTANCES(gt)); in __xe_gt_apply_ccs_mode()
23 struct xe_device *xe = gt_to_xe(gt); in __xe_gt_apply_ccs_mode()
27 xe_assert(xe, xe_gt_ccs_mode_enabled(gt)); in __xe_gt_apply_ccs_mode()
54 for_each_hw_engine(hwe, gt, id) { in __xe_gt_apply_ccs_mode()
64 while ((CCS_INSTANCES(gt) & BIT(cslice)) == 0) in __xe_gt_apply_ccs_mode()
79 xe_mmio_write32(&gt->mmio, CCS_MODE, mode); in __xe_gt_apply_ccs_mode()
81 xe_gt_dbg(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n", in __xe_gt_apply_ccs_mode()
85 void xe_gt_apply_ccs_mode(struct xe_gt *gt) in xe_gt_apply_ccs_mode() argument
87 if (!gt->ccs_mode || IS_SRIOV_VF(gt_to_xe(gt))) in xe_gt_apply_ccs_mode()
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H A Dxe_hw_engine.c282 hwe->gt = NULL; in hw_engine_fini()
298 xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base)); in xe_hw_engine_mmio_write32()
299 xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain); in xe_hw_engine_mmio_write32()
303 xe_mmio_write32(&hwe->gt->mmio, reg, val); in xe_hw_engine_mmio_write32()
318 xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base)); in xe_hw_engine_mmio_read32()
319 xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain); in xe_hw_engine_mmio_read32()
323 return xe_mmio_read32(&hwe->gt->mmio, reg); in xe_hw_engine_mmio_read32()
329 xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE); in xe_hw_engine_enable_ring()
333 xe_mmio_write32(&hwe->gt->mmio, RCU_MODE, in xe_hw_engine_enable_ring()
340 if (xe_device_has_msix(gt_to_xe(hwe->gt))) in xe_hw_engine_enable_ring()
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H A Dxe_eu_stall.c54 struct xe_gt *gt; member
86 struct xe_gt *gt; member
218 struct xe_gt *gt = arg; in xe_eu_stall_fini() local
220 destroy_workqueue(gt->eu_stall->buf_ptr_poll_wq); in xe_eu_stall_fini()
221 mutex_destroy(&gt->eu_stall->stream_lock); in xe_eu_stall_fini()
222 kfree(gt->eu_stall); in xe_eu_stall_fini()
233 int xe_eu_stall_init(struct xe_gt *gt) in xe_eu_stall_init() argument
235 struct xe_device *xe = gt_to_xe(gt); in xe_eu_stall_init()
241 gt->eu_stall = kzalloc_obj(*gt->eu_stall); in xe_eu_stall_init()
242 if (!gt->eu_stall) { in xe_eu_stall_init()
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H A Dxe_gt_sriov_pf_debugfs.c119 struct xe_gt *gt = extract_gt(data); \
120 struct xe_device *xe = gt_to_xe(gt); \
127 err = xe_gt_sriov_pf_policy_set_##POLICY(gt, val); \
136 struct xe_gt *gt = extract_gt(data); \
138 *val = xe_gt_sriov_pf_policy_get_##POLICY(gt); \
148 static void pf_add_policy_attrs(struct xe_gt *gt, struct dentry *parent) in pf_add_policy_attrs() argument
150 xe_gt_assert(gt, gt == extract_gt(parent)); in pf_add_policy_attrs()
151 xe_gt_assert(gt, PFID == extract_vfid(parent)); in pf_add_policy_attrs()
197 struct xe_gt *gt = extract_gt(m->private); in sched_groups_info() local
199 gt->sriov.pf.policy.guc.sched_groups.current_mode; in sched_groups_info()
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H A Dxe_guc.c161 static bool needs_wa_dual_queue(struct xe_gt *gt) in needs_wa_dual_queue() argument
168 if (XE_GT_WA(gt, 22011391025)) in needs_wa_dual_queue()
183 if (CCS_INSTANCES(gt) && GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) in needs_wa_dual_queue()
192 struct xe_gt *gt = guc_to_gt(guc); in guc_ctl_wa_flags() local
195 if (XE_GT_WA(gt, 22012773006)) in guc_ctl_wa_flags()
198 if (XE_GT_WA(gt, 14014475959)) in guc_ctl_wa_flags()
201 if (needs_wa_dual_queue(gt)) in guc_ctl_wa_flags()
212 if (XE_GT_WA(gt, 22012727170) || XE_GT_WA(gt, 22012727685)) in guc_ctl_wa_flags()
215 if (XE_GT_WA(gt, 18020744125) && in guc_ctl_wa_flags()
216 !xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER)) in guc_ctl_wa_flags()
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H A Dxe_gsc_proxy.c68 struct xe_gt *gt = gsc_to_gt(gsc); in xe_gsc_proxy_init_done() local
69 u32 fwsts1 = xe_mmio_read32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE)); in xe_gsc_proxy_init_done()
77 struct xe_gt *gt = gsc_to_gt(gsc); in xe_gsc_wait_for_proxy_init_done() local
80 return xe_mmio_wait32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE), in xe_gsc_wait_for_proxy_init_done()
88 struct xe_gt *gt = gsc_to_gt(gsc); in __gsc_proxy_irq_rmw() local
93 xe_mmio_rmw32(&gt->mmio, HECI_H_CSR(MTL_GSC_HECI2_BASE), clr, set); in __gsc_proxy_irq_rmw()
112 struct xe_gt *gt = gsc_to_gt(gsc); in proxy_send_to_csme() local
118 xe_gt_err(gt, "Failed to send CSME proxy message\n"); in proxy_send_to_csme()
124 xe_gt_err(gt, "Failed to receive CSME proxy message\n"); in proxy_send_to_csme()
133 struct xe_gt *gt = gsc_to_gt(gsc); in proxy_send_to_gsc() local
[all …]
H A Dxe_guc_ads.c234 static size_t calculate_regset_size(struct xe_gt *gt) in calculate_regset_size() argument
242 for_each_hw_engine(hwe, gt, id) in calculate_regset_size()
248 if (XE_GT_WA(gt, 1607983814)) in calculate_regset_size()
254 static u32 engine_enable_mask(struct xe_gt *gt, enum xe_engine_class class) in engine_enable_mask() argument
260 for_each_hw_engine(hwe, gt, id) in engine_enable_mask()
269 struct xe_gt *gt = ads_to_gt(ads); in calculate_golden_lrc_size() local
274 if (!engine_enable_mask(gt, class)) in calculate_golden_lrc_size()
277 real_size = xe_gt_lrc_size(gt, class); in calculate_golden_lrc_size()
311 struct xe_gt *gt = ads_to_gt(ads); in guc_waklv_init() local
318 if (XE_GT_WA(gt, 16021333562)) in guc_waklv_init()
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H A Dxe_reg_sr.c75 struct xe_gt *gt) in xe_reg_sr_add() argument
110 xe_gt_err(gt, in xe_reg_sr_add()
130 static void apply_one_mmio(struct xe_gt *gt, struct xe_reg_sr_entry *entry) in apply_one_mmio() argument
148 xe_gt_mcr_unicast_read_any(gt, reg_mcr) : in apply_one_mmio()
149 xe_mmio_read32(&gt->mmio, reg)) & (~entry->clr_bits); in apply_one_mmio()
160 xe_gt_dbg(gt, "REG[0x%x] = 0x%08x", reg.addr, val); in apply_one_mmio()
163 xe_gt_mcr_multicast_write(gt, reg_mcr, val); in apply_one_mmio()
165 xe_mmio_write32(&gt->mmio, reg, val); in apply_one_mmio()
168 void xe_reg_sr_apply_mmio(struct xe_reg_sr *sr, struct xe_gt *gt) in xe_reg_sr_apply_mmio() argument
180 xe_gt_assert(gt, !IS_SRIOV_VF(gt_to_xe(gt))); in xe_reg_sr_apply_mmio()
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_reset.c156 static int i915_do_reset(struct intel_gt *gt, in i915_do_reset() argument
160 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev); in i915_do_reset()
185 static int g33_do_reset(struct intel_gt *gt, in g33_do_reset() argument
189 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev); in g33_do_reset()
195 static int g4x_do_reset(struct intel_gt *gt, in g4x_do_reset() argument
199 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev); in g4x_do_reset()
200 struct intel_uncore *uncore = gt->uncore; in g4x_do_reset()
211 GT_TRACE(gt, "Wait for media reset failed\n"); in g4x_do_reset()
219 GT_TRACE(gt, "Wait for render reset failed\n"); in g4x_do_reset()
232 static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask, in ilk_do_reset() argument
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H A Dintel_gt.h20 #define IS_GFX_GT_IP_RANGE(gt, from, until) ( \ argument
23 ((gt)->type != GT_MEDIA && \
24 GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
25 GRAPHICS_VER_FULL((gt)->i915) <= (until)))
34 #define IS_MEDIA_GT_IP_RANGE(gt, from, until) ( \ argument
37 ((gt) && (gt)->type == GT_MEDIA && \
38 MEDIA_VER_FULL((gt)->i915) >= (from) && \
39 MEDIA_VER_FULL((gt)->i915) <= (until)))
56 #define IS_GFX_GT_IP_STEP(gt, ipver, from, until) ( \ argument
58 (IS_GFX_GT_IP_RANGE((gt), (ipver), (ipver)) && \
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H A Dselftest_reset.c18 __igt_reset_stolen(struct intel_gt *gt, in __igt_reset_stolen() argument
22 struct i915_ggtt *ggtt = gt->ggtt; in __igt_reset_stolen()
23 const struct resource *dsm = &gt->i915->dsm.stolen; in __igt_reset_stolen()
51 igt_global_reset_lock(gt); in __igt_reset_stolen()
52 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in __igt_reset_stolen()
54 err = igt_spinner_init(&spin, gt); in __igt_reset_stolen()
58 for_each_engine(engine, gt, id) { in __igt_reset_stolen()
89 i915_gem_get_pat_index(gt->i915, in __igt_reset_stolen()
98 if (!__drm_mm_interval_first(&gt->i915->mm.stolen, in __igt_reset_stolen()
114 intel_gt_reset(gt, mask, NULL); in __igt_reset_stolen()
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H A Dintel_gt_pm_irq.c13 static void write_pm_imr(struct intel_gt *gt) in write_pm_imr() argument
15 struct drm_i915_private *i915 = gt->i915; in write_pm_imr()
16 struct intel_uncore *uncore = gt->uncore; in write_pm_imr()
17 u32 mask = gt->pm_imr; in write_pm_imr()
32 static void gen6_gt_pm_update_irq(struct intel_gt *gt, in gen6_gt_pm_update_irq() argument
40 lockdep_assert_held(gt->irq_lock); in gen6_gt_pm_update_irq()
42 new_val = gt->pm_imr; in gen6_gt_pm_update_irq()
46 if (new_val != gt->pm_imr) { in gen6_gt_pm_update_irq()
47 gt->pm_imr = new_val; in gen6_gt_pm_update_irq()
48 write_pm_imr(gt); in gen6_gt_pm_update_irq()
[all …]
H A Dintel_gt_sysfs.c49 static struct kobject *gt_get_parent_obj(struct intel_gt *gt) in gt_get_parent_obj() argument
51 return &gt->i915->drm.primary->kdev->kobj; in gt_get_parent_obj()
58 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name); in id_show() local
60 return sysfs_emit(buf, "%u\n", gt->info.id); in id_show()
81 void intel_gt_sysfs_register(struct intel_gt *gt) in intel_gt_sysfs_register() argument
91 if (gt_is_root(gt)) in intel_gt_sysfs_register()
92 intel_gt_sysfs_pm_init(gt, gt_get_parent_obj(gt)); in intel_gt_sysfs_register()
95 if (kobject_init_and_add(&gt->sysfs_gt, &kobj_gt_type, in intel_gt_sysfs_register()
96 gt->i915->sysfs_gt, "gt%d", gt->info.id)) in intel_gt_sysfs_register()
99 gt->sysfs_defaults = kobject_create_and_add(".defaults", &gt->sysfs_gt); in intel_gt_sysfs_register()
[all …]
H A Dselftest_slpc.c22 struct intel_gt *gt; member
53 static int slpc_set_freq(struct intel_gt *gt, u32 freq) in slpc_set_freq() argument
56 struct intel_guc_slpc *slpc = &gt_to_guc(gt)->slpc; in slpc_set_freq()
113 static u64 measure_power_at_freq(struct intel_gt *gt, int *freq, u64 *power) in measure_power_at_freq() argument
117 err = slpc_set_freq(gt, *freq); in measure_power_at_freq()
120 *freq = intel_rps_read_actual_frequency(&gt->rps); in measure_power_at_freq()
121 *power = slpc_measure_power(&gt->rps, freq); in measure_power_at_freq()
198 static int slpc_power(struct intel_gt *gt, struct intel_engine_cs *engine) in slpc_power() argument
200 struct intel_guc_slpc *slpc = &gt_to_guc(gt)->slpc; in slpc_power()
212 if (!librapl_supported(gt->i915)) in slpc_power()
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H A Dselftest_hangcheck.c33 struct intel_gt *gt; member
41 static int hang_init(struct hang *h, struct intel_gt *gt) in hang_init() argument
47 h->gt = gt; in hang_init()
49 h->ctx = kernel_context(gt->i915, NULL); in hang_init()
55 h->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in hang_init()
61 h->obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in hang_init()
76 intel_gt_coherent_map_type(gt, h->obj, false)); in hang_init()
106 struct intel_gt *gt = h->gt; in hang_create_request() local
116 obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in hang_create_request()
122 vaddr = i915_gem_object_pin_map_unlocked(obj, intel_gt_coherent_map_type(gt, obj, false)); in hang_create_request()
[all …]
H A Dselftest_gt_pm.c81 struct intel_gt *gt = arg; in live_gt_clocks() local
87 if (!gt->clock_frequency) { /* unknown */ in live_gt_clocks()
92 if (GRAPHICS_VER(gt->i915) < 4) /* Any CS_TIMESTAMP? */ in live_gt_clocks()
95 wakeref = intel_gt_pm_get(gt); in live_gt_clocks()
96 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL); in live_gt_clocks()
98 for_each_engine(engine, gt, id) { in live_gt_clocks()
109 time = intel_gt_clock_interval_to_ns(engine->gt, cycles); in live_gt_clocks()
110 expected = intel_gt_ns_to_clock_interval(engine->gt, dt); in live_gt_clocks()
114 engine->gt->clock_frequency / 1000); in live_gt_clocks()
131 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL); in live_gt_clocks()
[all …]
H A Dintel_gt_irq.h23 void gen11_gt_irq_reset(struct intel_gt *gt);
24 void gen11_gt_irq_postinstall(struct intel_gt *gt);
25 void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl);
27 bool gen11_gt_reset_one_iir(struct intel_gt *gt,
31 void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir);
33 void gen5_gt_irq_postinstall(struct intel_gt *gt);
34 void gen5_gt_irq_reset(struct intel_gt *gt);
35 void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask);
36 void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask);
38 void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir);
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H A Dintel_gt_mcr.h11 void intel_gt_mcr_init(struct intel_gt *gt);
12 void intel_gt_mcr_lock(struct intel_gt *gt, unsigned long *flags);
13 void intel_gt_mcr_unlock(struct intel_gt *gt, unsigned long flags);
14 void intel_gt_mcr_lock_sanitize(struct intel_gt *gt);
16 u32 intel_gt_mcr_read(struct intel_gt *gt,
19 u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg);
20 u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg);
22 void intel_gt_mcr_unicast_write(struct intel_gt *gt,
25 void intel_gt_mcr_multicast_write(struct intel_gt *gt,
27 void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt,
[all …]
H A Dintel_engine_cs.c273 u32 intel_engine_context_size(struct intel_gt *gt, u8 class) in intel_engine_context_size() argument
275 struct intel_uncore *uncore = gt->uncore; in intel_engine_context_size()
284 switch (GRAPHICS_VER(gt->i915)) { in intel_engine_context_size()
286 MISSING_CASE(GRAPHICS_VER(gt->i915)); in intel_engine_context_size()
296 if (IS_HASWELL(gt->i915)) in intel_engine_context_size()
319 gt_dbg(gt, "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n", in intel_engine_context_size()
320 GRAPHICS_VER(gt->i915), cxt_size * 64, in intel_engine_context_size()
337 if (GRAPHICS_VER(gt->i915) < 8) in intel_engine_context_size()
449 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, in intel_engine_setup() argument
453 struct drm_i915_private *i915 = gt->i915; in intel_engine_setup()
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/linux/drivers/gpu/drm/i915/selftests/
H A Digt_reset.c14 void igt_global_reset_lock(struct intel_gt *gt) in igt_global_reset_lock() argument
19 pr_debug("%s: current gpu_error=%08lx\n", __func__, gt->reset.flags); in igt_global_reset_lock()
21 while (test_and_set_bit(I915_RESET_BACKOFF, &gt->reset.flags)) in igt_global_reset_lock()
22 wait_event(gt->reset.queue, in igt_global_reset_lock()
23 !test_bit(I915_RESET_BACKOFF, &gt->reset.flags)); in igt_global_reset_lock()
25 for_each_engine(engine, gt, id) { in igt_global_reset_lock()
27 &gt->reset.flags)) in igt_global_reset_lock()
28 wait_on_bit(&gt->reset.flags, I915_RESET_ENGINE + id, in igt_global_reset_lock()
33 void igt_global_reset_unlock(struct intel_gt *gt) in igt_global_reset_unlock() argument
38 for_each_engine(engine, gt, id) in igt_global_reset_unlock()
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/linux/drivers/media/radio/
H A Dradio-gemtek.c150 static void gemtek_bu2614_transmit(struct gemtek *gt) in gemtek_bu2614_transmit() argument
152 struct radio_isa_card *isa = &gt->isa; in gemtek_bu2614_transmit()
155 mute = gt->muted ? GEMTEK_MT : 0x00; in gemtek_bu2614_transmit()
160 for (i = 0, q = gt->bu2614data; i < 32; i++, q >>= 1) { in gemtek_bu2614_transmit()
182 struct gemtek *gt = kzalloc_obj(*gt); in gemtek_alloc() local
184 if (gt) in gemtek_alloc()
185 gt->muted = true; in gemtek_alloc()
186 return gt ? &gt->isa : NULL; in gemtek_alloc()
194 struct gemtek *gt = container_of(isa, struct gemtek, isa); in gemtek_s_frequency() local
196 if (hardmute && gt->muted) in gemtek_s_frequency()
[all …]
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_gsc_uc.c19 struct intel_gt *gt = gsc_uc_to_gt(gsc); in gsc_work() local
24 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in gsc_work()
26 spin_lock_irq(gt->irq_lock); in gsc_work()
29 spin_unlock_irq(gt->irq_lock); in gsc_work()
53 if (intel_uc_uses_huc(&gt->uc) && in gsc_work()
54 intel_huc_is_authenticated(&gt->uc.huc, INTEL_HUC_AUTH_BY_GUC)) in gsc_work()
55 intel_huc_auth(&gt->uc.huc, INTEL_HUC_AUTH_BY_GSC); in gsc_work()
60 gt_err(gt, "Proxy request received with GSC not loaded!\n"); in gsc_work()
71 gt_err(gt, "GSC proxy handler failed to init\n"); in gsc_work()
85 gt_dbg(gt, "GSC Proxy initialized\n"); in gsc_work()
[all …]
H A Dintel_guc_ads.c163 struct intel_gt *gt = guc_to_gt(guc); in guc_policies_init() local
164 struct drm_i915_private *i915 = gt->i915; in guc_policies_init()
206 struct intel_gt *gt = guc_to_gt(guc); in intel_guc_global_policies_update() local
222 with_intel_runtime_pm(&gt->i915->runtime_pm, wakeref) in intel_guc_global_policies_update()
228 static void guc_mapping_table_init(struct intel_gt *gt, in guc_mapping_table_init() argument
241 for_each_engine(engine, gt, id) { in guc_mapping_table_init()
301 static long __must_check guc_mmio_reg_add(struct intel_gt *gt, in guc_mmio_reg_add() argument
337 #define GUC_MMIO_REG_ADD(gt, regset, reg, masked) \ argument
338 guc_mmio_reg_add(gt, \
349 static long __must_check guc_mcr_reg_add(struct intel_gt *gt, in guc_mcr_reg_add() argument
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