124f90d66SChris Wilson // SPDX-License-Identifier: MIT
279ffac85SChris Wilson /*
379ffac85SChris Wilson * Copyright © 2019 Intel Corporation
479ffac85SChris Wilson */
579ffac85SChris Wilson
601fabda8SLucas De Marchi #include <linux/string_helpers.h>
7a70a9e99SChris Wilson #include <linux/suspend.h>
8a70a9e99SChris Wilson
979ffac85SChris Wilson #include "i915_drv.h"
10801543b2SJani Nikula #include "i915_irq.h"
11cb823ed9SChris Wilson #include "i915_params.h"
12dffa8febSChris Wilson #include "intel_context.h"
13092be382SChris Wilson #include "intel_engine_pm.h"
14cb823ed9SChris Wilson #include "intel_gt.h"
159c878557SChris Wilson #include "intel_gt_clock_utils.h"
1637280ef5SNirmoy Das #include "intel_gt_mcr.h"
1779ffac85SChris Wilson #include "intel_gt_pm.h"
1867804e48SJohn Harrison #include "intel_gt_print.h"
1966101975SChris Wilson #include "intel_gt_requests.h"
203e7abf81SAndi Shyti #include "intel_llc.h"
21c1132367SAndi Shyti #include "intel_rc6.h"
223e7abf81SAndi Shyti #include "intel_rps.h"
2379ffac85SChris Wilson #include "intel_wakeref.h"
240cfab4cbSHuang, Sean Z #include "pxp/intel_pxp_pm.h"
2579ffac85SChris Wilson
2681387fc4SThomas Hellström #define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2)
2781387fc4SThomas Hellström
user_forcewake(struct intel_gt * gt,bool suspend)28d4033a9bSChris Wilson static void user_forcewake(struct intel_gt *gt, bool suspend)
29d4033a9bSChris Wilson {
30d4033a9bSChris Wilson int count = atomic_read(>->user_wakeref);
315e4e06e4SAndrzej Hajda intel_wakeref_t wakeref;
32d4033a9bSChris Wilson
33d4033a9bSChris Wilson /* Inside suspend/resume so single threaded, no races to worry about. */
34d4033a9bSChris Wilson if (likely(!count))
35d4033a9bSChris Wilson return;
36d4033a9bSChris Wilson
375e4e06e4SAndrzej Hajda wakeref = intel_gt_pm_get(gt);
38d4033a9bSChris Wilson if (suspend) {
39d4033a9bSChris Wilson GEM_BUG_ON(count > atomic_read(>->wakeref.count));
40d4033a9bSChris Wilson atomic_sub(count, >->wakeref.count);
41d4033a9bSChris Wilson } else {
42d4033a9bSChris Wilson atomic_add(count, >->wakeref.count);
43d4033a9bSChris Wilson }
445e4e06e4SAndrzej Hajda intel_gt_pm_put(gt, wakeref);
45d4033a9bSChris Wilson }
46d4033a9bSChris Wilson
runtime_begin(struct intel_gt * gt)478c3b1ba0SChris Wilson static void runtime_begin(struct intel_gt *gt)
488c3b1ba0SChris Wilson {
498c3b1ba0SChris Wilson local_irq_disable();
508c3b1ba0SChris Wilson write_seqcount_begin(>->stats.lock);
518c3b1ba0SChris Wilson gt->stats.start = ktime_get();
528c3b1ba0SChris Wilson gt->stats.active = true;
538c3b1ba0SChris Wilson write_seqcount_end(>->stats.lock);
548c3b1ba0SChris Wilson local_irq_enable();
558c3b1ba0SChris Wilson }
568c3b1ba0SChris Wilson
runtime_end(struct intel_gt * gt)578c3b1ba0SChris Wilson static void runtime_end(struct intel_gt *gt)
588c3b1ba0SChris Wilson {
598c3b1ba0SChris Wilson local_irq_disable();
608c3b1ba0SChris Wilson write_seqcount_begin(>->stats.lock);
618c3b1ba0SChris Wilson gt->stats.active = false;
628c3b1ba0SChris Wilson gt->stats.total =
638c3b1ba0SChris Wilson ktime_add(gt->stats.total,
648c3b1ba0SChris Wilson ktime_sub(ktime_get(), gt->stats.start));
658c3b1ba0SChris Wilson write_seqcount_end(>->stats.lock);
668c3b1ba0SChris Wilson local_irq_enable();
678c3b1ba0SChris Wilson }
688c3b1ba0SChris Wilson
__gt_unpark(struct intel_wakeref * wf)69c7302f20SChris Wilson static int __gt_unpark(struct intel_wakeref *wf)
7079ffac85SChris Wilson {
71cb823ed9SChris Wilson struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref);
72cb823ed9SChris Wilson struct drm_i915_private *i915 = gt->i915;
7379ffac85SChris Wilson
74639f2f24SVenkata Sandeep Dhanalakota GT_TRACE(gt, "\n");
7579ffac85SChris Wilson
7679ffac85SChris Wilson /*
7779ffac85SChris Wilson * It seems that the DMC likes to transition between the DC states a lot
7879ffac85SChris Wilson * when there are no connected displays (no active power domains) during
7979ffac85SChris Wilson * command submission.
8079ffac85SChris Wilson *
8179ffac85SChris Wilson * This activity has negative impact on the performance of the chip with
8279ffac85SChris Wilson * huge latencies observed in the interrupt handler and elsewhere.
8379ffac85SChris Wilson *
8479ffac85SChris Wilson * Work around it by grabbing a GT IRQ power domain whilst there is any
8579ffac85SChris Wilson * GT activity, preventing any DC state transitions.
8679ffac85SChris Wilson */
87cb823ed9SChris Wilson gt->awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
88cb823ed9SChris Wilson GEM_BUG_ON(!gt->awake);
8979ffac85SChris Wilson
90730eaeb5SChris Wilson intel_rc6_unpark(>->rc6);
913e7abf81SAndi Shyti intel_rps_unpark(>->rps);
92da5d5167STvrtko Ursulin i915_pmu_gt_unparked(gt);
9377cdd054SUmesh Nerlige Ramappa intel_guc_busyness_unpark(gt);
9479ffac85SChris Wilson
9566101975SChris Wilson intel_gt_unpark_requests(gt);
968c3b1ba0SChris Wilson runtime_begin(gt);
9779ffac85SChris Wilson
9879ffac85SChris Wilson return 0;
9979ffac85SChris Wilson }
10079ffac85SChris Wilson
__gt_park(struct intel_wakeref * wf)101c7302f20SChris Wilson static int __gt_park(struct intel_wakeref *wf)
10279ffac85SChris Wilson {
103ee236af8STvrtko Ursulin struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref);
104ee236af8STvrtko Ursulin intel_wakeref_t wakeref = fetch_and_zero(>->awake);
105ee236af8STvrtko Ursulin struct drm_i915_private *i915 = gt->i915;
10679ffac85SChris Wilson
107639f2f24SVenkata Sandeep Dhanalakota GT_TRACE(gt, "\n");
10879ffac85SChris Wilson
1098c3b1ba0SChris Wilson runtime_end(gt);
11066101975SChris Wilson intel_gt_park_requests(gt);
11179ffac85SChris Wilson
11277cdd054SUmesh Nerlige Ramappa intel_guc_busyness_park(gt);
11371e51ca8SChris Wilson i915_vma_parked(gt);
114da5d5167STvrtko Ursulin i915_pmu_gt_parked(gt);
1153e7abf81SAndi Shyti intel_rps_park(>->rps);
116730eaeb5SChris Wilson intel_rc6_park(>->rc6);
11779ffac85SChris Wilson
118c7302f20SChris Wilson /* Everything switched off, flush any residual interrupt just in case */
119c7302f20SChris Wilson intel_synchronize_irq(i915);
120c7302f20SChris Wilson
12181ff52b7SChris Wilson /* Defer dropping the display power well for 100ms, it's slow! */
12279ffac85SChris Wilson GEM_BUG_ON(!wakeref);
12381ff52b7SChris Wilson intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref);
12479ffac85SChris Wilson
12579ffac85SChris Wilson return 0;
12679ffac85SChris Wilson }
12779ffac85SChris Wilson
128c7302f20SChris Wilson static const struct intel_wakeref_ops wf_ops = {
129c7302f20SChris Wilson .get = __gt_unpark,
130c7302f20SChris Wilson .put = __gt_park,
131c7302f20SChris Wilson };
13279ffac85SChris Wilson
intel_gt_pm_init_early(struct intel_gt * gt)13399f2eb96STvrtko Ursulin void intel_gt_pm_init_early(struct intel_gt *gt)
13479ffac85SChris Wilson {
135bec68cc9STvrtko Ursulin /*
136bec68cc9STvrtko Ursulin * We access the runtime_pm structure via gt->i915 here rather than
137bec68cc9STvrtko Ursulin * gt->uncore as we do elsewhere in the file because gt->uncore is not
138bec68cc9STvrtko Ursulin * yet initialized for all tiles at this point in the driver startup.
139bec68cc9STvrtko Ursulin * runtime_pm is per-device rather than per-tile, so this is still the
140bec68cc9STvrtko Ursulin * correct structure.
141bec68cc9STvrtko Ursulin */
1425e4e06e4SAndrzej Hajda intel_wakeref_init(>->wakeref, gt->i915, &wf_ops, "GT");
1438c3b1ba0SChris Wilson seqcount_mutex_init(>->stats.lock, >->wakeref.mutex);
14479ffac85SChris Wilson }
14579ffac85SChris Wilson
intel_gt_pm_init(struct intel_gt * gt)146c1132367SAndi Shyti void intel_gt_pm_init(struct intel_gt *gt)
147c1132367SAndi Shyti {
148c1132367SAndi Shyti /*
149c1132367SAndi Shyti * Enabling power-management should be "self-healing". If we cannot
150c1132367SAndi Shyti * enable a feature, simply leave it disabled with a notice to the
151c1132367SAndi Shyti * user.
152c1132367SAndi Shyti */
153c1132367SAndi Shyti intel_rc6_init(>->rc6);
1543e7abf81SAndi Shyti intel_rps_init(>->rps);
155c1132367SAndi Shyti }
156c1132367SAndi Shyti
reset_engines(struct intel_gt * gt)157cb823ed9SChris Wilson static bool reset_engines(struct intel_gt *gt)
15879ffac85SChris Wilson {
159cb823ed9SChris Wilson if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
16079ffac85SChris Wilson return false;
16179ffac85SChris Wilson
162*31c3c53eSNirmoy Das return intel_gt_reset_all_engines(gt) == 0;
16379ffac85SChris Wilson }
16479ffac85SChris Wilson
gt_sanitize(struct intel_gt * gt,bool force)165d03b224fSChris Wilson static void gt_sanitize(struct intel_gt *gt, bool force)
16679ffac85SChris Wilson {
16779ffac85SChris Wilson struct intel_engine_cs *engine;
16879ffac85SChris Wilson enum intel_engine_id id;
169fd6fe087SChris Wilson intel_wakeref_t wakeref;
17079ffac85SChris Wilson
17157bdac8eSAndrzej Hajda GT_TRACE(gt, "force:%s\n", str_yes_no(force));
172fd6fe087SChris Wilson
173fd6fe087SChris Wilson /* Use a raw wakeref to avoid calling intel_display_power_get early */
174fd6fe087SChris Wilson wakeref = intel_runtime_pm_get(gt->uncore->rpm);
175fd6fe087SChris Wilson intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
176fd6fe087SChris Wilson
1779c878557SChris Wilson intel_gt_check_clock_frequency(gt);
1789c878557SChris Wilson
179fd6fe087SChris Wilson /*
180fd6fe087SChris Wilson * As we have just resumed the machine and woken the device up from
181fd6fe087SChris Wilson * deep PCI sleep (presumably D3_cold), assume the HW has been reset
182fd6fe087SChris Wilson * back to defaults, recovering from whatever wedged state we left it
183fd6fe087SChris Wilson * in and so worth trying to use the device once more.
184fd6fe087SChris Wilson */
185fd6fe087SChris Wilson if (intel_gt_is_wedged(gt))
186fd6fe087SChris Wilson intel_gt_unset_wedged(gt);
18779ffac85SChris Wilson
188dac38381SUmesh Nerlige Ramappa /* For GuC mode, ensure submission is disabled before stopping ring */
189dac38381SUmesh Nerlige Ramappa intel_uc_reset_prepare(>->uc);
190dac38381SUmesh Nerlige Ramappa
191dac38381SUmesh Nerlige Ramappa for_each_engine(engine, gt, id) {
1923c00660dSChris Wilson if (engine->reset.prepare)
1933c00660dSChris Wilson engine->reset.prepare(engine);
19479ffac85SChris Wilson
1954a0ca47aSChris Wilson if (engine->sanitize)
1964a0ca47aSChris Wilson engine->sanitize(engine);
197dac38381SUmesh Nerlige Ramappa }
1984a0ca47aSChris Wilson
1993c00660dSChris Wilson if (reset_engines(gt) || force) {
2005d904e3cSTvrtko Ursulin for_each_engine(engine, gt, id)
201cb823ed9SChris Wilson __intel_engine_reset(engine, false);
20279ffac85SChris Wilson }
20379ffac85SChris Wilson
204eb5e7da7SMatthew Brost intel_uc_reset(>->uc, false);
205eb5e7da7SMatthew Brost
2065d904e3cSTvrtko Ursulin for_each_engine(engine, gt, id)
2073c00660dSChris Wilson if (engine->reset.finish)
2083c00660dSChris Wilson engine->reset.finish(engine);
209fd6fe087SChris Wilson
210389b7f00SChris Wilson intel_rps_sanitize(>->rps);
211389b7f00SChris Wilson
212fd6fe087SChris Wilson intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
213fd6fe087SChris Wilson intel_runtime_pm_put(gt->uncore->rpm, wakeref);
2143c00660dSChris Wilson }
2153c00660dSChris Wilson
intel_gt_pm_fini(struct intel_gt * gt)216c1132367SAndi Shyti void intel_gt_pm_fini(struct intel_gt *gt)
217c1132367SAndi Shyti {
218c1132367SAndi Shyti intel_rc6_fini(>->rc6);
219c1132367SAndi Shyti }
220c1132367SAndi Shyti
intel_gt_resume_early(struct intel_gt * gt)22135ba33f7SNirmoy Das void intel_gt_resume_early(struct intel_gt *gt)
22235ba33f7SNirmoy Das {
22337280ef5SNirmoy Das /*
22437280ef5SNirmoy Das * Sanitize steer semaphores during driver resume. This is necessary
22537280ef5SNirmoy Das * to address observed cases of steer semaphores being
22637280ef5SNirmoy Das * held after a suspend operation. Confirmation from the hardware team
22737280ef5SNirmoy Das * assures the safety of this operation, as no lock acquisitions
22837280ef5SNirmoy Das * by other agents occur during driver load/resume process.
22937280ef5SNirmoy Das */
23037280ef5SNirmoy Das intel_gt_mcr_lock_sanitize(gt);
23137280ef5SNirmoy Das
23235ba33f7SNirmoy Das intel_uncore_resume_early(gt->uncore);
23335ba33f7SNirmoy Das intel_gt_check_and_clear_faults(gt);
23435ba33f7SNirmoy Das }
23535ba33f7SNirmoy Das
intel_gt_resume(struct intel_gt * gt)236092be382SChris Wilson int intel_gt_resume(struct intel_gt *gt)
23779ffac85SChris Wilson {
23879ffac85SChris Wilson struct intel_engine_cs *engine;
23979ffac85SChris Wilson enum intel_engine_id id;
2405e4e06e4SAndrzej Hajda intel_wakeref_t wakeref;
241cfe6b30fSChris Wilson int err;
24279ffac85SChris Wilson
2433f04bdceSMichał Winiarski err = intel_gt_has_unrecoverable_error(gt);
244d03b224fSChris Wilson if (err)
245d03b224fSChris Wilson return err;
246d03b224fSChris Wilson
247639f2f24SVenkata Sandeep Dhanalakota GT_TRACE(gt, "\n");
248fd6fe087SChris Wilson
24979ffac85SChris Wilson /*
25079ffac85SChris Wilson * After resume, we may need to poke into the pinned kernel
25179ffac85SChris Wilson * contexts to paper over any damage caused by the sudden suspend.
25279ffac85SChris Wilson * Only the kernel contexts should remain pinned over suspend,
25379ffac85SChris Wilson * allowing us to fixup the user contexts on their first pin.
25479ffac85SChris Wilson */
2554243cd53SChris Wilson gt_sanitize(gt, true);
2564243cd53SChris Wilson
2575e4e06e4SAndrzej Hajda wakeref = intel_gt_pm_get(gt);
2583e7abf81SAndi Shyti
259c1132367SAndi Shyti intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
260c1132367SAndi Shyti intel_rc6_sanitize(>->rc6);
26145b152f7SChris Wilson if (intel_gt_is_wedged(gt)) {
26245b152f7SChris Wilson err = -EIO;
26345b152f7SChris Wilson goto out_fw;
26445b152f7SChris Wilson }
265c1132367SAndi Shyti
266cfe6b30fSChris Wilson /* Only when the HW is re-initialised, can we replay the requests */
267cfe6b30fSChris Wilson err = intel_gt_init_hw(gt);
268cfe6b30fSChris Wilson if (err) {
26967804e48SJohn Harrison gt_probe_error(gt, "Failed to initialize GPU, declaring it wedged!\n");
270d03b224fSChris Wilson goto err_wedged;
271cfe6b30fSChris Wilson }
272cfe6b30fSChris Wilson
273eb5e7da7SMatthew Brost intel_uc_reset_finish(>->uc);
274eb5e7da7SMatthew Brost
2753e7abf81SAndi Shyti intel_rps_enable(>->rps);
2763e7abf81SAndi Shyti intel_llc_enable(>->llc);
2773e7abf81SAndi Shyti
2785d904e3cSTvrtko Ursulin for_each_engine(engine, gt, id) {
279092be382SChris Wilson intel_engine_pm_get(engine);
280092be382SChris Wilson
281092be382SChris Wilson engine->serial++; /* kernel context lost */
282faea1792SDaniele Ceraolo Spurio err = intel_engine_resume(engine);
283092be382SChris Wilson
284092be382SChris Wilson intel_engine_pm_put(engine);
285092be382SChris Wilson if (err) {
28667804e48SJohn Harrison gt_err(gt, "Failed to restart %s (%d)\n",
287092be382SChris Wilson engine->name, err);
288d03b224fSChris Wilson goto err_wedged;
28979ffac85SChris Wilson }
29079ffac85SChris Wilson }
291c1132367SAndi Shyti
292c1132367SAndi Shyti intel_rc6_enable(>->rc6);
293fd6fe087SChris Wilson
294fd6fe087SChris Wilson intel_uc_resume(>->uc);
295fd6fe087SChris Wilson
296d4033a9bSChris Wilson user_forcewake(gt, false);
297d4033a9bSChris Wilson
298d03b224fSChris Wilson out_fw:
299c1132367SAndi Shyti intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
3005e4e06e4SAndrzej Hajda intel_gt_pm_put(gt, wakeref);
301a2ae2962SNirmoy Das intel_gt_bind_context_set_ready(gt);
302092be382SChris Wilson return err;
303d03b224fSChris Wilson
304d03b224fSChris Wilson err_wedged:
305d03b224fSChris Wilson intel_gt_set_wedged(gt);
306d03b224fSChris Wilson goto out_fw;
307092be382SChris Wilson }
3089dfe3459SDaniele Ceraolo Spurio
wait_for_suspend(struct intel_gt * gt)309a70a9e99SChris Wilson static void wait_for_suspend(struct intel_gt *gt)
310c1132367SAndi Shyti {
311a70a9e99SChris Wilson if (!intel_gt_pm_is_awake(gt))
312a70a9e99SChris Wilson return;
313a70a9e99SChris Wilson
31481387fc4SThomas Hellström if (intel_gt_wait_for_idle(gt, I915_GT_SUSPEND_IDLE_TIMEOUT) == -ETIME) {
315c1132367SAndi Shyti /*
316c1132367SAndi Shyti * Forcibly cancel outstanding work and leave
317c1132367SAndi Shyti * the gpu quiet.
318c1132367SAndi Shyti */
319c1132367SAndi Shyti intel_gt_set_wedged(gt);
3200cdfdf6fSChris Wilson intel_gt_retire_requests(gt);
321c1132367SAndi Shyti }
322c1132367SAndi Shyti
323c1132367SAndi Shyti intel_gt_pm_wait_for_idle(gt);
324c1132367SAndi Shyti }
325c1132367SAndi Shyti
intel_gt_suspend_prepare(struct intel_gt * gt)326a70a9e99SChris Wilson void intel_gt_suspend_prepare(struct intel_gt *gt)
327a70a9e99SChris Wilson {
328a2ae2962SNirmoy Das intel_gt_bind_context_set_unready(gt);
329a70a9e99SChris Wilson user_forcewake(gt, true);
330a70a9e99SChris Wilson wait_for_suspend(gt);
331a70a9e99SChris Wilson }
332a70a9e99SChris Wilson
pm_suspend_target(void)333a70a9e99SChris Wilson static suspend_state_t pm_suspend_target(void)
334a70a9e99SChris Wilson {
335e435c608SChris Wilson #if IS_ENABLED(CONFIG_SUSPEND) && IS_ENABLED(CONFIG_PM_SLEEP)
336a70a9e99SChris Wilson return pm_suspend_target_state;
337a70a9e99SChris Wilson #else
338a70a9e99SChris Wilson return PM_SUSPEND_TO_IDLE;
339a70a9e99SChris Wilson #endif
340a70a9e99SChris Wilson }
341a70a9e99SChris Wilson
intel_gt_suspend_late(struct intel_gt * gt)342a70a9e99SChris Wilson void intel_gt_suspend_late(struct intel_gt *gt)
343c1132367SAndi Shyti {
344c1132367SAndi Shyti intel_wakeref_t wakeref;
345c1132367SAndi Shyti
346c1132367SAndi Shyti /* We expect to be idle already; but also want to be independent */
347a70a9e99SChris Wilson wait_for_suspend(gt);
348c1132367SAndi Shyti
349e26b6d43SChris Wilson if (is_mock_gt(gt))
350e26b6d43SChris Wilson return;
351e26b6d43SChris Wilson
352e26b6d43SChris Wilson GEM_BUG_ON(gt->awake);
353e26b6d43SChris Wilson
354c56ce956SThomas Hellström intel_uc_suspend(>->uc);
355c56ce956SThomas Hellström
356a70a9e99SChris Wilson /*
357a70a9e99SChris Wilson * On disabling the device, we want to turn off HW access to memory
358a70a9e99SChris Wilson * that we no longer own.
359a70a9e99SChris Wilson *
360a70a9e99SChris Wilson * However, not all suspend-states disable the device. S0 (s2idle)
361a70a9e99SChris Wilson * is effectively runtime-suspend, the device is left powered on
362a70a9e99SChris Wilson * but needs to be put into a low power state. We need to keep
363a70a9e99SChris Wilson * powermanagement enabled, but we also retain system state and so
364a70a9e99SChris Wilson * it remains safe to keep on using our allocated memory.
365a70a9e99SChris Wilson */
366a70a9e99SChris Wilson if (pm_suspend_target() == PM_SUSPEND_TO_IDLE)
367a70a9e99SChris Wilson return;
368fd6fe087SChris Wilson
3693e7abf81SAndi Shyti with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
3703e7abf81SAndi Shyti intel_rps_disable(>->rps);
371c1132367SAndi Shyti intel_rc6_disable(>->rc6);
3723e7abf81SAndi Shyti intel_llc_disable(>->llc);
3733e7abf81SAndi Shyti }
374fd6fe087SChris Wilson
375d03b224fSChris Wilson gt_sanitize(gt, false);
376fd6fe087SChris Wilson
377639f2f24SVenkata Sandeep Dhanalakota GT_TRACE(gt, "\n");
378c1132367SAndi Shyti }
379c1132367SAndi Shyti
intel_gt_runtime_suspend(struct intel_gt * gt)3809dfe3459SDaniele Ceraolo Spurio void intel_gt_runtime_suspend(struct intel_gt *gt)
3819dfe3459SDaniele Ceraolo Spurio {
382a2ae2962SNirmoy Das intel_gt_bind_context_set_unready(gt);
3839dfe3459SDaniele Ceraolo Spurio intel_uc_runtime_suspend(>->uc);
384fd6fe087SChris Wilson
385639f2f24SVenkata Sandeep Dhanalakota GT_TRACE(gt, "\n");
3869dfe3459SDaniele Ceraolo Spurio }
3879dfe3459SDaniele Ceraolo Spurio
intel_gt_runtime_resume(struct intel_gt * gt)3889dfe3459SDaniele Ceraolo Spurio int intel_gt_runtime_resume(struct intel_gt *gt)
3899dfe3459SDaniele Ceraolo Spurio {
3900cfab4cbSHuang, Sean Z int ret;
3910cfab4cbSHuang, Sean Z
392639f2f24SVenkata Sandeep Dhanalakota GT_TRACE(gt, "\n");
3939dfe3459SDaniele Ceraolo Spurio intel_gt_init_swizzling(gt);
394dec9cf9eSChris Wilson intel_ggtt_restore_fences(gt->ggtt);
3959dfe3459SDaniele Ceraolo Spurio
3960cfab4cbSHuang, Sean Z ret = intel_uc_runtime_resume(>->uc);
3970cfab4cbSHuang, Sean Z if (ret)
3980cfab4cbSHuang, Sean Z return ret;
3990cfab4cbSHuang, Sean Z
400a2ae2962SNirmoy Das intel_gt_bind_context_set_ready(gt);
4010cfab4cbSHuang, Sean Z return 0;
4029dfe3459SDaniele Ceraolo Spurio }
403c1132367SAndi Shyti
__intel_gt_get_awake_time(const struct intel_gt * gt)4048c3b1ba0SChris Wilson static ktime_t __intel_gt_get_awake_time(const struct intel_gt *gt)
4058c3b1ba0SChris Wilson {
4068c3b1ba0SChris Wilson ktime_t total = gt->stats.total;
4078c3b1ba0SChris Wilson
4088c3b1ba0SChris Wilson if (gt->stats.active)
4098c3b1ba0SChris Wilson total = ktime_add(total,
4108c3b1ba0SChris Wilson ktime_sub(ktime_get(), gt->stats.start));
4118c3b1ba0SChris Wilson
4128c3b1ba0SChris Wilson return total;
4138c3b1ba0SChris Wilson }
4148c3b1ba0SChris Wilson
intel_gt_get_awake_time(const struct intel_gt * gt)4158c3b1ba0SChris Wilson ktime_t intel_gt_get_awake_time(const struct intel_gt *gt)
4168c3b1ba0SChris Wilson {
4178c3b1ba0SChris Wilson unsigned int seq;
4188c3b1ba0SChris Wilson ktime_t total;
4198c3b1ba0SChris Wilson
4208c3b1ba0SChris Wilson do {
4218c3b1ba0SChris Wilson seq = read_seqcount_begin(>->stats.lock);
4228c3b1ba0SChris Wilson total = __intel_gt_get_awake_time(gt);
4238c3b1ba0SChris Wilson } while (read_seqcount_retry(>->stats.lock, seq));
4248c3b1ba0SChris Wilson
4258c3b1ba0SChris Wilson return total;
4268c3b1ba0SChris Wilson }
4278c3b1ba0SChris Wilson
428c1132367SAndi Shyti #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
429c1132367SAndi Shyti #include "selftest_gt_pm.c"
430c1132367SAndi Shyti #endif
431