Searched refs:gfx_table (Results 1 – 14 of 14) sorted by relevance
600 dpm_table = &(data->dpm_table.gfx_table); in vega20_setup_gfxclk_dpm_table()666 dpm_table = &(data->dpm_table.gfx_table); in vega20_setup_default_dpm_tables()1481 &(data->dpm_table.gfx_table); in vega20_get_sclk_od()1483 &(data->golden_dpm_table.gfx_table); in vega20_get_sclk_od()1500 &(data->golden_dpm_table.gfx_table); in vega20_set_sclk_od()1571 struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table); in vega20_populate_umdpstate_clocks() local1574 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL && in vega20_populate_umdpstate_clocks()1576 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value; in vega20_populate_umdpstate_clocks()1579 hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value; in vega20_populate_umdpstate_clocks()1583 hwmgr->pstate_sclk_peak = gfx_table->dpm_levels[gfx_table->count - 1].value; in vega20_populate_umdpstate_clocks()[all …]
667 dpm_table = &(data->dpm_table.gfx_table); in vega12_setup_default_dpm_tables()788 struct vega12_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);1041 struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table); in vega12_populate_umdpstate_clocks()1166 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level; in vega12_upload_dpm_min_level()1257 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level; in vega12_upload_dpm_max_level()1661 soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table)); in vega12_force_dpm_highest()1663 data->dpm_table.gfx_table.dpm_state.soft_min_level = in vega12_force_dpm_highest()1664 data->dpm_table.gfx_table.dpm_state.soft_max_level = in vega12_force_dpm_highest()1665 data->dpm_table.gfx_table.dpm_levels[soft_level].value; in vega12_force_dpm_highest()1690 soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); in vega12_force_dpm_lowest()[all …]
1361 dpm_table = &(data->dpm_table.gfx_table); in vega10_setup_default_dpm_tables()1733 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); in vega10_populate_all_graphic_levels()3439 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_find_dpm_states_clocks_in_dpm_table()3495 for (count = 0; count < dpm_table->gfx_table.count; count++) in vega10_populate_and_upload_sclk_mclk_dpm_levels()3496 dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk; in vega10_populate_and_upload_sclk_mclk_dpm_levels()3579 &(data->dpm_table.gfx_table), in vega10_trim_dpm_states()3649 data->dpm_table.gfx_table.dpm_state.soft_min_level) { in vega10_upload_dpm_bootup_level()3655 data->dpm_table.gfx_table.dpm_state.soft_min_level = in vega10_upload_dpm_bootup_level()3707 data->dpm_table.gfx_table.dpm_state.soft_max_level) { in vega10_upload_dpm_max_level()3712 data->dpm_table.gfx_table.dpm_state.soft_max_level = in vega10_upload_dpm_max_level()[all …]
126 struct vega12_single_dpm_table gfx_table; member
148 struct vega10_single_dpm_table gfx_table; member
179 struct vega20_single_dpm_table gfx_table; member
61 struct aldebaran_single_dpm_table gfx_table; member
594 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v13_0_0_set_default_dpm_table()890 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v13_0_0_get_dpm_ultimate_freq()1212 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); in smu_v13_0_0_print_clk_levels()2003 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); in smu_v13_0_0_force_clk_levels()2306 struct smu_13_0_dpm_table *gfx_table = in smu_v13_0_0_populate_umd_state_clk() local2307 &dpm_context->dpm_tables.gfx_table; in smu_v13_0_0_populate_umd_state_clk()2325 pstate_table->gfxclk_pstate.min = gfx_table->min; in smu_v13_0_0_populate_umd_state_clk()2327 (driver_clocks.GameClockAc < gfx_table->max)) in smu_v13_0_0_populate_umd_state_clk()2330 pstate_table->gfxclk_pstate.peak = gfx_table->max; in smu_v13_0_0_populate_umd_state_clk()2348 driver_clocks.BaseClockAc < gfx_table->max) in smu_v13_0_0_populate_umd_state_clk()[all …]
1588 struct smu_13_0_dpm_table *gfx_table = in smu_v13_0_set_performance_level() local1589 &dpm_context->dpm_tables.gfx_table; in smu_v13_0_set_performance_level()1614 sclk_min = sclk_max = gfx_table->max; in smu_v13_0_set_performance_level()1622 sclk_min = sclk_max = gfx_table->min; in smu_v13_0_set_performance_level()1630 sclk_min = gfx_table->min; in smu_v13_0_set_performance_level()1631 sclk_max = gfx_table->max; in smu_v13_0_set_performance_level()
61 struct arcturus_single_dpm_table gfx_table; member
1862 struct smu_11_0_dpm_table *gfx_table = in smu_v11_0_set_performance_level() local1863 &dpm_context->dpm_tables.gfx_table; in smu_v11_0_set_performance_level()1879 sclk_min = sclk_max = gfx_table->max; in smu_v11_0_set_performance_level()1884 sclk_min = sclk_max = gfx_table->min; in smu_v11_0_set_performance_level()1889 sclk_min = gfx_table->min; in smu_v11_0_set_performance_level()1890 sclk_max = gfx_table->max; in smu_v11_0_set_performance_level()
992 dpm_table = &dpm_context->dpm_tables.gfx_table; in navi10_set_default_dpm_table()1714 struct smu_11_0_dpm_table *gfx_table = in navi10_populate_umd_state_clk() local1715 &dpm_context->dpm_tables.gfx_table; in navi10_populate_umd_state_clk()1725 pstate_table->gfxclk_pstate.min = gfx_table->min; in navi10_populate_umd_state_clk()1769 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value; in navi10_populate_umd_state_clk()1780 if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK && in navi10_populate_umd_state_clk()
524 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v14_0_2_set_default_dpm_table()808 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v14_0_2_get_dpm_ultimate_freq()1073 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); in smu_v14_0_2_print_clk_levels()1398 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); in smu_v14_0_2_force_clk_levels()1586 struct smu_14_0_dpm_table *gfx_table = in smu_v14_0_2_populate_umd_state_clk() local1587 &dpm_context->dpm_tables.gfx_table; in smu_v14_0_2_populate_umd_state_clk()1605 pstate_table->gfxclk_pstate.min = gfx_table->min; in smu_v14_0_2_populate_umd_state_clk()1607 (driver_clocks.GameClockAc < gfx_table->max)) in smu_v14_0_2_populate_umd_state_clk()1610 pstate_table->gfxclk_pstate.peak = gfx_table->max; in smu_v14_0_2_populate_umd_state_clk()1628 driver_clocks.BaseClockAc < gfx_table->max) in smu_v14_0_2_populate_umd_state_clk()[all …]
1250 struct smu_14_0_dpm_table *gfx_table = in smu_v14_0_set_performance_level() local1251 &dpm_context->dpm_tables.gfx_table; in smu_v14_0_set_performance_level()1276 sclk_min = sclk_max = gfx_table->max; in smu_v14_0_set_performance_level()1284 sclk_min = sclk_max = gfx_table->min; in smu_v14_0_set_performance_level()1292 sclk_min = gfx_table->min; in smu_v14_0_set_performance_level()1293 sclk_max = gfx_table->max; in smu_v14_0_set_performance_level()