Searched refs:er32 (Results 1 – 12 of 12) sorted by relevance
52 reg = er32(STATUS); in e1000_set_lan_id_multi_port_pcie()360 er32(CRCERRS); in e1000e_clear_hw_cntrs_base()361 er32(SYMERRS); in e1000e_clear_hw_cntrs_base()362 er32(MPC); in e1000e_clear_hw_cntrs_base()363 er32(SCC); in e1000e_clear_hw_cntrs_base()364 er32(ECOL); in e1000e_clear_hw_cntrs_base()365 er32(MCC); in e1000e_clear_hw_cntrs_base()366 er32(LATECOL); in e1000e_clear_hw_cntrs_base()367 er32(COLC); in e1000e_clear_hw_cntrs_base()368 er32(DC); in e1000e_clear_hw_cntrs_base()[all …]
123 u32 eecd = er32(EECD); in e1000_init_nvm_params_82571()250 mac->arc_subsystem_valid = !!(er32(FWSM) & in e1000_init_mac_params_82571()278 swsm2 = er32(SWSM2); in e1000_init_mac_params_82571()295 swsm = er32(SWSM); in e1000_init_mac_params_82571()317 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; in e1000_get_variants_82571()452 swsm = er32(SWSM); in e1000_get_hw_semaphore_82571()466 swsm = er32(SWSM); in e1000_get_hw_semaphore_82571()470 if (er32(SWSM) & E1000_SWSM_SWESMBI) in e1000_get_hw_semaphore_82571()496 swsm = er32(SWSM); in e1000_put_hw_semaphore_82571()513 extcnf_ctrl = er32(EXTCNF_CTRL); in e1000_get_hw_semaphore_82573()[all …]
73 u32 eecd = er32(EECD); in e1000_init_nvm_params_80003es2lan()141 mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK); in e1000_init_mac_params_80003es2lan()284 swfw_sync = er32(SW_FW_SYNC); in e1000_acquire_swfw_sync_80003es2lan()324 swfw_sync = er32(SW_FW_SYNC); in e1000_release_swfw_sync_80003es2lan()500 if (er32(EEMNGCTL) & mask) in e1000_get_cfg_done_80003es2lan()684 ctrl = er32(CTRL); in e1000_reset_hw_80003es2lan()716 er32(ICR); in e1000_reset_hw_80003es2lan()776 reg_data = er32(TXDCTL(0)); in e1000_init_hw_80003es2lan()782 reg_data = er32(TXDCTL(1)); in e1000_init_hw_80003es2lan()788 reg_data = er32(TCTL); in e1000_init_hw_80003es2lan()[all …]
49 hicr = er32(HICR); in e1000_mng_enable_host_if()56 hicr = er32(HICR); in e1000_mng_enable_host_if()79 u32 fwsm = er32(FWSM); in e1000e_check_mng_mode_generic()278 hicr = er32(HICR); in e1000e_mng_write_dhcp_info()296 manc = er32(MANC); in e1000e_enable_mng_pass_thru()302 fwsm = er32(FWSM); in e1000e_enable_mng_pass_thru()303 factps = er32(FACTPS); in e1000e_enable_mng_pass_thru()314 factps = er32(FACTPS); in e1000e_enable_mng_pass_thru()
103 tsync_ctrl = er32(TSYNCTXCTL); in e1000e_phc_get_syncdevicetime()109 tsync_ctrl = er32(TSYNCTXCTL); in e1000e_phc_get_syncdevicetime()117 dev_cycles = er32(SYSSTMPH); in e1000e_phc_get_syncdevicetime()119 dev_cycles |= er32(SYSSTMPL); in e1000e_phc_get_syncdevicetime()124 sys_cycles = er32(PLTSTMPH); in e1000e_phc_get_syncdevicetime()126 sys_cycles |= er32(PLTSTMPL); in e1000e_phc_get_syncdevicetime()284 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) in e1000e_ptp_init()296 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) in e1000e_ptp_init()
48 manc = er32(MANC); in e1000e_check_reset_block_generic()161 mdic = er32(MDIC); in e1000e_read_phy_reg_mdic()241 mdic = er32(MDIC); in e1000e_write_phy_reg_mdic()514 kmrnctrlsta = er32(KMRNCTRLSTA); in __e1000_read_kmrn_reg()1476 ctrl = er32(CTRL); in e1000e_phy_force_speed_duplex_setup()2154 ctrl = er32(CTRL); in e1000e_phy_hw_reset_generic()2694 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) in e1000_access_phy_wakeup_reg_bm()
330 u32 manc = er32(MANC); in e1000_init_manageability()344 u32 manc = er32(MANC); in e1000_release_manageability()450 if (er32(MANC) & E1000_MANC_SMBUS_EN) in e1000_power_down_phy()488 rctl = er32(RCTL); in e1000_down()495 tctl = er32(TCTL); in e1000_down()606 pba = er32(PBA); in e1000_reset()682 u32 ctrl = er32(CTRL); in e1000_reset()1131 if (er32(STATUS) & E1000_STATUS_FUNC_1) { in e1000_probe()1158 if (er32(STATUS) & E1000_STATUS_FUNC_1) in e1000_probe()1652 tctl = er32(TCTL); in e1000_configure_tx()[all …]
28 #define er32(reg) \ macro69 #define E1000_WRITE_FLUSH() er32(STATUS)
189 #define er32(reg) ioread32(ioaddr + (reg)) macro415 ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800); in epic_init_one()471 ew32(NVCTL, er32(NVCTL) & ~0x483c); in epic_init_one()531 #define eeprom_delay() er32(EECTL)549 er32(INTMASK); in __epic_pci_commit()577 (er32(EECTL) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD); in read_eeprom()595 retval = (retval << 1) | ((er32(EECTL) & EE_DATA_READ) ? 1 : 0); in read_eeprom()618 if ((er32(MIICtrl) & MII_READOP) == 0) { in mdio_read()641 if ((er32(MIICtrl) & MII_WRITEOP) == 0) in mdio_write()680 ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800); in epic_open()[all …]
76 #define er32(reg) readl(hw->hw_addr + E1000_##reg) macro82 #define e1e_flush() er32(STATUS)
81 status = er32(STATUS); in e1000_get_link_up_info_vf()114 ctrl = er32(CTRL); in e1000_reset_hw_vf()399 if (!(er32(STATUS) & E1000_STATUS_LU)) in e1000_check_for_link_vf()
122 u32 v2p_mailbox = er32(V2PMAILBOX(0)); in e1000_read_v2p_mailbox()