| /linux/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop2_reg.c | 693 .en_reg = 0,
700 .en_reg = 0,
707 .en_reg = RK3568_VP_DSP_CTRL,
714 .en_reg = RK3568_VP_DSP_CTRL,
721 .en_reg = RK3568_VP_DSP_CTRL,
729 .en_reg = RK3568_CLUSTER_WIN_CTRL0,
736 .en_reg = RK3568_CLUSTER_WIN_CTRL0,
743 .en_reg = RK3568_SMART_REGION0_CTRL,
750 .en_reg = RK3568_SMART_REGION0_CTRL,
757 .en_reg = RK3568_SMART_REGION0_CTRL,
[all …]
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| /linux/drivers/clk/ |
| H A D | clk-vt8500.c | 24 void __iomem *en_reg; member
83 en_val = readl(cdev->en_reg); in vt8500_dclk_enable()
85 writel(en_val, cdev->en_reg); in vt8500_dclk_enable()
99 en_val = readl(cdev->en_reg); in vt8500_dclk_disable()
101 writel(en_val, cdev->en_reg); in vt8500_dclk_disable()
109 u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit)); in vt8500_dclk_is_enabled()
226 u32 en_reg, div_reg; in vtwm_device_clk_init() local
244 rc = of_property_read_u32(node, "enable-reg", &en_reg); in vtwm_device_clk_init()
246 dev_clk->en_reg = pmc_base + en_reg; in vtwm_device_clk_init()
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| /linux/drivers/irqchip/ |
| H A D | irq-digicolor.c | 58 unsigned en_reg, unsigned ack_reg) in digicolor_set_gc() argument
65 gc->chip_types[0].regs.mask = en_reg; in digicolor_set_gc()
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| /linux/include/linux/mfd/mt6358/ |
| H A D | core.h | 12 unsigned int en_reg; member
149 .en_reg = MT6358_##sp##_TOP_INT_CON0, \
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| /linux/drivers/regulator/ |
| H A D | tps65090-regulator.c | 200 #define tps65090_REG_FIXEDV(_id, _sname, en_reg, _en_bits, _volt, _ops) \ argument
201 tps65090_REG_DESC(_id, _sname, en_reg, _en_bits, 1, _volt, _ops)
203 #define tps65090_REG_SWITCH(_id, _sname, en_reg, _en_bits, _ops) \ argument
204 tps65090_REG_DESC(_id, _sname, en_reg, _en_bits, 0, 0, _ops)
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| H A D | sc2731-regulator.c | 130 #define SC2731_REGU_LINEAR(_id, en_reg, en_mask, vreg, vmask, \ argument
143 .enable_reg = en_reg, \
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| H A D | ltc3676.c | 195 #define LTC3676_REG(_id, _name, _ops, en_reg, en_bit, dvba_reg, dvb_mask) \ argument
212 .enable_reg = (en_reg), \
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| H A D | mt6363-regulator.c | 118 #define MT6363_BUCK(match, vreg, min, max, step, en_reg, lp_reg, \ argument
132 .enable_reg = en_reg, \
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| /linux/include/linux/mfd/mt6357/ |
| H A D | core.h | 112 .en_reg = MT6357_##sp##_TOP_INT_CON0, \
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| /linux/include/linux/mfd/mt6359/ |
| H A D | core.h | 126 .en_reg = MT6359_##sp##_TOP_INT_CON0, \
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| /linux/arch/mips/cavium-octeon/ |
| H A D | octeon-irq.c | 2133 u64 en_reg; member
2150 en = cvmx_read_csr(host_data->en_reg); in octeon_irq_cib_enable()
2152 cvmx_write_csr(host_data->en_reg, en); in octeon_irq_cib_enable()
2164 en = cvmx_read_csr(host_data->en_reg); in octeon_irq_cib_disable()
2166 cvmx_write_csr(host_data->en_reg, en); in octeon_irq_cib_disable()
2256 en = cvmx_read_csr(host_data->en_reg); in octeon_irq_cib_handler()
2271 en = cvmx_read_csr(host_data->en_reg); in octeon_irq_cib_handler()
2273 cvmx_write_csr(host_data->en_reg, en); in octeon_irq_cib_handler()
2324 host_data->en_reg = (u64)phys_to_virt(res.start); in octeon_irq_init_cib()
2343 cvmx_write_csr(host_data->en_reg, 0); /* disable all IRQs */ in octeon_irq_init_cib()
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt8188-apmixedsys.c | 55 .en_reg = _en_reg, \
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| H A D | clk-mt8195-apmixedsys.c | 56 .en_reg = _en_reg, \
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| H A D | clk-pll.c | 347 if (data->en_reg) in mtk_clk_register_pll_ops()
348 pll->en_addr = base + data->en_reg; in mtk_clk_register_pll_ops()
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| H A D | clk-mt8196-vlpckgen.c | 161 .en_reg = VLP_PLLEN_ALL, \
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