Searched refs:dramclk_khz (Results 1 – 10 of 10) sorted by relevance
140 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) in dcn201_update_clocks()141 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; in dcn201_update_clocks()
448 else if (a->dramclk_khz != b->dramclk_khz) in dcn60_are_clock_states_equal()858 dramclk_khz_override = new_clocks->dramclk_khz; in dcn60_auto_dpm_test_log()878 new_clocks->dramclk_khz > 0 && in dcn60_auto_dpm_test_log()1411 new_clocks.dramclk_khz = context->bw_ctx.bw.dcn.clk.dramclk_khz; in dcn60_set_hard_min_memclk()1415 new_clocks.dramclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn60_set_hard_min_memclk()1416 new_clocks.idle_dramclk_khz = new_clocks.dramclk_khz; in dcn60_set_hard_min_memclk()
1283 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) { in dcn35_update_clocks_fpga()1284 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz; in dcn35_update_clocks_fpga()
1601 dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ? in dm_helpers_dp_handle_test_pattern_request()1603 dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz; in dm_helpers_dp_handle_test_pattern_request()
1263 if (dc->clk_mgr->clks.dramclk_khz <= softmax_memclk_khz && in dcn30_prepare_bandwidth()1264 context->bw_ctx.bw.dcn.clk.dramclk_khz > softmax_memclk_khz) in dcn30_prepare_bandwidth()
60 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn50_initialize_min_clocks()
762 int dramclk_khz; member
1900 unsigned int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000; in dcn60_get_power_profile()
1943 unsigned int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000; in dcn401_get_power_profile()
6812 funcMin = (dc->clk_mgr->clks.dramclk_khz + 999) / 1000; in dc_enable_dcmode_clk_limit()