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Searched refs:dpm_table (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c611 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) in vega12_setup_single_dpm_table() argument
621 dpm_table->count = num_of_levels; in vega12_setup_single_dpm_table()
628 dpm_table->dpm_levels[i].value = clk; in vega12_setup_single_dpm_table()
629 dpm_table->dpm_levels[i].enabled = true; in vega12_setup_single_dpm_table()
648 struct vega12_single_dpm_table *dpm_table; in vega12_setup_default_dpm_tables() local
651 memset(&data->dpm_table, 0, sizeof(data->dpm_table)); in vega12_setup_default_dpm_tables()
654 dpm_table = &(data->dpm_table.soc_table); in vega12_setup_default_dpm_tables()
656 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK); in vega12_setup_default_dpm_tables()
661 dpm_table->count = 1; in vega12_setup_default_dpm_tables()
662 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; in vega12_setup_default_dpm_tables()
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H A Dvega20_hwmgr.c569 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) in vega20_setup_single_dpm_table() argument
579 dpm_table->count = num_of_levels; in vega20_setup_single_dpm_table()
586 dpm_table->dpm_levels[i].value = clk; in vega20_setup_single_dpm_table()
587 dpm_table->dpm_levels[i].enabled = true; in vega20_setup_single_dpm_table()
597 struct vega20_single_dpm_table *dpm_table; in vega20_setup_gfxclk_dpm_table() local
600 dpm_table = &(data->dpm_table.gfx_table); in vega20_setup_gfxclk_dpm_table()
602 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); in vega20_setup_gfxclk_dpm_table()
607 dpm_table->count = 1; in vega20_setup_gfxclk_dpm_table()
608 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; in vega20_setup_gfxclk_dpm_table()
618 struct vega20_single_dpm_table *dpm_table; in vega20_setup_memclk_dpm_table() local
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H A Dvega12_hwmgr.h313 struct vega12_dpm_table dpm_table; member
H A Dvega10_hwmgr.h311 struct vega10_dpm_table dpm_table; member
H A Dvega20_hwmgr.h435 struct vega20_dpm_table dpm_table; member
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dfiji_smumgr.c490 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in fiji_populate_bapm_parameters_in_dpm_table() local
502 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
504 dpm_table->TargetTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
511 dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp); in fiji_populate_bapm_parameters_in_dpm_table()
512 dpm_table->GpuTjHyst = 8; in fiji_populate_bapm_parameters_in_dpm_table()
514 dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase; in fiji_populate_bapm_parameters_in_dpm_table()
517 dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
519 dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
521 dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
523 dpm_table->TemperatureLimitLiquid2 = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
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H A Diceland_smumgr.c767 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_smc_link_level() local
772 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in iceland_populate_smc_link_level()
774 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in iceland_populate_smc_link_level()
776 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in iceland_populate_smc_link_level()
788 (uint8_t)dpm_table->pcie_speed_table.count; in iceland_populate_smc_link_level()
790 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in iceland_populate_smc_link_level()
963 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_all_graphic_levels() local
980 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
982 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
996 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels()
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H A Dci_smumgr.c476 struct smu7_dpm_table *dpm_table = &data->dpm_table; in ci_populate_all_graphic_levels() local
486 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
488 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
494 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
501 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
503 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
719 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in ci_populate_bapm_parameters_in_dpm_table() local
725 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256)); in ci_populate_bapm_parameters_in_dpm_table()
726 dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256)); in ci_populate_bapm_parameters_in_dpm_table()
728 dpm_table->DTETjOffset = 0; in ci_populate_bapm_parameters_in_dpm_table()
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H A Dvegam_smumgr.c574 struct smu7_dpm_table *dpm_table = &data->dpm_table; in vegam_populate_smc_link_level() local
579 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in vegam_populate_smc_link_level()
581 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in vegam_populate_smc_link_level()
583 dpm_table->pcie_speed_table.dpm_levels[i].param1); in vegam_populate_smc_link_level()
591 (uint8_t)dpm_table->pcie_speed_table.count; in vegam_populate_smc_link_level()
595 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in vegam_populate_smc_link_level()
868 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in vegam_populate_all_graphic_levels() local
872 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in vegam_populate_all_graphic_levels()
888 for (i = 0; i < dpm_table->sclk_table.count; i++) { in vegam_populate_all_graphic_levels()
891 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
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H A Dtonga_smumgr.c510 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_smc_link_level() local
515 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in tonga_populate_smc_link_level()
517 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in tonga_populate_smc_link_level()
519 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in tonga_populate_smc_link_level()
531 (uint8_t)dpm_table->pcie_speed_table.count; in tonga_populate_smc_link_level()
533 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in tonga_populate_smc_link_level()
691 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_all_graphic_levels() local
693 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count; in tonga_populate_all_graphic_levels()
710 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
712 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
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H A Dpolaris10_smumgr.c820 struct smu7_dpm_table *dpm_table = &data->dpm_table; in polaris10_populate_smc_link_level() local
825 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in polaris10_populate_smc_link_level()
827 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in polaris10_populate_smc_link_level()
829 dpm_table->pcie_speed_table.dpm_levels[i].param1); in polaris10_populate_smc_link_level()
837 (uint8_t)dpm_table->pcie_speed_table.count; in polaris10_populate_smc_link_level()
841 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in polaris10_populate_smc_link_level()
1040 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in polaris10_populate_all_graphic_levels() local
1044 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in polaris10_populate_all_graphic_levels()
1067 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels()
1070 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
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/linux/drivers/gpu/drm/radeon/
H A Dci_dpm.c405 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table() local
413 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
414 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
416 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
417 dpm_table->GpuTjMax = in ci_populate_bapm_parameters_in_dpm_table()
419 dpm_table->GpuTjHyst = 8; in ci_populate_bapm_parameters_in_dpm_table()
421 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; in ci_populate_bapm_parameters_in_dpm_table()
424 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); in ci_populate_bapm_parameters_in_dpm_table()
425 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); in ci_populate_bapm_parameters_in_dpm_table()
427 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
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H A Dci_dpm.h193 struct ci_dpm_table dpm_table; member