| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega12_hwmgr.c | 611 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) in vega12_setup_single_dpm_table() argument
621 dpm_table->count = num_of_levels; in vega12_setup_single_dpm_table()
628 dpm_table->dpm_levels[i].value = clk; in vega12_setup_single_dpm_table()
629 dpm_table->dpm_levels[i].enabled = true; in vega12_setup_single_dpm_table()
648 struct vega12_single_dpm_table *dpm_table; in vega12_setup_default_dpm_tables() local
651 memset(&data->dpm_table, 0, sizeof(data->dpm_table)); in vega12_setup_default_dpm_tables()
654 dpm_table = &(data->dpm_table.soc_table); in vega12_setup_default_dpm_tables()
656 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK); in vega12_setup_default_dpm_tables()
661 dpm_table->count = 1; in vega12_setup_default_dpm_tables()
662 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; in vega12_setup_default_dpm_tables()
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| H A D | vega20_hwmgr.c | 569 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) in vega20_setup_single_dpm_table() argument
579 dpm_table->count = num_of_levels; in vega20_setup_single_dpm_table()
586 dpm_table->dpm_levels[i].value = clk; in vega20_setup_single_dpm_table()
587 dpm_table->dpm_levels[i].enabled = true; in vega20_setup_single_dpm_table()
597 struct vega20_single_dpm_table *dpm_table; in vega20_setup_gfxclk_dpm_table() local
600 dpm_table = &(data->dpm_table.gfx_table); in vega20_setup_gfxclk_dpm_table()
602 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); in vega20_setup_gfxclk_dpm_table()
607 dpm_table->count = 1; in vega20_setup_gfxclk_dpm_table()
608 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; in vega20_setup_gfxclk_dpm_table()
618 struct vega20_single_dpm_table *dpm_table; in vega20_setup_memclk_dpm_table() local
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| H A D | vega10_hwmgr.c | 1240 struct vega10_single_dpm_table *dpm_table, in vega10_setup_default_single_dpm_table() argument
1245 dpm_table->count = 0; in vega10_setup_default_single_dpm_table()
1248 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= in vega10_setup_default_single_dpm_table()
1250 dpm_table->dpm_levels[dpm_table->count].value = in vega10_setup_default_single_dpm_table()
1252 dpm_table->dpm_levels[dpm_table->count].enabled = true; in vega10_setup_default_single_dpm_table()
1253 dpm_table->count++; in vega10_setup_default_single_dpm_table()
1260 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table); in vega10_setup_default_pcie_table()
1311 struct vega10_single_dpm_table *dpm_table; in vega10_setup_default_dpm_tables() local
1353 dpm_table = &(data->dpm_table.soc_table); in vega10_setup_default_dpm_tables()
1355 dpm_table, in vega10_setup_default_dpm_tables()
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| H A D | smu7_hwmgr.c | 662 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, in smu7_setup_default_pcie_table()
673 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, in smu7_setup_default_pcie_table()
679 data->dpm_table.pcie_speed_table.count = max_entry - 1; in smu7_setup_default_pcie_table()
683 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, in smu7_setup_default_pcie_table()
688 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, in smu7_setup_default_pcie_table()
693 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, in smu7_setup_default_pcie_table()
698 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, in smu7_setup_default_pcie_table()
703 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, in smu7_setup_default_pcie_table()
708 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, in smu7_setup_default_pcie_table()
714 data->dpm_table.pcie_speed_table.count = 6; in smu7_setup_default_pcie_table()
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| H A D | smu_helper.c | 350 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_reset_single_dpm_table() local
352 dpm_table->count = count > max ? max : count; in phm_reset_single_dpm_table()
354 for (i = 0; i < dpm_table->count; i++) in phm_reset_single_dpm_table()
355 dpm_table->dpm_level[i].enabled = false; in phm_reset_single_dpm_table()
365 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_setup_pcie_table_entry() local
366 dpm_table->dpm_level[index].value = pcie_gen; in phm_setup_pcie_table_entry()
367 dpm_table->dpm_level[index].param1 = pcie_lanes; in phm_setup_pcie_table_entry()
368 dpm_table->dpm_level[index].enabled = 1; in phm_setup_pcie_table_entry()
375 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_get_dpm_level_enable_mask_value() local
377 for (i = dpm_table->count; i > 0; i--) { in phm_get_dpm_level_enable_mask_value()
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| H A D | smu7_hwmgr.h | 214 struct smu7_dpm_table dpm_table; member
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| H A D | vega12_hwmgr.h | 313 struct vega12_dpm_table dpm_table; member
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| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | fiji_smumgr.c | 490 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in fiji_populate_bapm_parameters_in_dpm_table() local
502 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
504 dpm_table->TargetTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
511 dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp); in fiji_populate_bapm_parameters_in_dpm_table()
512 dpm_table->GpuTjHyst = 8; in fiji_populate_bapm_parameters_in_dpm_table()
514 dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase; in fiji_populate_bapm_parameters_in_dpm_table()
517 dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
519 dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
521 dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
523 dpm_table->TemperatureLimitLiquid2 = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
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| H A D | iceland_smumgr.c | 767 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_smc_link_level() local
772 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in iceland_populate_smc_link_level()
774 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in iceland_populate_smc_link_level()
776 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in iceland_populate_smc_link_level()
788 (uint8_t)dpm_table->pcie_speed_table.count; in iceland_populate_smc_link_level()
790 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in iceland_populate_smc_link_level()
963 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_all_graphic_levels() local
980 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
982 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
996 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels()
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| H A D | ci_smumgr.c | 476 struct smu7_dpm_table *dpm_table = &data->dpm_table; in ci_populate_all_graphic_levels() local
486 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
488 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
494 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
501 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
503 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
720 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in ci_populate_bapm_parameters_in_dpm_table() local
726 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256)); in ci_populate_bapm_parameters_in_dpm_table()
727 dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256)); in ci_populate_bapm_parameters_in_dpm_table()
729 dpm_table->DTETjOffset = 0; in ci_populate_bapm_parameters_in_dpm_table()
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| H A D | vegam_smumgr.c | 574 struct smu7_dpm_table *dpm_table = &data->dpm_table; in vegam_populate_smc_link_level() local
579 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in vegam_populate_smc_link_level()
581 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in vegam_populate_smc_link_level()
583 dpm_table->pcie_speed_table.dpm_levels[i].param1); in vegam_populate_smc_link_level()
591 (uint8_t)dpm_table->pcie_speed_table.count; in vegam_populate_smc_link_level()
595 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in vegam_populate_smc_link_level()
868 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in vegam_populate_all_graphic_levels() local
872 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in vegam_populate_all_graphic_levels()
888 for (i = 0; i < dpm_table->sclk_table.count; i++) { in vegam_populate_all_graphic_levels()
891 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
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| H A D | tonga_smumgr.c | 510 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_smc_link_level() local
515 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in tonga_populate_smc_link_level()
517 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in tonga_populate_smc_link_level()
519 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in tonga_populate_smc_link_level()
531 (uint8_t)dpm_table->pcie_speed_table.count; in tonga_populate_smc_link_level()
533 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in tonga_populate_smc_link_level()
691 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_all_graphic_levels() local
693 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count; in tonga_populate_all_graphic_levels()
710 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
712 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
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| H A D | polaris10_smumgr.c | 820 struct smu7_dpm_table *dpm_table = &data->dpm_table; in polaris10_populate_smc_link_level() local
825 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in polaris10_populate_smc_link_level()
827 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in polaris10_populate_smc_link_level()
829 dpm_table->pcie_speed_table.dpm_levels[i].param1); in polaris10_populate_smc_link_level()
837 (uint8_t)dpm_table->pcie_speed_table.count; in polaris10_populate_smc_link_level()
841 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in polaris10_populate_smc_link_level()
1040 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in polaris10_populate_all_graphic_levels() local
1044 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in polaris10_populate_all_graphic_levels()
1067 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels()
1070 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | sienna_cichlid_ppt.c | 957 struct smu_dpm_table *dpm_table; in sienna_cichlid_set_default_dpm_table() local
964 dpm_table = &dpm_context->dpm_tables.soc_table; in sienna_cichlid_set_default_dpm_table()
965 dpm_table->clk_type = SMU_SOCCLK; in sienna_cichlid_set_default_dpm_table()
970 dpm_table); in sienna_cichlid_set_default_dpm_table()
974 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; in sienna_cichlid_set_default_dpm_table()
976 dpm_table->count = 1; in sienna_cichlid_set_default_dpm_table()
977 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in sienna_cichlid_set_default_dpm_table()
978 dpm_table->dpm_levels[0].enabled = true; in sienna_cichlid_set_default_dpm_table()
982 dpm_table = &dpm_context->dpm_tables.gfx_table; in sienna_cichlid_set_default_dpm_table()
983 dpm_table->clk_type = SMU_GFXCLK; in sienna_cichlid_set_default_dpm_table()
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| H A D | navi10_ppt.c | 965 struct smu_dpm_table *dpm_table; in navi10_set_default_dpm_table() local
969 dpm_table = &dpm_context->dpm_tables.soc_table; in navi10_set_default_dpm_table()
970 dpm_table->clk_type = SMU_SOCCLK; in navi10_set_default_dpm_table()
974 dpm_table); in navi10_set_default_dpm_table()
978 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; in navi10_set_default_dpm_table()
980 dpm_table->count = 1; in navi10_set_default_dpm_table()
981 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in navi10_set_default_dpm_table()
982 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
986 dpm_table = &dpm_context->dpm_tables.gfx_table; in navi10_set_default_dpm_table()
987 dpm_table->clk_type = SMU_GFXCLK; in navi10_set_default_dpm_table()
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| H A D | arcturus_ppt.c | 359 struct smu_dpm_table *dpm_table = NULL; in arcturus_set_default_dpm_table() local
363 dpm_table = &dpm_context->dpm_tables.soc_table; in arcturus_set_default_dpm_table()
364 dpm_table->clk_type = SMU_SOCCLK; in arcturus_set_default_dpm_table()
368 dpm_table); in arcturus_set_default_dpm_table()
372 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; in arcturus_set_default_dpm_table()
374 dpm_table->count = 1; in arcturus_set_default_dpm_table()
375 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in arcturus_set_default_dpm_table()
376 dpm_table->dpm_levels[0].enabled = true; in arcturus_set_default_dpm_table()
380 dpm_table = &dpm_context->dpm_tables.gfx_table; in arcturus_set_default_dpm_table()
381 dpm_table->clk_type = SMU_GFXCLK; in arcturus_set_default_dpm_table()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| H A D | smu_v13_0_7_ppt.c | 591 struct smu_dpm_table *dpm_table; in smu_v13_0_7_set_default_dpm_table() local
595 dpm_table = &dpm_context->dpm_tables.soc_table; in smu_v13_0_7_set_default_dpm_table()
596 dpm_table->clk_type = SMU_SOCCLK; in smu_v13_0_7_set_default_dpm_table()
600 dpm_table); in smu_v13_0_7_set_default_dpm_table()
604 dpm_table->count = 1; in smu_v13_0_7_set_default_dpm_table()
605 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in smu_v13_0_7_set_default_dpm_table()
606 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_7_set_default_dpm_table()
610 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v13_0_7_set_default_dpm_table()
611 dpm_table->clk_type = SMU_GFXCLK; in smu_v13_0_7_set_default_dpm_table()
615 dpm_table); in smu_v13_0_7_set_default_dpm_table()
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| H A D | aldebaran_ppt.c | 346 struct smu_dpm_table *dpm_table; in aldebaran_get_dpm_ultimate_freq() local
353 dpm_table = &dpm_context->dpm_tables.uclk_table; in aldebaran_get_dpm_ultimate_freq()
357 dpm_table = &dpm_context->dpm_tables.gfx_table; in aldebaran_get_dpm_ultimate_freq()
360 dpm_table = &dpm_context->dpm_tables.soc_table; in aldebaran_get_dpm_ultimate_freq()
363 dpm_table = &dpm_context->dpm_tables.fclk_table; in aldebaran_get_dpm_ultimate_freq()
366 dpm_table = &dpm_context->dpm_tables.vclk_table; in aldebaran_get_dpm_ultimate_freq()
369 dpm_table = &dpm_context->dpm_tables.dclk_table; in aldebaran_get_dpm_ultimate_freq()
375 min_clk = SMU_DPM_TABLE_MIN(dpm_table); in aldebaran_get_dpm_ultimate_freq()
376 max_clk = SMU_DPM_TABLE_MAX(dpm_table); in aldebaran_get_dpm_ultimate_freq()
399 struct smu_dpm_table *dpm_table = NULL; in aldebaran_set_default_dpm_table() local
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| H A D | smu_v13_0_0_ppt.c | 563 struct smu_dpm_table *dpm_table; in smu_v13_0_0_set_default_dpm_table() local
567 dpm_table = &dpm_context->dpm_tables.soc_table; in smu_v13_0_0_set_default_dpm_table()
568 dpm_table->clk_type = SMU_SOCCLK; in smu_v13_0_0_set_default_dpm_table()
572 dpm_table); in smu_v13_0_0_set_default_dpm_table()
576 dpm_table->count = 1; in smu_v13_0_0_set_default_dpm_table()
577 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in smu_v13_0_0_set_default_dpm_table()
578 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_0_set_default_dpm_table()
582 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v13_0_0_set_default_dpm_table()
583 dpm_table->clk_type = SMU_GFXCLK; in smu_v13_0_0_set_default_dpm_table()
587 dpm_table); in smu_v13_0_0_set_default_dpm_table()
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| H A D | smu_v13_0_6_ppt.c | 255 struct smu_dpm_table *dpm_table; member
986 struct smu_dpm_table *dpm_table; in smu_v13_0_6_get_dpm_ultimate_freq() local
995 dpm_table = &dpm_context->dpm_tables.uclk_table; in smu_v13_0_6_get_dpm_ultimate_freq()
999 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v13_0_6_get_dpm_ultimate_freq()
1002 dpm_table = &dpm_context->dpm_tables.soc_table; in smu_v13_0_6_get_dpm_ultimate_freq()
1005 dpm_table = &dpm_context->dpm_tables.fclk_table; in smu_v13_0_6_get_dpm_ultimate_freq()
1008 dpm_table = &dpm_context->dpm_tables.vclk_table; in smu_v13_0_6_get_dpm_ultimate_freq()
1011 dpm_table = &dpm_context->dpm_tables.dclk_table; in smu_v13_0_6_get_dpm_ultimate_freq()
1017 min_clk = SMU_DPM_TABLE_MIN(dpm_table); in smu_v13_0_6_get_dpm_ultimate_freq()
1018 max_clk = SMU_DPM_TABLE_MAX(dpm_table); in smu_v13_0_6_get_dpm_ultimate_freq()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| H A D | smu_v14_0_2_ppt.c | 461 struct smu_dpm_table *dpm_table; in smu_v14_0_2_set_default_dpm_table() local
465 dpm_table = &dpm_context->dpm_tables.soc_table; in smu_v14_0_2_set_default_dpm_table()
466 dpm_table->clk_type = SMU_SOCCLK; in smu_v14_0_2_set_default_dpm_table()
470 dpm_table); in smu_v14_0_2_set_default_dpm_table()
474 dpm_table->count = 1; in smu_v14_0_2_set_default_dpm_table()
475 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in smu_v14_0_2_set_default_dpm_table()
476 dpm_table->dpm_levels[0].enabled = true; in smu_v14_0_2_set_default_dpm_table()
480 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v14_0_2_set_default_dpm_table()
481 dpm_table->clk_type = SMU_GFXCLK; in smu_v14_0_2_set_default_dpm_table()
485 dpm_table); in smu_v14_0_2_set_default_dpm_table()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | ci_dpm.c | 405 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table() local
413 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
414 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
416 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
417 dpm_table->GpuTjMax = in ci_populate_bapm_parameters_in_dpm_table()
419 dpm_table->GpuTjHyst = 8; in ci_populate_bapm_parameters_in_dpm_table()
421 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; in ci_populate_bapm_parameters_in_dpm_table()
424 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); in ci_populate_bapm_parameters_in_dpm_table()
425 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); in ci_populate_bapm_parameters_in_dpm_table()
427 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
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| H A D | ci_dpm.h | 193 struct ci_dpm_table dpm_table; member
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| /linux/drivers/gpu/drm/amd/pm/swsmu/ |
| H A D | smu_cmn.c | 1286 struct smu_dpm_table *dpm_table, in smu_cmn_print_dpm_clk_levels() argument
1296 if (!dpm_table || !buf) in smu_cmn_print_dpm_clk_levels()
1301 count = dpm_table->count; in smu_cmn_print_dpm_clk_levels()
1302 is_fine_grained = dpm_table->flags & SMU_DPM_TABLE_FINE_GRAINED; in smu_cmn_print_dpm_clk_levels()
1303 min_clk = SMU_DPM_TABLE_MIN(dpm_table); in smu_cmn_print_dpm_clk_levels()
1304 max_clk = SMU_DPM_TABLE_MAX(dpm_table); in smu_cmn_print_dpm_clk_levels()
1318 dpm_table->dpm_levels[i].value); in smu_cmn_print_dpm_clk_levels()
1321 dpm_table->dpm_levels[i].value, in smu_cmn_print_dpm_clk_levels()
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| H A D | smu_cmn.h | 199 struct smu_dpm_table *dpm_table,
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