| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dmub_psr.h | 40 bool (*psr_copy_settings)(struct dmub_psr *dmub, struct dc_link *link,
42 void (*psr_enable)(struct dmub_psr *dmub, bool enable, bool wait,
44 void (*psr_get_state)(struct dmub_psr *dmub, enum dc_psr_state *dc_psr_state,
46 void (*psr_set_level)(struct dmub_psr *dmub, uint16_t psr_level,
48 void (*psr_force_static)(struct dmub_psr *dmub, uint8_t panel_inst);
49 void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency,
51 void (*psr_set_sink_vtotal_in_psr_active)(struct dmub_psr *dmub,
53 void (*psr_set_power_opt)(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst);
57 void dmub_psr_destroy(struct dmub_psr **dmub);
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| /linux/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_dcn314.c | 41 #define CTX dmub
42 #define REGS dmub->regs_dcn31
64 bool dmub_dcn314_is_psrsu_supported(struct dmub_srv *dmub) in dmub_dcn314_is_psrsu_supported() argument
66 return dmub->fw_version >= DMUB_FW_VERSION(8, 0, 16); in dmub_dcn314_is_psrsu_supported()
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| H A D | dmub_dcn351.c | 12 #define CTX dmub
13 #define REGS dmub->regs_dcn35
16 void dmub_srv_dcn351_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) in dmub_srv_dcn351_regs_init() argument
18 struct dmub_srv_dcn35_regs *regs = dmub->regs_dcn35; in dmub_srv_dcn351_regs_init()
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| H A D | dmub_dcn30.h | 37 void dmub_dcn30_backdoor_load(struct dmub_srv *dmub,
41 void dmub_dcn30_setup_windows(struct dmub_srv *dmub,
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| H A D | dmub_dcn301.c | 35 #define CTX dmub
36 #define REGS dmub->regs
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| H A D | dmub_dcn303.c | 36 #define CTX dmub
37 #define REGS dmub->regs
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| H A D | dmub_dcn21.c | 35 #define CTX dmub
36 #define REGS dmub->regs
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| H A D | dmub_dcn302.c | 35 #define CTX dmub
36 #define REGS dmub->regs
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| H A D | dmub_dcn316.c | 41 #define CTX dmub
42 #define REGS dmub->regs_dcn31
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| H A D | dmub_dcn315.c | 41 #define CTX dmub
42 #define REGS dmub->regs_dcn31
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| H A D | dmub_dcn314.h | 33 bool dmub_dcn314_is_psrsu_supported(struct dmub_srv *dmub);
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| H A D | dmub_dcn351.h | 11 void dmub_srv_dcn351_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);
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| /linux/drivers/gpu/drm/amd/display/dmub/ |
| H A D | dmub_srv_stat.h | 38 enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub,
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/tests/ |
| H A D | amdgpu_dm_irq_test.c | 187 static uint32_t dm_test_dmub_get_outbox0_wptr(struct dmub_srv *dmub) in dm_test_dmub_get_outbox0_wptr() argument
192 static uint32_t dm_test_dmub_get_outbox1_wptr(struct dmub_srv *dmub) in dm_test_dmub_get_outbox1_wptr() argument
3478 struct dmub_srv *dmub; in dm_test_dmub_outbox1_low_irq_empty() local
3485 dmub = kunit_kzalloc(test, sizeof(*dmub), GFP_KERNEL); in dm_test_dmub_outbox1_low_irq_empty()
3486 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dmub); in dm_test_dmub_outbox1_low_irq_empty()
3488 dmub->hw_funcs.get_outbox0_wptr = dm_test_dmub_get_outbox0_wptr; in dm_test_dmub_outbox1_low_irq_empty()
3489 dc_dmub_srv->dmub = dmub; in dm_test_dmub_outbox1_low_irq_empty()
3512 struct dmub_srv *dmub; in dm_test_alloc_adev_outbox_notify() local
3519 dmub = kunit_kzalloc(test, sizeof(*dmub), GFP_KERNEL); in dm_test_alloc_adev_outbox_notify()
3520 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dmub); in dm_test_alloc_adev_outbox_notify()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn60/ |
| H A D | dcn60_hwseq.c | 760 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; in dcn60_init_hw()
761 …dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver > 0; in dcn60_init_hw()
762 dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver; in dcn60_init_hw()
786 volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1; in dcn60_update_cursor_offload_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn50/ |
| H A D | dcn50_hwseq.c | 749 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; in dcn50_init_hw()
750 …dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver > 0; in dcn50_init_hw()
751 dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver; in dcn50_init_hw()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_debugfs.c | 1031 if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub) in replay_capability_show()
1033 (bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported; in replay_capability_show()
2695 if (dc_dmub_srv && dc_dmub_srv->dmub) { in ips_status_show()
2698 &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw; in ips_status_show()
3542 struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub; in dmub_trace_mask_set()
3586 struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub; in dmub_trace_mask_show()
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| H A D | amdgpu_dm.c | 1125 struct dmub_srv *dmub = NULL; in amdgpu_dm_boot_time_crc_init() local
1135 dmub = adev->dm.dc->ctx->dmub_srv->dmub; in amdgpu_dm_boot_time_crc_init()
1138 if (!dmub || !dmub->hw_funcs.get_fw_boot_option) { in amdgpu_dm_boot_time_crc_init()
1143 option = dmub->hw_funcs.get_fw_boot_option(dmub); in amdgpu_dm_boot_time_crc_init()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 838 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; in dcn30_init_hw()
839 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver; in dcn30_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc.c | 1294 memcpy(color, &dc->ctx->dmub_srv->dmub->visual_confirm_color, sizeof(struct tg_color)); in dc_get_visual_confirm_for_stream()
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