| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | Makefile | 47 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
48 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
49 CFLAGS_$(AMDDALPATH)/dc/dml/dcn10/dcn10_fpu.o := $(dml_ccflags)
50 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
51 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags) $(frame_warn_flag)
52 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
53 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags) $(frame_warn_flag)
54 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
55 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags) $(frame_warn_flag)
56 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 459 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
460 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
461 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
471 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn315_update_soc_for_wm_a()
474 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()
475 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = in dcn315_update_soc_for_wm_a()
477 context->bw_ctx.dml.soc.sr_exit_time_us = in dcn315_update_soc_for_wm_a()
489 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
494 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn31_calculate_wm_and_dlg_fp()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calcs.c | 458 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); in dcn_bw_calc_rq_dlg_ttu() local
507 dml1_rq_dlg_get_rq_params(dml, rq_param, &input->pipe.src); in dcn_bw_calc_rq_dlg_ttu()
508 dml1_extract_rq_regs(dml, rq_regs, rq_param); in dcn_bw_calc_rq_dlg_ttu()
510 dml, in dcn_bw_calc_rq_dlg_ttu()
1078 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; in dcn_validate_bandwidth()
1079 context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time; in dcn_validate_bandwidth()
1294 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = in dcn_validate_bandwidth()
1296 context->bw_ctx.dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time; in dcn_validate_bandwidth()
1568 dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time; in dcn_bw_sync_calcs_and_dml()
1569 dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time; in dcn_bw_sync_calcs_and_dml()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 321 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; in dcn35_update_bw_bounding_box_fpu()
349 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, in dcn35_update_bw_bounding_box_fpu()
530 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 384;/*per guide*/ in dcn35_populate_dml_pipes_from_context_fpu()
544 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn35_populate_dml_pipes_from_context_fpu()
550 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn35_populate_dml_pipes_from_context_fpu()
553 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn35_populate_dml_pipes_from_context_fpu()
568 context->bw_ctx.dml.vba.ODMCombinePolicy = in dcn35_populate_dml_pipes_from_context_fpu()
601 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in dcn35_decide_zstate_support()
604 bool allow_z10 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z10_residency; in dcn35_decide_zstate_support()
617 (int)context->bw_ctx.dml.vba.StutterPeriod); in dcn35_decide_zstate_support()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn10/ |
| H A D | dcn10_fpu.c | 133 struct display_mode_lib *dml = &dc->dml; in dcn10_resource_construct_fp() local
135 dml->ip.max_num_dpp = 3; in dcn10_resource_construct_fp()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 355 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; in dcn351_update_bw_bounding_box_fpu()
383 dml_init_instance(&dc->dml, &dcn3_51_soc, &dcn3_51_ip, in dcn351_update_bw_bounding_box_fpu()
563 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 384;/*per guide*/ in dcn351_populate_dml_pipes_from_context_fpu()
577 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn351_populate_dml_pipes_from_context_fpu()
583 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn351_populate_dml_pipes_from_context_fpu()
586 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn351_populate_dml_pipes_from_context_fpu()
601 context->bw_ctx.dml.vba.ODMCombinePolicy = in dcn351_populate_dml_pipes_from_context_fpu()
632 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in dcn351_decide_zstate_support()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1379 struct display_mode_lib *dml = &context->bw_ctx.dml; in dcn30_set_mcif_arb_params() local
1406 dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j); in dcn30_set_mcif_arb_params()
1638 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn30_internal_validate_bw()
1644 context->bw_ctx.dml.vba.maxMpcComb = 0; in dcn30_internal_validate_bw()
1645 context->bw_ctx.dml.vba.VoltageLevel = 0; in dcn30_internal_validate_bw()
1646 context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive; in dcn30_internal_validate_bw()
1655 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1663 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn30_internal_validate_bw()
1665 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1667 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 801 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
803 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
805 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
813 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
815 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
816 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
825 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn21_fast_validate_bw()
855 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
879 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
883 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | Makefile | 25 DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link dsc resource optc dpp hubbub dccg hubp dio…
38 DC_LIBS += dml
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/ |
| H A D | dml2_internal_shared_types.h | 897 struct dml2_instance *dml; member
903 struct dml2_instance *dml; member
910 struct dml2_instance *dml; member
916 struct dml2_instance *dml; member
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1828 struct vba_vars_st *v = &context->bw_ctx.dml.vba; in dcn20_validate_apply_pipe_split_flags()
1883 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1888 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2034 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn20_fast_validate_bw()
2036 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2054 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2073 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) in dcn20_fast_validate_bw()
2083 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn20_fast_validate_bw()
2087 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2110 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1672 …const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MI… in dcn315_populate_dml_pipes_from_context()
1705 &context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB); in dcn315_populate_dml_pipes_from_context()
1709 …ired = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc); in dcn315_populate_dml_pipes_from_context()
1758 …t_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc) in dcn315_populate_dml_pipes_from_context()
1783 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn315_populate_dml_pipes_from_context()
1785 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE) in dcn315_populate_dml_pipes_from_context()
1786 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE; in dcn315_populate_dml_pipes_from_context()
1793 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn315_populate_dml_pipes_from_context()
1797 && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) { in dcn315_populate_dml_pipes_from_context()
1799 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn315_populate_dml_pipes_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 1617 …const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MI… in dcn316_populate_dml_pipes_from_context()
1667 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn316_populate_dml_pipes_from_context()
1669 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_16_MAX_DET_SIZE) in dcn316_populate_dml_pipes_from_context()
1670 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_16_MAX_DET_SIZE; in dcn316_populate_dml_pipes_from_context()
1671 ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_16_DEFAULT_DET_SIZE); in dcn316_populate_dml_pipes_from_context()
1677 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn316_populate_dml_pipes_from_context()
1680 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn316_populate_dml_pipes_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 872 ctx->dc->dml.ip.det_buffer_size_kbytes, in dcn32_hubbub_create()
873 ctx->dc->dml.ip.pixel_chunk_size_kbytes, in dcn32_hubbub_create()
874 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); in dcn32_hubbub_create()
1760 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; in dml1_validate()
1797 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dml1_validate()
2016 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false; in dcn32_populate_dml_pipes_from_context()
2018 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; in dcn32_populate_dml_pipes_from_context()
2357 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); in dcn32_resource_construct()
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| H A D | dcn32_resource_helpers.c | 711 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_subvp_vblank_admissable()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1701 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE; in dcn31_populate_dml_pipes_from_context()
1709 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn31_populate_dml_pipes_from_context()
1714 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; in dcn31_populate_dml_pipes_from_context()
1716 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn31_populate_dml_pipes_from_context()
1725 return context->bw_ctx.dml.ip.det_buffer_size_kbytes; in dcn31_get_det_buffer_size()
1805 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dcn31_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_state.c | 190 memcpy(&state->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib)); in init_state()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 866 ctx->dc->dml.ip.det_buffer_size_kbytes, in dcn321_hubbub_create()
867 ctx->dc->dml.ip.pixel_chunk_size_kbytes, in dcn321_hubbub_create()
868 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); in dcn321_hubbub_create()
1859 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); in dcn321_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 589 struct display_mode_lib dml; member
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 1468 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1); in dcn10_resource_construct()
1639 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 503 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes; in dcn30_mmhubbub_warmup()
518 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes; in dcn30_mmhubbub_warmup()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1744 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dcn314_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 1198 dml_init_instance(&dc->dml, &dcn201_soc, &dcn201_ip, DML_PROJECT_DCN201); in dcn201_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 2401 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) { in dcn20_prepare_bandwidth()
2402 compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes; in dcn20_prepare_bandwidth()
2403 …dc->optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_siz… in dcn20_prepare_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 1291 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); in dcn303_resource_construct()
|