| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ |
| H A D | fanpwm.c | 44 u32 divs, duty; in nvkm_fanpwm_get() local
47 ret = therm->func->pwm_get(therm, fan->func.line, &divs, &duty); in nvkm_fanpwm_get()
48 if (ret == 0 && divs) { in nvkm_fanpwm_get()
49 divs = max(divs, duty); in nvkm_fanpwm_get()
51 duty = divs - duty; in nvkm_fanpwm_get()
52 return (duty * 100) / divs; in nvkm_fanpwm_get()
63 u32 divs, duty; in nvkm_fanpwm_set() local
66 divs = fan->base.perf.pwm_divisor; in nvkm_fanpwm_set()
68 divs = 1; in nvkm_fanpwm_set()
70 divs = therm->func->pwm_clock(therm, fan->func.line); in nvkm_fanpwm_set()
[all …]
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| H A D | gf119.c | 68 gf119_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in gf119_fan_pwm_get() argument
76 *divs = nvkm_rd32(device, 0x00e114 + (indx * 8)); in gf119_fan_pwm_get()
81 *divs = nvkm_rd32(device, 0x0200d8) & 0x1fff; in gf119_fan_pwm_get()
90 gf119_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in gf119_fan_pwm_set() argument
97 nvkm_wr32(device, 0x00e114 + (indx * 8), divs); in gf119_fan_pwm_set()
100 nvkm_mask(device, 0x0200d8, 0x1fff, divs); /* keep the high bits */ in gf119_fan_pwm_set()
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| H A D | gm107.c | 34 gm107_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in gm107_fan_pwm_get() argument
37 *divs = nvkm_rd32(device, 0x10eb20) & 0x1fff; in gm107_fan_pwm_get()
43 gm107_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in gm107_fan_pwm_set() argument
46 nvkm_mask(device, 0x10eb10, 0x1fff, divs); /* keep the high bits */ in gm107_fan_pwm_set()
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| H A D | nv40.c | 121 nv40_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in nv40_fan_pwm_get() argument
129 *divs = (reg & 0x00007fff); in nv40_fan_pwm_get()
136 *divs = nvkm_rd32(device, 0x0015f8); in nv40_fan_pwm_get()
149 nv40_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in nv40_fan_pwm_set() argument
154 nvkm_mask(device, 0x0010f0, 0x7fff7fff, (duty << 16) | divs); in nv40_fan_pwm_set()
157 nvkm_wr32(device, 0x0015f8, divs); in nv40_fan_pwm_set()
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| H A D | nv50.c | 66 nv50_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in nv50_fan_pwm_get() argument
74 *divs = nvkm_rd32(device, 0x00e114 + (id * 8)); in nv50_fan_pwm_get()
83 nv50_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in nv50_fan_pwm_set() argument
90 nvkm_wr32(device, 0x00e114 + (id * 8), divs); in nv50_fan_pwm_set()
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| /linux/drivers/clk/ |
| H A D | clk-fsl-flexspi.c | 56 const struct clk_div_table *divs; in fsl_flexspi_clk_probe() local
58 divs = device_get_match_data(dev); in fsl_flexspi_clk_probe()
59 if (!divs) in fsl_flexspi_clk_probe()
81 reg, 0, 5, 0, divs, NULL); in fsl_flexspi_clk_probe()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | mcp77.c | 209 int divs = 0; in mcp77_clk_calc() local
213 out = calc_P(nvkm_clk_read(&clk->base, nv_clk_src_hclkm4), core, &divs); in mcp77_clk_calc()
220 clk->cctrl = divs << 16; in mcp77_clk_calc()
244 out = calc_P((core << 1), shader, &divs); in mcp77_clk_calc()
248 (divs + P2) <= 7) { in mcp77_clk_calc()
250 clk->sctrl = (divs + P2) << 16; in mcp77_clk_calc()
259 out = calc_P(core, vdec, &divs); in mcp77_clk_calc()
263 clk->vdiv = divs << 16; in mcp77_clk_calc()
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| H A D | nv50.c | 448 clk_mask(hwsq, divs, divsm, divsv); in nv50_clk_calc()
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| /linux/drivers/clk/samsung/ |
| H A D | clk-cpu.c | 67 u32 divs[4]; member
418 .divs = { 0x1800, 0x1808, 0x180c, 0x1810 },
423 .divs = { 0x1800, 0x1808, 0x180c, 0x1810 },
529 val = readl(base + regs->divs[i]); in exynos850_cpuclk_pre_rate_change()
531 writel(val, base + regs->divs[i]); in exynos850_cpuclk_pre_rate_change()
532 wait_until_divider_stable(base + regs->divs[i], E850_BUSY_MASK); in exynos850_cpuclk_pre_rate_change()
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| /linux/arch/mips/include/asm/ |
| H A D | mips-r2-to-r6-emul.h | 17 u64 divs; member
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| /linux/arch/mips/kernel/ |
| H A D | mips-r2-to-r6-emul.c | 463 MIPS_R2_STATS(divs); in div_func()
485 MIPS_R2_STATS(divs); in divu_func()
574 MIPS_R2_STATS(divs); in ddiv_func()
599 MIPS_R2_STATS(divs); in ddivu_func()
2252 (unsigned long)__this_cpu_read(mipsr2emustats.divs), in mipsr2_emul_show()
2253 (unsigned long)__this_cpu_read(mipsr2bdemustats.divs)); in mipsr2_emul_show()
2314 __this_cpu_write((mipsr2emustats).divs, 0); in mipsr2_clear_show()
2315 __this_cpu_write((mipsr2bdemustats).divs, 0); in mipsr2_clear_show()
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| /linux/drivers/clk/qcom/ |
| H A D | dispcc-sm8250.c | 1318 static struct clk_regmap_div * const divs[] = { in disp_cc_sm8250_probe() local
1336 for (i = 0; i < ARRAY_SIZE(divs); i++) { in disp_cc_sm8250_probe()
1337 divs[i]->reg -= 4; in disp_cc_sm8250_probe()
1338 divs[i]->width = 4; in disp_cc_sm8250_probe()
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-cpu.c | 104 for (i = 0; i < ARRAY_SIZE(rate->divs); i++) { in rockchip_cpuclk_set_dividers()
105 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; in rockchip_cpuclk_set_dividers()
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| H A D | clk-rk3368.c | 204 .divs = { \
214 .divs = { \
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| H A D | clk-rk3036.c | 93 .divs = { \
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| H A D | clk-rk3128.c | 92 .divs = { \
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| H A D | clk-rk3228.c | 93 .divs = { \
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| H A D | clk-rk3399.c | 341 .divs = { \
351 .divs = { \
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| H A D | clk-rv1108.c | 82 .divs = { \
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| H A D | clk-rk3328.c | 105 .divs = { \
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| H A D | clk-rk3506.c | 86 .divs = { \
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| H A D | clk-rk3288.c | 158 .divs = { \
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| H A D | clk-rk3576.c | 149 .divs = { \
157 .divs = { \
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| H A D | clk-rk3308.c | 86 .divs = { \
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| /linux/arch/m68k/ifpsp060/src/ |
| H A D | ilsp.S | 105 # divs.l #
195 tst.b POSNEG(%a6) # do divs, divu separately
198 # it was a divs.l, so ccode setting is a little more complicated...
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