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Searched refs:div_reg (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/clk/socfpga/
H A Dclk-gate-a10.c29 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
46 u32 div_reg[3]; in __socfpga_gate_init() local
77 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_gate_init()
79 socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_gate_init()
80 socfpga_clk->shift = div_reg[1]; in __socfpga_gate_init()
81 socfpga_clk->width = div_reg[2]; in __socfpga_gate_init()
83 socfpga_clk->div_reg = NULL; in __socfpga_gate_init()
H A Dclk-periph.c26 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
27 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
61 u32 div_reg[3]; in __socfpga_periph_init() local
71 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
73 periph_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in __socfpga_periph_init()
74 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
75 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
77 periph_clk->div_reg = NULL; in __socfpga_periph_init()
H A Dclk-periph-a10.c28 } else if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
29 div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
71 u32 div_reg[3]; in __socfpga_periph_init() local
81 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
83 periph_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_periph_init()
84 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
85 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
87 periph_clk->div_reg = NULL; in __socfpga_periph_init()
H A Dclk-gate-s10.c29 } else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
43 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_dbg_clk_recalc_rate()
147 if (clks->div_reg) in s10_register_gate()
148 socfpga_clk->div_reg = regbase + clks->div_reg; in s10_register_gate()
150 socfpga_clk->div_reg = NULL; in s10_register_gate()
205 if (clks->div_reg) in agilex_register_gate()
206 socfpga_clk->div_reg = regbase + clks->div_reg; in agilex_register_gate()
208 socfpga_clk->div_reg = NULL; in agilex_register_gate()
262 if (clks->div_reg) in agilex5_register_gate()
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H A Dclk-gate.c96 else if (socfpgaclk->div_reg) { in socfpga_clk_get_div()
97 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_get_div()
100 if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_get_div()
140 u32 div_reg[3]; in socfpga_gate_init() local
176 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in socfpga_gate_init()
178 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in socfpga_gate_init()
179 socfpga_clk->shift = div_reg[1]; in socfpga_gate_init()
180 socfpga_clk->width = div_reg[2]; in socfpga_gate_init()
182 socfpga_clk->div_reg = NULL; in socfpga_gate_init()
H A Dclk.h47 void __iomem *div_reg; member
59 void __iomem *div_reg; member
H A Dstratix10-clk.h68 unsigned long div_reg; member
105 unsigned long div_reg; member
/linux/drivers/clk/bcm/
H A Dclk-bcm2835.c492 u32 div_reg; member
1037 div = cprman_read(cprman, data->div_reg); in bcm2835_clock_get_rate()
1128 cprman_write(cprman, data->div_reg, div); in bcm2835_clock_set_rate()
1950 .div_reg = CM_OTPDIV,
1962 .div_reg = CM_TIMERDIV,
1973 .div_reg = CM_TSENSDIV,
1980 .div_reg = CM_TECDIV,
1989 .div_reg = CM_H264DIV,
1997 .div_reg = CM_ISPDIV,
2010 .div_reg = CM_SDCDIV,
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/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-afe-clk.c410 int div_reg; member
425 .div_reg = CLK_AUDDIV_2,
438 .div_reg = CLK_AUDDIV_2,
451 .div_reg = CLK_AUDDIV_2,
464 .div_reg = CLK_AUDDIV_2,
477 .div_reg = CLK_AUDDIV_3,
490 .div_reg = CLK_AUDDIV_2,
500 .div_reg = CLK_AUDDIV_3,
513 .div_reg = CLK_AUDDIV_3,
526 .div_reg = CLK_AUDDIV_4,
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/linux/drivers/clk/
H A Dclk-vt8500.c22 void __iomem *div_reg; member
118 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
190 writel(divisor, cdev->div_reg); in vt8500_dclk_set_rate()
226 u32 en_reg, div_reg; in vtwm_device_clk_init() local
256 rc = of_property_read_u32(node, "divisor-reg", &div_reg); in vtwm_device_clk_init()
258 dev_clk->div_reg = pmc_base + div_reg; in vtwm_device_clk_init()
H A Dclk-en7523.c97 u16 div_reg; member
191 .div_reg = REG_SPI_CLK_DIV_SEL,
287 .div_reg = REG_SPI_CLK_DIV_SEL,
673 u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg; in en7523_register_clocks()
723 u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; in en7581_register_clocks()
H A Dclk-k230.c2244 u32 div, mul, div_reg; in k230_clk_set_rate_div() local
2260 div_reg = readl(rate_self->reg + clk->div_reg_off); in k230_clk_set_rate_div()
2261 div_reg &= ~(rate_self->div_mask << rate_self->div_shift); in k230_clk_set_rate_div()
2262 div_reg |= ((div - 1) & rate_self->div_mask) << (rate_self->div_shift); in k230_clk_set_rate_div()
2263 div_reg |= BIT(rate_self->write_enable_bit); in k230_clk_set_rate_div()
2264 writel(div_reg, rate_self->reg + clk->div_reg_off); in k230_clk_set_rate_div()
2275 u32 div, mul, div_reg, mul_reg; in k230_clk_set_rate_mul_div() local
2291 div_reg = readl(rate_self->reg + clk->div_reg_off); in k230_clk_set_rate_mul_div()
2292 div_reg &= ~(rate_self->div_mask << rate_self->div_shift); in k230_clk_set_rate_mul_div()
2293 div_reg |= ((div - 1) & rate_self->div_mask) << (rate_self->div_shift); in k230_clk_set_rate_mul_div()
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H A Dclk-k210.c34 u8 div_reg; member
54 .div_reg = (_reg), \
756 if (!cfg->div_reg) in k210_clk_get_rate()
759 reg = readl(ksc->regs + cfg->div_reg); in k210_clk_get_rate()
H A Dclk-bm1880.c115 u32 div_reg; member
150 .div_reg = _div_reg, \
808 div_hws->div.reg = clks->div_reg; in bm1880_clk_register_composite()
/linux/drivers/clk/hisilicon/
H A Dclk-hi3620.c225 u32 div_reg; member
241 void __iomem *div_reg; member
371 val = readl_relaxed(mclk->div_reg); in mmc_clk_set_timing()
373 writel_relaxed(val, mclk->div_reg); in mmc_clk_set_timing()
431 mclk->div_reg = base + mmc_clk->div_reg; in hisi_register_clk_mmc()
/linux/drivers/clk/mediatek/
H A Dclk-mtk.h210 u32 div_reg; member
221 .div_reg = _reg, \
H A Dclk-mt8167.c662 .div_reg = _reg, \
H A Dclk-mt8365.c545 .div_reg = _reg, \
H A Dclk-mtk.c418 mcd->flags, base + mcd->div_reg, mcd->div_shift, in mtk_clk_register_dividers()
/linux/drivers/clk/samsung/
H A Dclk-cpu.c124 static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask) in wait_until_divider_stable() argument
129 if (!(readl(div_reg) & mask)) in wait_until_divider_stable()
133 if (!(readl(div_reg) & mask)) in wait_until_divider_stable()
/linux/drivers/clk/ingenic/
H A Dcgu.c414 u32 div_reg, div; in ingenic_clk_recalc_rate() local
421 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
422 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()