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Searched refs:div0 (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/clk/uniphier/
H A Dclk-uniphier.h110 #define UNIPHIER_CLK_DIV2(parent, div0, div1) \ argument
111 UNIPHIER_CLK_DIV(parent, div0), \
114 #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \ argument
115 UNIPHIER_CLK_DIV2(parent, div0, div1), \
118 #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \ argument
119 UNIPHIER_CLK_DIV2(parent, div0, div1), \
122 #define UNIPHIER_CLK_DIV5(parent, div0, div1, div2, div3, div4) \ argument
123 UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3), \
/linux/drivers/clk/samsung/
H A Dclk-cpu.c169 unsigned long div0; in exynos_set_safe_div() local
171 div0 = readl(base + regs->div_cpu0); in exynos_set_safe_div()
172 div0 = (div0 & ~mask) | (div & mask); in exynos_set_safe_div()
173 writel(div0, base + regs->div_cpu0); in exynos_set_safe_div()
203 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local
220 div0 = cfg_data->div0; in exynos_cpuclk_pre_rate_change()
252 div0 |= alt_div; in exynos_cpuclk_pre_rate_change()
261 writel(div0, base + regs->div_cpu0); in exynos_cpuclk_pre_rate_change()
302 div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK); in exynos_cpuclk_post_rate_change()
330 unsigned long div0, div1 = 0, mux_reg; in exynos5433_cpuclk_pre_rate_change() local
[all …]
H A Dclk-cpu.h44 unsigned long div0; member
/linux/arch/microblaze/lib/
H A Dudivsi3.S46 bgti r6, div0
51 div0: label
H A Dumodsi3.S45 bgtid r6, div0
53 div0: label
H A Ddivsi3.S37 div0: label
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgf100.c278 u32 src0, div0, div1D, div1P = 0; in calc_clk() local
286 clk0 = calc_src(clk, idx, freq, &src0, &div0); in calc_clk()
301 if (div0) { in calc_clk()
303 info->ddiv |= div0 << 8; in calc_clk()
304 info->ddiv |= div0; in calc_clk()
H A Dgk104.c292 u32 src0, div0, div1D, div1P = 0; in calc_clk() local
300 clk0 = calc_src(clk, idx, freq, &src0, &div0); in calc_clk()
315 if (div0) { in calc_clk()
317 info->ddiv |= div0; in calc_clk()
/linux/drivers/clk/x86/
H A Dclk-cgu.c395 unsigned int div0, div1, exdiv; in lgm_clk_ddiv_recalc_rate() local
398 div0 = lgm_get_clk_val(ddiv->membase, ddiv->reg, in lgm_clk_ddiv_recalc_rate()
405 do_div(prate, div0); in lgm_clk_ddiv_recalc_rate()
/linux/drivers/clk/nxp/
H A Dclk-lpc32xx.c1436 struct clk_hw_proto0 *mux0, *div0, *gate0; in lpc32xx_clk_register() local
1439 div0 = clk_hw->hw1.div; in lpc32xx_clk_register()
1445 if (div0) { in lpc32xx_clk_register()
1446 dops = div0->ops; in lpc32xx_clk_register()
1447 div_hw = &div0->clk.hw; in lpc32xx_clk_register()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h216 u32 div0; member
H A Dintel_dpll_mgr.c2913 hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val); in icl_calc_dpll_state()
3716 hw_state->div0 = intel_de_read(i915, TGL_DPLL0_DIV0(id)); in icl_pll_get_hw_state()
3717 hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK; in icl_pll_get_hw_state()
3794 TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0); in icl_dpll_write()
4096 hw_state->cfgcr0, hw_state->cfgcr1, hw_state->div0, in icl_dump_hw_state()
4118 a->div0 == b->div0 && in icl_compare_hw_state()
/linux/sound/pci/
H A Des1938.c446 unsigned int bits, div0; in snd_es1938_rate_set() local
454 div0 = 256 - 7160000*20/(8*82*runtime->rate); in snd_es1938_rate_set()
458 snd_es1938_mixer_write(chip, 0x72, div0); in snd_es1938_rate_set()
461 snd_es1938_write(chip, 0xA2, div0); in snd_es1938_rate_set()
/linux/sound/isa/
H A Des18xx.c398 unsigned int bits, div0; in snd_es18xx_rate_set() local
413 div0 = 256 - 7160000*20/(8*82*runtime->rate); in snd_es18xx_rate_set()
421 snd_es18xx_write(chip, 0xA2, div0); in snd_es18xx_rate_set()
422 snd_es18xx_mixer_write(chip, 0x72, div0); in snd_es18xx_rate_set()
425 snd_es18xx_write(chip, 0xA2, div0); in snd_es18xx_rate_set()
/linux/kernel/trace/
H A Dtrace_events_hist.c5424 goto div0; in __get_percentage()
5431 goto div0; in __get_percentage()
5434 div0: in __get_percentage()