| /linux/drivers/clk/baikal-t1/ |
| H A D | ccu-div.c | 61 unsigned long div) in ccu_div_lock_delay_ns() argument
63 u64 ns = 4ULL * (div ?: 1) * NSEC_PER_SEC; in ccu_div_lock_delay_ns()
71 unsigned long div) in ccu_div_calc_freq() argument
73 return ref_clk / (div ?: 1); in ccu_div_calc_freq()
76 static int ccu_div_var_update_clkdiv(struct ccu_div *div, in ccu_div_var_update_clkdiv() argument
87 if (div->features & CCU_DIV_LOCK_SHIFTED) in ccu_div_var_update_clkdiv()
92 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_var_update_clkdiv()
102 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_update_clkdiv()
113 struct ccu_div *div = to_ccu_div(hw); in ccu_div_var_enable() local
123 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_enable()
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| /linux/drivers/clk/berlin/ |
| H A D | berlin2-div.c | 67 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_is_enabled() local
68 struct berlin2_div_map *map = &div->map; in berlin2_div_is_enabled()
71 if (div->lock) in berlin2_div_is_enabled()
72 spin_lock(div->lock); in berlin2_div_is_enabled()
74 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_is_enabled()
77 if (div->lock) in berlin2_div_is_enabled()
78 spin_unlock(div->lock); in berlin2_div_is_enabled()
85 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_enable() local
86 struct berlin2_div_map *map = &div->map; in berlin2_div_enable()
89 if (div->lock) in berlin2_div_enable()
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| /linux/drivers/clk/ti/ |
| H A D | divider.c | 26 for (clkt = table; clkt->div; clkt++) in _get_table_div()
28 return clkt->div; in _get_table_div()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
72 unsigned int div) in _get_table_val() argument
76 for (clkt = table; clkt->div; clkt++) in _get_table_val()
77 if (clkt->div == div) in _get_table_val()
82 static unsigned int _get_val(struct clk_omap_divider *divider, u8 div) in _get_val() argument
85 return div; in _get_val()
87 return __ffs(div); in _get_val()
89 return _get_table_val(divider->table, div); in _get_val()
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| /linux/drivers/clk/ |
| H A D | clk-divider.c | 51 for (clkt = table; clkt->div; clkt++) in _get_table_maxdiv()
52 if (clkt->div > maxdiv && clkt->val <= mask) in _get_table_maxdiv()
53 maxdiv = clkt->div; in _get_table_maxdiv()
62 for (clkt = table; clkt->div; clkt++) in _get_table_mindiv()
63 if (clkt->div < mindiv) in _get_table_mindiv()
64 mindiv = clkt->div; in _get_table_mindiv()
87 for (clkt = table; clkt->div; clkt++) in _get_table_div()
89 return clkt->div; in _get_table_div()
110 unsigned int div) in _get_table_val() argument
114 for (clkt = table; clkt->div; clkt++) in _get_table_val()
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| H A D | clk-fsl-flexspi.c | 14 { .val = 0, .div = 1, },
15 { .val = 1, .div = 2, },
16 { .val = 2, .div = 3, },
17 { .val = 3, .div = 4, },
18 { .val = 4, .div = 5, },
19 { .val = 5, .div = 6, },
20 { .val = 6, .div = 7, },
21 { .val = 7, .div = 8, },
22 { .val = 11, .div = 12, },
23 { .val = 15, .div = 16, },
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| H A D | clk-milbeaut.c | 83 u8 div; member
101 { .val = 0, .div = 8 },
102 { .val = 1, .div = 9 },
103 { .val = 2, .div = 10 },
104 { .val = 3, .div = 15 },
105 { .div = 0 },
109 { .val = 1, .div = 2 },
110 { .val = 3, .div = 4 },
111 { .div = 0 },
115 { .val = 3, .div = 4 },
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| H A D | clk-cdce706.c | 29 #define CDCE706_DIVIDER(div) (13 + (div)) argument
50 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4)) argument
51 #define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1)) argument
52 #define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div)) argument
72 unsigned div; member
170 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div); in cdce706_pll_recalc_rate()
173 if (hwd->div && hwd->mul) { in cdce706_pll_recalc_rate()
176 do_div(res, hwd->div); in cdce706_pll_recalc_rate()
180 if (hwd->div) in cdce706_pll_recalc_rate()
181 return parent_rate / hwd->div; in cdce706_pll_recalc_rate()
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| H A D | clk-fixed-factor.c | 29 do_div(rate, fix->div); in clk_factor_recalc_rate()
41 best_parent = (req->rate / fix->mult) * fix->div; in clk_factor_determine_rate()
45 req->rate = (req->best_parent_rate / fix->div) * fix->mult; in clk_factor_determine_rate()
97 unsigned long flags, unsigned int mult, unsigned int div, in __clk_hw_register_fixed_factor() argument
119 fix->div = div; in __clk_hw_register_fixed_factor()
167 unsigned int mult, unsigned int div) in devm_clk_hw_register_fixed_factor_index() argument
172 flags, mult, div, 0, 0, true); in devm_clk_hw_register_fixed_factor_index()
191 unsigned long flags, unsigned int mult, unsigned int div) in devm_clk_hw_register_fixed_factor_parent_hw() argument
196 &pdata, flags, mult, div, 0, 0, true); in devm_clk_hw_register_fixed_factor_parent_hw()
202 unsigned long flags, unsigned int mult, unsigned int div) in clk_hw_register_fixed_factor_parent_hw() argument
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| /linux/drivers/clk/imx/ |
| H A D | clk-divider-gate.c | 21 struct clk_divider *div = to_clk_divider(hw); in to_clk_divider_gate() local
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
29 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_recalc_rate_ro() local
32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro()
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()
37 return divider_recalc_rate(hw, parent_rate, val, div->table, in clk_divider_gate_recalc_rate_ro()
38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro()
45 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_recalc_rate() local
49 spin_lock_irqsave(div->lock, flags); in clk_divider_gate_recalc_rate()
54 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate()
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| /linux/drivers/clk/sunxi/ |
| H A D | clk-sunxi.c | 35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
52 if (div < 10) in sun4i_get_pll1_factors()
56 else if (div < 20 || (div < 32 && (div & 1))) in sun4i_get_pll1_factors()
61 else if (div < 40 || (div < 64 && (div & 2))) in sun4i_get_pll1_factors()
69 div <<= req->p; in sun4i_get_pll1_factors()
70 div /= (req->k + 1); in sun4i_get_pll1_factors()
71 req->n = div / 4; in sun4i_get_pll1_factors()
159 u8 div; in sun8i_a23_get_pll1_factors() local
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| H A D | clk-sun9i-cpus.c | 33 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
34 (div << SUN9I_CPUS_DIV_SHIFT))
39 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
40 (div << SUN9I_CPUS_PLL4_DIV_SHIFT))
72 u8 div, pre_div = 1; in sun9i_a80_cpus_clk_round() local
81 div = DIV_ROUND_UP(parent_rate, rate); in sun9i_a80_cpus_clk_round()
84 if (parent == SUN9I_CPUS_MUX_PARENT_PLL4 && div > 4) { in sun9i_a80_cpus_clk_round()
86 if (div < 32) { in sun9i_a80_cpus_clk_round()
87 pre_div = div; in sun9i_a80_cpus_clk_round()
88 div = 1; in sun9i_a80_cpus_clk_round()
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| /linux/drivers/clk/mxs/ |
| H A D | clk-div.c | 38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_determine_rate() local
48 return div->ops->determine_rate(&div->divider.hw, req); in clk_div_determine_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
59 ret = mxs_clk_wait(div->reg, div->busy); in clk_div_set_rate()
73 struct clk_div *div; in mxs_clk_div() local
77 div = kzalloc_obj(*div, GFP_KERNEL); in mxs_clk_div()
78 if (!div) in mxs_clk_div()
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| /linux/drivers/clk/bcm/ |
| H A D | clk-iproc-asiu.c | 22 struct iproc_asiu_div div; member
82 val = readl(asiu->div_base + clk->div.offset); in iproc_asiu_clk_recalc_rate()
83 if ((val & (1 << clk->div.en_shift)) == 0) { in iproc_asiu_clk_recalc_rate()
89 div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width); in iproc_asiu_clk_recalc_rate()
91 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width); in iproc_asiu_clk_recalc_rate()
104 unsigned int div; in iproc_asiu_clk_determine_rate() local
112 div = DIV_ROUND_CLOSEST(req->best_parent_rate, req->rate); in iproc_asiu_clk_determine_rate()
113 if (div < 2) { in iproc_asiu_clk_determine_rate()
119 req->rate = req->best_parent_rate / div; in iproc_asiu_clk_determine_rate()
129 unsigned int div, div_h, div_l; in iproc_asiu_clk_set_rate() local
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| H A D | clk-kona.c | 51 static inline u64 scaled_div_value(struct bcm_clk_div *div, u32 reg_div) in scaled_div_value() argument
53 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
58 scaled_div_min(struct bcm_clk_div *div) in scaled_div_min() argument
60 if (divider_is_fixed(div)) in scaled_div_min()
61 return (u64)div->u.fixed; in scaled_div_min()
63 return scaled_div_value(div, 0); in scaled_div_min()
67 u64 scaled_div_max(struct bcm_clk_div *div) in scaled_div_max() argument
71 if (divider_is_fixed(div)) in scaled_div_max()
72 return (u64)div->u.fixed; in scaled_div_max()
74 reg_div = ((u32)1 << div->u.s.width) - 1; in scaled_div_max()
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| /linux/drivers/clk/ingenic/ |
| H A D | cgu.c | 414 u32 div_reg, div; in ingenic_clk_recalc_rate() local
420 if (!(clk_info->div.bypass_mask & BIT(parent))) { in ingenic_clk_recalc_rate()
421 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
422 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
423 GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_recalc_rate()
425 if (clk_info->div.div_table) in ingenic_clk_recalc_rate()
426 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
428 div = (div + 1) * clk_info->div.div; in ingenic_clk_recalc_rate()
430 rate /= div; in ingenic_clk_recalc_rate()
433 rate /= clk_info->fixdiv.div; in ingenic_clk_recalc_rate()
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| /linux/drivers/clk/tegra/ |
| H A D | clk-divider.c | 24 int div; in get_div() local
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
29 if (div < 0) in get_div()
32 return div; in get_div()
40 int div, mul; in clk_frac_div_recalc_rate() local
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
52 div += mul; in clk_frac_div_recalc_rate()
55 rate += div - 1; in clk_frac_div_recalc_rate()
56 do_div(rate, div); in clk_frac_div_recalc_rate()
65 int div, mul; in clk_frac_div_determine_rate() local
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| /linux/drivers/media/platform/st/sti/hva/ |
| H A D | hva-debugfs.c | 121 u64 div; in hva_dbg_perf_begin() local
131 div = (u64)ktime_us_delta(dbg->begin, prev); in hva_dbg_perf_begin()
132 do_div(div, 100); in hva_dbg_perf_begin()
133 period = (u32)div; in hva_dbg_perf_begin()
152 div = (u64)dbg->window_stream_size * 80; in hva_dbg_perf_begin()
153 do_div(div, dbg->window_duration); in hva_dbg_perf_begin()
154 bitrate = (u32)div; in hva_dbg_perf_begin()
178 u64 div; in hva_dbg_perf_end() local
187 div = stream->vbuf.vb2_buf.timestamp; in hva_dbg_perf_end()
188 do_div(div, 1000); in hva_dbg_perf_end()
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| /linux/drivers/clk/zynqmp/ |
| H A D | divider.c | 86 u32 div, value; in zynqmp_clk_divider_recalc_rate() local
89 ret = zynqmp_pm_clock_getdivider(clk_id, &div); in zynqmp_clk_divider_recalc_rate()
96 value = div & 0xFFFF; in zynqmp_clk_divider_recalc_rate()
98 value = div >> 16; in zynqmp_clk_divider_recalc_rate()
179 u32 value, div; in zynqmp_clk_divider_set_rate() local
184 div = value & 0xFFFF; in zynqmp_clk_divider_set_rate()
185 div |= 0xffff << 16; in zynqmp_clk_divider_set_rate()
187 div = 0xffff; in zynqmp_clk_divider_set_rate()
188 div |= value << 16; in zynqmp_clk_divider_set_rate()
192 div = __ffs(div); in zynqmp_clk_divider_set_rate()
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| /linux/drivers/clk/qcom/ |
| H A D | clk-regmap-mux-div.c | 23 int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div) in mux_div_set_src_div() argument
29 val = (div << md->hid_shift) | (src << md->src_shift); in mux_div_set_src_div()
60 u32 *div) in mux_div_get_src_div() argument
79 *div = d; in mux_div_get_src_div()
92 unsigned int i, div, max_div; in mux_div_determine_rate() local
101 for (div = 1; div < max_div; div++) { in mux_div_determine_rate()
102 parent_rate = mult_frac(req_rate, div, 2); in mux_div_determine_rate()
104 actual_rate = mult_frac(parent_rate, 2, div); in mux_div_determine_rate()
129 u32 div, max_div, best_src = 0, best_div = 0; in __mux_div_set_rate_and_parent() local
138 for (div = 1; div < max_div; div++) { in __mux_div_set_rate_and_parent()
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| /linux/drivers/clk/at91/ |
| H A D | clk-master.c | 39 u8 div; member
87 u8 div; in clk_master_div_recalc_rate() local
101 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_recalc_rate()
103 rate /= characteristics->divisors[div]; in clk_master_div_recalc_rate()
118 unsigned int mckr, div; in clk_master_div_save_context() local
125 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_save_context()
126 div = master->characteristics->divisors[div]; in clk_master_div_save_context()
129 master->pms.rate = DIV_ROUND_CLOSEST(master->pms.parent_rate, div); in clk_master_div_save_context()
139 u8 div; in clk_master_div_restore_context() local
146 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_restore_context()
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| H A D | clk-sam9x60-pll.c | 47 u8 div; member
346 static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div, in sam9x60_div_pll_set_div() argument
355 (div << core->layout->div_shift) | ena_val); in sam9x60_div_pll_set_div()
367 struct sam9x60_div *div = to_sam9x60_div(core); in sam9x60_div_pll_set() local
379 if (!!(val & core->layout->endiv_mask) && cdiv == div->div) in sam9x60_div_pll_set()
382 sam9x60_div_pll_set_div(core, div->div, 1); in sam9x60_div_pll_set()
440 struct sam9x60_div *div = to_sam9x60_div(core); in sam9x60_div_pll_recalc_rate() local
442 return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1)); in sam9x60_div_pll_recalc_rate()
509 struct sam9x60_div *div = to_sam9x60_div(core); in sam9x60_div_pll_set_rate() local
511 div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; in sam9x60_div_pll_set_rate()
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| /linux/drivers/pwm/ |
| H A D | pwm-rcar.c | 76 u64 div, tmp; in rcar_pwm_get_clock_division() local
81 div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE; in rcar_pwm_get_clock_division()
82 tmp = (u64)period_ns * clk_rate + div - 1; in rcar_pwm_get_clock_division()
83 tmp = div64_u64(tmp, div); in rcar_pwm_get_clock_division()
84 div = ilog2(tmp - 1) + 1; in rcar_pwm_get_clock_division()
86 return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE; in rcar_pwm_get_clock_division()
90 unsigned int div) in rcar_pwm_set_clock_control() argument
97 if (div & 1) in rcar_pwm_set_clock_control()
100 div >>= 1; in rcar_pwm_set_clock_control()
102 value |= div << RCAR_PWMCR_CC0_SHIFT; in rcar_pwm_set_clock_control()
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| /linux/drivers/clk/actions/ |
| H A D | owl-factor.c | 21 for (clkt = table; clkt->div; clkt++) in _get_table_maxval()
28 unsigned int val, unsigned int *mul, unsigned int *div) in _get_table_div_mul() argument
32 for (clkt = table; clkt->div; clkt++) { in _get_table_div_mul()
35 *div = clkt->div; in _get_table_div_mul()
50 for (clkt = table; clkt->div; clkt++) { in _get_table_val()
52 do_div(calc_rate, clkt->div); in _get_table_val()
84 for (clkt = factor_hw->table; clkt->div; clkt++) { in owl_clk_val_best()
85 try_parent_rate = rate * clkt->div / clkt->mul; in owl_clk_val_best()
89 __func__, clkt->val, clkt->mul, clkt->div, in owl_clk_val_best()
102 cur_rate = DIV_ROUND_UP(parent_rate, clkt->div) * clkt->mul; in owl_clk_val_best()
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| /linux/drivers/clk/hisilicon/ |
| H A D | clkdivider-hi6220.c | 104 struct hi6220_clk_divider *div; in hi6220_register_clkdiv() local
112 div = kzalloc_obj(*div, GFP_KERNEL); in hi6220_register_clkdiv()
113 if (!div) in hi6220_register_clkdiv()
122 kfree(div); in hi6220_register_clkdiv()
127 table[i].div = min_div + i; in hi6220_register_clkdiv()
128 table[i].val = table[i].div - 1; in hi6220_register_clkdiv()
138 div->reg = reg; in hi6220_register_clkdiv()
139 div->shift = shift; in hi6220_register_clkdiv()
140 div->width = width; in hi6220_register_clkdiv()
141 div->mask = mask_bit ? BIT(mask_bit) : 0; in hi6220_register_clkdiv()
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| /linux/sound/aoa/soundbus/i2sbus/ |
| H A D | interface.h | 89 # define I2S_SF_MCLKDIV_OTHER(div) (((div/2-1)<<I2S_SF_MCLKDIV_SHIFT)&I2S_SF_MCLKDIV_MASK) argument
90 static inline int i2s_sf_mclkdiv(int div, int *out) in i2s_sf_mclkdiv() argument
94 switch(div) { in i2s_sf_mclkdiv()
100 if (div%2) return -1; in i2s_sf_mclkdiv()
101 d = div/2-1; in i2s_sf_mclkdiv()
104 *out |= I2S_SF_MCLKDIV_OTHER(div); in i2s_sf_mclkdiv()
116 # define I2S_SF_SCLKDIV_OTHER(div) (((div/2-1)<<I2S_SF_SCLKDIV_SHIFT)&I2S_SF_SCLKDIV_MASK) argument
117 static inline int i2s_sf_sclkdiv(int div, int *out) in i2s_sf_sclkdiv() argument
121 switch(div) { in i2s_sf_sclkdiv()
125 if (div%2) return -1; in i2s_sf_sclkdiv()
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