1 /*
2 * SPDX-License-Identifier: MIT
3 *
4 * Copyright 2026 Advanced Micro Devices, Inc.
5 */
6
7 #include "dm_services.h"
8 #include "dc.h"
9
10 #include "dcn32/dcn32_init.h"
11 #include "dcn42/dcn42_init.h"
12 #include "dcn42b/dcn42b_init.h"
13
14 #include "resource.h"
15 #include "include/irq_service_interface.h"
16 #include "basics/conversion.h"
17
18 #include "dcn42b_resource.h"
19 #include "dcn20/dcn20_resource.h"
20 #include "dcn30/dcn30_resource.h"
21 #include "dcn31/dcn31_resource.h"
22 #include "dcn32/dcn32_resource.h"
23 #include "dcn35/dcn35_resource.h"
24 #include "dcn321/dcn321_resource.h"
25 #include "dcn401/dcn401_resource.h"
26 #include "dcn42/dcn42_resource.h"
27 #include "dcn42/dcn42_resource_fpu.h"
28
29 #include "dcn10/dcn10_ipp.h"
30 #include "dcn35/dcn35_hubbub.h"
31 #include "dcn42/dcn42_hubbub.h"
32 #include "dcn401/dcn401_mpc.h"
33 #include "dcn42/dcn42_mpc.h"
34 #include "dcn35/dcn35_hubp.h"
35 #include "dcn42/dcn42_hubp.h"
36 #include "irq/dcn42/irq_service_dcn42.h"
37 #include "dcn42/dcn42_dpp.h"
38 #include "dcn401/dcn401_dsc.h"
39 #include "dcn42/dcn42_optc.h"
40 #include "dcn20/dcn20_hwseq.h"
41 #include "dcn30/dcn30_hwseq.h"
42 #include "dce110/dce110_hwseq.h"
43 #include "dcn35/dcn35_opp.h"
44 #include "dcn30/dcn30_vpg.h"
45 #include "dcn31/dcn31_vpg.h"
46 #include "dcn42/dcn42_dio_stream_encoder.h"
47 #include "dcn42/dcn42_pg_cntl.h"
48 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
49 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
50 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
51 #include "dcn42/dcn42_hpo_dp_link_encoder.h"
52 #include "dcn31/dcn31_apg.h"
53 #include "dcn31/dcn31_dio_link_encoder.h"
54 #include "dcn401/dcn401_dio_link_encoder.h"
55 #include "dcn10/dcn10_link_encoder.h"
56 #include "dcn321/dcn321_dio_link_encoder.h"
57 #include "dce/dce_clock_source.h"
58 #include "dce/dce_audio.h"
59 #include "dce/dce_hwseq.h"
60 #include "clk_mgr.h"
61 #include "dio/virtual/virtual_stream_encoder.h"
62 #include "dml/display_mode_vba.h"
63 #include "dcn42/dcn42_dccg.h"
64 #include "dcn10/dcn10_resource.h"
65 #include "link_service.h"
66 #include "dcn31/dcn31_panel_cntl.h"
67
68 #include "dcn30/dcn30_dwb.h"
69 #include "dcn42/dcn42_mmhubbub.h"
70 #include "dcn42/dcn42_dio_link_encoder.h"
71
72 #include "dcn/dcn_4_2_1_offset.h"
73 #include "dcn/dcn_4_2_1_sh_mask.h"
74 #include "dpcs/dpcs_4_0_1_offset.h"
75 #include "dpcs/dpcs_4_0_1_sh_mask.h"
76
77 #include "reg_helper.h"
78 #include "dce/dmub_abm.h"
79 #include "dce/dmub_psr.h"
80 #include "dce/dmub_replay.h"
81 #include "dce/dce_aux.h"
82 #include "dce/dce_i2c.h"
83
84 #include "dml/dcn30/display_mode_vba_30.h"
85 #include "vm_helper.h"
86 #include "dcn20/dcn20_vmid.h"
87
88 #include "dc_state_priv.h"
89 #include "link_enc_cfg.h"
90
91 #include "dml2_0/dml2_wrapper.h"
92
93 #define DC_LOGGER_INIT(logger)
94
95 #define regBIF_BX1_BIOS_SCRATCH_3 0x003b
96 #define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 1
97 #define regBIF_BX1_BIOS_SCRATCH_6 0x003e
98 #define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 1
99
100 #define regAPG0_APG_DBG_GEN_CONTROL 0x2075
101 #define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2
102 #define regAPG1_APG_DBG_GEN_CONTROL 0x2199
103 #define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2
104 #define regAPG2_APG_DBG_GEN_CONTROL 0x22bd
105 #define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2
106 #define regAPG3_APG_DBG_GEN_CONTROL 0x23e1
107 #define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2
108 #define regAPG4_APG_DBG_GEN_CONTROL 0x2505
109 #define regAPG4_APG_DBG_GEN_CONTROL_BASE_IDX 2
110 #define regAPG5_APG_DBG_GEN_CONTROL 0x0915
111 #define regAPG5_APG_DBG_GEN_CONTROL_BASE_IDX 3
112 #define regAPG6_APG_DBG_GEN_CONTROL 0x3632
113 #define regAPG6_APG_DBG_GEN_CONTROL_BASE_IDX 2
114 #define regAPG7_APG_DBG_GEN_CONTROL 0x3706
115 #define regAPG7_APG_DBG_GEN_CONTROL_BASE_IDX 2
116 #define regAPG8_APG_DBG_GEN_CONTROL 0x37da
117 #define regAPG8_APG_DBG_GEN_CONTROL_BASE_IDX 2
118 #define regAPG9_APG_DBG_GEN_CONTROL 0x38ae
119 #define regAPG9_APG_DBG_GEN_CONTROL_BASE_IDX 2
120
121 #define regHUBP0_HUBPREQ_DEBUG_DB 0x05f8
122 #define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2
123 #define regHUBP0_HUBPREQ_DEBUG 0x05f9
124 #define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2
125 #define regHUBP1_HUBPREQ_DEBUG_DB 0x06d4
126 #define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2
127 #define regHUBP1_HUBPREQ_DEBUG 0x06d5
128 #define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2
129 #define regHUBP2_HUBPREQ_DEBUG_DB 0x07b0
130 #define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2
131 #define regHUBP2_HUBPREQ_DEBUG 0x07b1
132 #define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2
133 #define regHUBP3_HUBPREQ_DEBUG_DB 0x088c
134 #define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2
135 #define regHUBP3_HUBPREQ_DEBUG 0x088d
136 #define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2
137
138 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687
139 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2
140 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b
141 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2
142 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f
143 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2
144 #define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b
145 #define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2
146 #define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f
147 #define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2
148 #define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813
149 #define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2
150
151 #define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0
152 #define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4
153 #define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L
154 #define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L
155 #define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0
156 #define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL
157
158
159 #define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0
160 #define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4
161 #define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L
162 #define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L
163 #define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0
164 #define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL
165
166 enum dcn401_clk_src_array_id {
167 DCN401_CLK_SRC_PLL0,
168 DCN401_CLK_SRC_PLL1,
169 DCN401_CLK_SRC_PLL2,
170 DCN401_CLK_SRC_TOTAL
171 };
172
173 /* begin
174 * macros to expend register list macro defined in HW object header file
175 */
176
177 /* DCN */
178 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
179
180 #define BASE(seg) BASE_INNER(seg)
181
182 #define SR(reg_name) \
183 REG_STRUCT.reg_name = BASE(reg##reg_name##_BASE_IDX) + \
184 reg##reg_name
185 #define SR_ARR(reg_name, id) \
186 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \
187 reg##reg_name
188 #define SR_ARR_INIT(reg_name, id, value) \
189 REG_STRUCT[id].reg_name = value
190
191 #define SRI(reg_name, block, id) \
192 REG_STRUCT.reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
193 reg##block##id##_##reg_name
194
195 #define SRI_ARR(reg_name, block, id) \
196 REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
197 reg##block##id##_##reg_name
198
199 /*
200 * Used when a reg_name would otherwise begin with an integer
201 */
202 #define SRI_ARR_US(reg_name, block, id) \
203 REG_STRUCT[id].reg_name = BASE(reg##block##id##reg_name##_BASE_IDX) + \
204 reg##block##id##reg_name
205 #define SR_ARR_I2C(reg_name, id) \
206 REG_STRUCT[id - 1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
207
208 #define SRI_ARR_I2C(reg_name, block, id) \
209 REG_STRUCT[id - 1].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
210 reg##block##id##_##reg_name
211
212 #define SRI_ARR_ALPHABET(reg_name, block, index, id) \
213 REG_STRUCT[index].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
214 reg##block##id##_##reg_name
215
216 #define SRI2(reg_name, block, id) \
217 .reg_name = BASE(reg##reg_name##_BASE_IDX) + \
218 reg##reg_name
219 #define SRI2_ARR(reg_name, block, id) \
220 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \
221 reg##reg_name
222
223 #define SRIR(var_name, reg_name, block, id) \
224 .var_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
225 reg##block##id##_##reg_name
226
227 #define SRII(reg_name, block, id) \
228 REG_STRUCT.reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
229 reg##block##id##_##reg_name
230
231 #define SRII_ARR_2(reg_name, block, id, inst) \
232 REG_STRUCT[inst].reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
233 reg##block##id##_##reg_name
234
235 #define SRII_MPC_RMU(reg_name, block, id) \
236 .RMU##_##reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
237 reg##block##id##_##reg_name
238
239 #define SRII_DWB(reg_name, temp_name, block, id) \
240 REG_STRUCT.reg_name[id] = \
241 BASE(reg##block##id##_##temp_name##_BASE_IDX) + \
242 reg##block##id##_##temp_name
243
244 #define DCCG_SRII(reg_name, block, id) \
245 REG_STRUCT.block##_##reg_name[id] = \
246 BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
247 reg##block##id##_##reg_name
248
249 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
250 .field_name = reg_name##__##field_name##post_fix
251
252 #define VUPDATE_SRII(reg_name, block, id) \
253 REG_STRUCT.reg_name[id] = BASE(reg##reg_name##_##block##id##_BASE_IDX) + \
254 reg##reg_name##_##block##id
255
256 /* NBIO */
257 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
258
259 #define NBIO_BASE(seg) \
260 NBIO_BASE_INNER(seg)
261
262 #define NBIO_SR(reg_name) \
263 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_##reg_name##_BASE_IDX) + \
264 regBIF_BX1_##reg_name
265 #define NBIO_SR_ARR(reg_name, id) \
266 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_##reg_name##_BASE_IDX) + \
267 regBIF_BX1_##reg_name
268
269 #define CTX ctx
270 #define REG(reg_name) \
271 (ctx->dcn_reg_offsets[reg##reg_name##_BASE_IDX] + reg##reg_name)
272
273 static struct bios_registers bios_regs;
274
275 #define bios_regs_init() \
276 NBIO_SR(BIOS_SCRATCH_3), \
277 NBIO_SR(BIOS_SCRATCH_6)
278
279 #define clk_src_regs_init(index, pllid) \
280 CS_COMMON_REG_LIST_DCN42B_RI(index, pllid)
281
282 static struct dce110_clk_src_regs clk_src_regs[5];
283
284 static const struct dce110_clk_src_shift cs_shift = {
285 CS_COMMON_MASK_SH_LIST_DCN4_0_1(__SHIFT)
286 };
287 static const struct dce110_clk_src_mask cs_mask = {
288 CS_COMMON_MASK_SH_LIST_DCN4_0_1(_MASK)
289 };
290 #define abm_regs_init(id) \
291 ABM_DCN42B_REG_LIST_RI(id)
292
293 static struct dce_abm_registers abm_regs[4];
294
295 static const struct dce_abm_shift abm_shift = {
296 ABM_MASK_SH_LIST_DCN42(__SHIFT)};
297
298 static const struct dce_abm_mask abm_mask = {
299 ABM_MASK_SH_LIST_DCN42(_MASK)};
300
301 #define audio_regs_init(id) \
302 AUD_COMMON_REG_LIST_RI(id)
303
304 static struct dce_audio_registers audio_regs[5];
305
306 /* DTO2 not present for DCN42b */
307 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh) \
308 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh), \
309 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh), \
310 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh), \
311 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh), \
312 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh), \
313 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh), \
314 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh), \
315 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh), \
316 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh), \
317 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh), \
318 SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh), \
319 SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh), \
320 SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh)
321
322 static const struct dce_audio_shift audio_shift = {
323 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)};
324
325 static const struct dce_audio_mask audio_mask = {
326 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)};
327
328 #define vpg_regs_init(id) \
329 VPG_DCN401_REG_LIST_RI(id)
330
331 static struct dcn31_vpg_registers vpg_regs[10];
332
333 static const struct dcn31_vpg_shift vpg_shift = {
334 DCN31_VPG_MASK_SH_LIST(__SHIFT)};
335
336 static const struct dcn31_vpg_mask vpg_mask = {
337 DCN31_VPG_MASK_SH_LIST(_MASK)};
338
339 #define apg_regs_init(id) \
340 APG_DCN31_REG_LIST_RI(id)
341
342 static struct dcn31_apg_registers apg_regs[10];
343
344 static const struct dcn31_apg_shift apg_shift = {
345 DCN42B_APG_MASK_SH_LIST(__SHIFT)};
346
347 static const struct dcn31_apg_mask apg_mask = {
348 DCN42B_APG_MASK_SH_LIST(_MASK)};
349
350 #define stream_enc_regs_init(id) \
351 SE_DCN42B_REG_LIST_RI(id)
352
353 static struct dcn10_stream_enc_registers stream_enc_regs[5];
354
355 static const struct dcn10_stream_encoder_shift se_shift = {
356 SE_COMMON_MASK_SH_LIST_DCN42(__SHIFT)};
357
358 static const struct dcn10_stream_encoder_mask se_mask = {
359 SE_COMMON_MASK_SH_LIST_DCN42(_MASK)};
360
361 #define aux_regs_init(id) \
362 DCN2_AUX_REG_LIST_RI(id)
363
364 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
365
366 #define hpd_regs_init(id) \
367 HPD_REG_LIST_RI(id)
368
369 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
370
371 #define link_regs_init(id, phyid) \
372 LE_DCN401_REG_LIST_RI(id)
373
374 static struct dcn10_link_enc_registers link_enc_regs[5];
375
376 static const struct dcn10_link_enc_shift le_shift = {
377 LINK_ENCODER_MASK_SH_LIST_DCN42B(__SHIFT)};
378
379 static const struct dcn10_link_enc_mask le_mask = {
380 LINK_ENCODER_MASK_SH_LIST_DCN42B(_MASK)};
381
382 #define hpo_dp_stream_encoder_reg_init(id) \
383 DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
384
385 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
386
387 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
388 DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)};
389
390 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
391 DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)};
392
393 #define hpo_dp_link_encoder_reg_init(id) \
394 DCN42B_HPO_DP_LINK_ENC_REG_LIST_RI(id)
395 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
396 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
397 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
398 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
399
400 /* DCN42B has 2 HPO DP link encoders */
401 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
402
403 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
404 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)};
405
406 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
407 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)};
408
409 #define dpp_regs_init(id) \
410 DPP_REG_LIST_DCN42B_COMMON_RI(id)
411
412 static struct dcn42_dpp_registers dpp_regs[4];
413
414 static const struct dcn42_dpp_shift tf_shift = {
415 DPP_REG_LIST_SH_MASK_DCN42_COMMON(__SHIFT)};
416
417 static const struct dcn42_dpp_mask tf_mask = {
418 DPP_REG_LIST_SH_MASK_DCN42_COMMON(_MASK)};
419
420 #define opp_regs_init(id) \
421 OPP_REG_LIST_DCN401_RI(id)
422
423 static struct dcn20_opp_registers opp_regs[4];
424
425 static const struct dcn20_opp_shift opp_shift = {
426 OPP_MASK_SH_LIST_DCN20(__SHIFT)};
427
428 static const struct dcn20_opp_mask opp_mask = {
429 OPP_MASK_SH_LIST_DCN20(_MASK)};
430
431 #define aux_engine_regs_init(id) \
432 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
433 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
434 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
435 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)
436
437 static struct dce110_aux_registers aux_engine_regs[5];
438
439 static const struct dce110_aux_registers_shift aux_shift = {
440 DCN_AUX_MASK_SH_LIST(__SHIFT)};
441
442 static const struct dce110_aux_registers_mask aux_mask = {
443 DCN_AUX_MASK_SH_LIST(_MASK)};
444
445 #define dwbc_regs_dcn401_init(id) \
446 DWBC_COMMON_REG_LIST_DCN30_RI(id)
447
448 static struct dcn30_dwbc_registers dwbc401_regs[1];
449
450 static const struct dcn30_dwbc_shift dwbc401_shift = {
451 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)};
452
453 static const struct dcn30_dwbc_mask dwbc401_mask = {
454 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)};
455
456 #define mcif_wb_regs_dcn3_init(id) \
457 MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)
458
459 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];
460
461 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {
462 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)};
463
464 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {
465 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)};
466
467 #define dsc_regs_init(id) \
468 DSC_REG_LIST_DCN401_RI(id)
469
470 static struct dcn401_dsc_registers dsc_regs[4];
471
472 static const struct dcn401_dsc_shift dsc_shift = {
473 DSC_REG_LIST_SH_MASK_DCN401(__SHIFT)};
474
475 static const struct dcn401_dsc_mask dsc_mask = {
476 DSC_REG_LIST_SH_MASK_DCN401(_MASK)};
477
478 static struct dcn42_mpc_registers mpc_regs;
479
480 #define dcn_mpc_regs_init() \
481 MPC_REG_LIST_DCN42(0), \
482 MPC_REG_LIST_DCN42(1), \
483 MPC_REG_LIST_DCN42(2), \
484 MPC_REG_LIST_DCN42(3), \
485 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0), \
486 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1), \
487 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2), \
488 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3), \
489 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0), \
490 MPC_RMCM_REG_LIST_DCN42(0), \
491 MPC_RMCM_REG_LIST_DCN42(1)
492
493 static const struct dcn42_mpc_shift mpc_shift = {
494 MPC_COMMON_MASK_SH_LIST_DCN42(__SHIFT)};
495
496 static const struct dcn42_mpc_mask mpc_mask = {
497 MPC_COMMON_MASK_SH_LIST_DCN42(_MASK)};
498
499 #define optc_regs_init(id) \
500 OPTC_COMMON_REG_LIST_DCN42B_RI(id)
501
502 static struct dcn_optc_registers optc_regs[4];
503
504 static const struct dcn_optc_shift optc_shift = {
505 OPTC_COMMON_MASK_SH_LIST_DCN42B(__SHIFT)};
506
507 static const struct dcn_optc_mask optc_mask = {
508 OPTC_COMMON_MASK_SH_LIST_DCN42B(_MASK)};
509
510 #define hubp_regs_init(id) \
511 HUBP_REG_LIST_DCN42_RI(id)
512
513 static struct dcn_hubp2_registers hubp_regs[4];
514
515 static const struct dcn_hubp2_shift hubp_shift = {
516 HUBP_MASK_SH_LIST_DCN42B(__SHIFT)};
517
518 static const struct dcn_hubp2_mask hubp_mask = {
519 HUBP_MASK_SH_LIST_DCN42B(_MASK)};
520
521 static struct dcn_hubbub_registers hubbub_reg;
522
523 #define hubbub_reg_init() \
524 HUBBUB_REG_LIST_DCN42B(0)
525
526 static const struct dcn_hubbub_shift hubbub_shift = {
527 HUBBUB_MASK_SH_LIST_DCN42B(__SHIFT)};
528
529 static const struct dcn_hubbub_mask hubbub_mask = {
530 HUBBUB_MASK_SH_LIST_DCN42B(_MASK)};
531
532 static struct dccg_registers dccg_regs;
533
534 #define dccg_regs_init() \
535 DCCG_REG_LIST_DCN42B_RI()
536
537 static const struct dccg_shift dccg_shift = {
538 DCCG_MASK_SH_LIST_DCN42_COMMON(__SHIFT)};
539
540 static const struct dccg_mask dccg_mask = {
541 DCCG_MASK_SH_LIST_DCN42_COMMON(_MASK)};
542
543 static struct pg_cntl_registers pg_cntl_regs;
544
545 #define pg_cntl_dcn42b_regs_init() \
546 PG_CNTL_REG_LIST_DCN42B()
547
548 static const struct pg_cntl_shift pg_cntl_shift = {
549 PG_CNTL_MASK_SH_LIST_DCN42B(__SHIFT)
550 };
551
552 static const struct pg_cntl_mask pg_cntl_mask = {
553 PG_CNTL_MASK_SH_LIST_DCN42B(_MASK)
554 };
555 #define SRII2(reg_name_pre, reg_name_post, id) \
556 .reg_name_pre##_##reg_name_post[id] = \
557 BASE(reg##reg_name_pre##id##_##reg_name_post##_BASE_IDX) + \
558 reg##reg_name_pre##id##_##reg_name_post
559
560 /* Not in DCN42B:
561 * SRII(PIXEL_RATE_CNTL, OTG, 3),
562 * SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),
563 * SR(DOMAIN19_PG_CONFIG),
564 * SR(DOMAIN19_PG_STATUS),
565 */
566 #define HWSEQ_DCN42B_REG_LIST() \
567 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
568 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
569 SR(DIO_MEM_PWR_CTRL), \
570 SR(ODM_MEM_PWR_CTRL3), \
571 SR(MMHUBBUB_MEM_PWR_CNTL), \
572 SR(DCCG_GATE_DISABLE_CNTL), \
573 SR(DCCG_GATE_DISABLE_CNTL2), \
574 SR(DCCG_GATE_DISABLE_CNTL4), \
575 SR(DCCG_GATE_DISABLE_CNTL5), \
576 SR(DCFCLK_CNTL), \
577 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
578 SRII(PIXEL_RATE_CNTL, OTG, 0), \
579 SRII(PIXEL_RATE_CNTL, OTG, 1), \
580 SRII(PIXEL_RATE_CNTL, OTG, 2), \
581 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0), \
582 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1), \
583 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2), \
584 SR(MICROSECOND_TIME_BASE_DIV), \
585 SR(MILLISECOND_TIME_BASE_DIV), \
586 SR(DISPCLK_FREQ_CHANGE_CNTL), \
587 SR(RBBMIF_TIMEOUT_DIS), \
588 SR(RBBMIF_TIMEOUT_DIS_2), \
589 SR(DCHUBBUB_CRC_CTRL), \
590 SR(DPP_TOP0_DPP_CRC_CTRL), \
591 SR(DPP_TOP0_DPP_CRC_VAL_R), \
592 SR(DPP_TOP0_DPP_CRC_VAL_G), \
593 SR(DPP_TOP0_DPP_CRC_VAL_B), \
594 SR(DPP_TOP0_DPP_CRC_VAL_A), \
595 SR(MPC_CRC_CTRL), \
596 SR(MPC_CRC_RESULT_R), \
597 SR(MPC_CRC_RESULT_G), \
598 SR(MPC_CRC_RESULT_B), \
599 SR(MPC_CRC_RESULT_A), \
600 SR(DOMAIN0_PG_CONFIG), \
601 SR(DOMAIN1_PG_CONFIG), \
602 SR(DOMAIN2_PG_CONFIG), \
603 SR(DOMAIN3_PG_CONFIG), \
604 SR(DOMAIN16_PG_CONFIG), \
605 SR(DOMAIN17_PG_CONFIG), \
606 SR(DOMAIN18_PG_CONFIG), \
607 SR(DOMAIN22_PG_CONFIG), \
608 SR(DOMAIN23_PG_CONFIG), \
609 SR(DOMAIN24_PG_CONFIG), \
610 SR(DOMAIN25_PG_CONFIG), \
611 SR(DOMAIN26_PG_CONFIG), \
612 SR(DOMAIN0_PG_STATUS), \
613 SR(DOMAIN1_PG_STATUS), \
614 SR(DOMAIN2_PG_STATUS), \
615 SR(DOMAIN3_PG_STATUS), \
616 SR(DOMAIN16_PG_STATUS), \
617 SR(DOMAIN17_PG_STATUS), \
618 SR(DOMAIN18_PG_STATUS), \
619 SR(DOMAIN22_PG_STATUS), \
620 SR(DOMAIN23_PG_STATUS), \
621 SR(DOMAIN24_PG_STATUS), \
622 SR(DOMAIN25_PG_STATUS), \
623 SR(DOMAIN26_PG_STATUS), \
624 SR(DC_IP_REQUEST_CNTL), \
625 SR(AZALIA_AUDIO_DTO), \
626 SR(HPO_TOP_HW_CONTROL), \
627 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
628 SR(DMU_CLK_CNTL)
629
630 static struct dce_hwseq_registers hwseq_reg;
631
632 #define hwseq_reg_init() \
633 HWSEQ_DCN42B_REG_LIST()
634
635 /* Not in DCN42B
636 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
637 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
638 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
639 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \
640 HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh), \
641 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh), \
642 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh), \
643 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh), \
644 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh), \
645 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK4_GATE_DISABLE, mask_sh), \
646 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK5_GATE_DISABLE, mask_sh), \
647 */
648 #define HWSEQ_DCN42B_MASK_SH_LIST(mask_sh) \
649 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
650 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
651 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
652 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
653 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
654 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
655 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
656 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
657 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
658 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
659 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
660 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
661 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
662 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
663 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
664 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
665 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
666 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
667 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
668 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
669 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
670 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
671 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
672 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
673 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
674 HWS_SF(, DOMAIN26_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
675 HWS_SF(, DOMAIN26_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
676 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
677 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
678 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
679 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
680 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
681 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
682 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
683 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
684 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
685 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
686 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
687 HWS_SF(, DOMAIN26_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
688 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
689 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
690 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh), \
691 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
692 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
693 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
694 HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\
695 HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\
696 HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\
697 HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
698 HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
699 HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
700 HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\
701 HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
702 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
703 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
704 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
705 HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\
706 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
707 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
708 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
709 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
710 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
711 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
712 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
713 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
714 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
715 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \
716 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \
717 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
718 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
719 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
720 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
721 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
722 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
723 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
724 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
725 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
726 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh)
727
728 static const struct dce_hwseq_shift hwseq_shift = {
729 HWSEQ_DCN42B_MASK_SH_LIST(__SHIFT)};
730
731 static const struct dce_hwseq_mask hwseq_mask = {
732 HWSEQ_DCN42B_MASK_SH_LIST(_MASK)};
733
734 #define vmid_regs_init(id) \
735 DCN20_VMID_REG_LIST_RI(id)
736
737 static struct dcn_vmid_registers vmid_regs[16];
738
739 static const struct dcn20_vmid_shift vmid_shifts = {
740 DCN20_VMID_MASK_SH_LIST(__SHIFT)};
741
742 static const struct dcn20_vmid_mask vmid_masks = {
743 DCN20_VMID_MASK_SH_LIST(_MASK)};
744
745 static const struct resource_caps res_cap_dcn42b = {
746 .num_timing_generator = 3,
747 .num_opp = 3,
748 .num_dpp = 4,
749 .num_video_plane = 4,
750 .num_audio = 4,
751 .num_stream_encoder = 3,
752 .num_dig_link_enc = 3,
753 // .num_usb4_dpia = 6,
754 .num_hpo_dp_stream_encoder = 3,
755 .num_hpo_dp_link_encoder = 2,
756 .num_pll = 3,
757 .num_dwb = 1,
758 .num_ddc = 0,
759 .num_vmid = 16,
760 .num_mpc_3dlut = 2,
761 .num_dsc = 3,
762 .num_rmcm = 2,
763 .num_mpc = 4,
764 .num_aux = 3,
765 };
766
767 static const struct dc_plane_cap plane_cap = {
768 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
769 .per_pixel_alpha = true,
770
771 .pixel_format_support = {
772 .argb8888 = true,
773 .nv12 = true,
774 .fp16 = true,
775 .p010 = true,
776 .ayuv = false,
777 },
778
779 .max_upscale_factor = {.argb8888 = 16000, .nv12 = 16000, .fp16 = 16000},
780
781 // 6:1 downscaling ratio: 1000/6 = 166.666
782 .max_downscale_factor = {.argb8888 = 167, .nv12 = 167, .fp16 = 167},
783
784 .min_width = 64,
785 .min_height = 64};
786
787 static const struct dc_debug_options debug_defaults_drv = {
788 .limit_ffe = 3,
789 .disable_dmcu = true,
790 .force_abm_enable = false,
791 .clock_trace = true,
792 .disable_pplib_clock_request = false,
793 .disable_dpp_power_gate = true,
794 .disable_hubp_power_gate = true,
795 .disable_optc_power_gate = true,
796 .pipe_split_policy = MPC_SPLIT_AVOID,
797 .force_single_disp_pipe_split = false,
798 .disable_dcc = DCC_ENABLE,
799 .vsr_support = true,
800 .performance_trace = false,
801 .max_downscale_src_width = 4096, /*up to 4K*/
802 .disable_pplib_wm_range = false,
803 .scl_reset_length10 = true,
804 .sanity_checks = false,
805 .underflow_assert_delay_us = 0xFFFFFFFF,
806 .dwb_fi_phase = -1, // -1 = disable,
807 .dmub_command_table = true,
808 .pstate_enabled = true,
809 .enable_mem_low_power = {
810 .bits = {
811 .vga = false,
812 .i2c = true,
813 .dscl = true,
814 .cm = true,
815 .mpc = true,
816 .optc = true,
817 .vpg = true,
818 }},
819 .root_clock_optimization = {
820 .bits = {
821 .dpp = false,
822 .dsc = false,/*dscclk and dsc pg*/
823 .hdmistream = false,
824 .hdmichar = false,
825 .dpstream = false,
826 .symclk32_se = false,
827 .symclk32_le = false,
828 .symclk_fe = false,
829 .physymclk = false,
830 .dpiasymclk = false,
831 }
832 },
833 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
834 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
835 .minimum_z8_residency_time = 1, /* Always allow when other conditions are met */
836 .support_eDP1_5 = true,
837 .use_max_lb = true,
838 .force_disable_subvp = false,
839 .exit_idle_opt_for_cursor_updates = true,
840 .using_dml2 = true,
841 .using_dml21 = true,
842 .enable_single_display_2to1_odm_policy = true,
843
844 // must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
845 .enable_double_buffered_dsc_pg_support = true,
846 .enable_dp_dig_pixel_rate_div_policy = 1,
847 .allow_sw_cursor_fallback = false,
848 .psp_disabled_wa = true,
849 .alloc_extra_way_for_cursor = true,
850 .min_prefetch_in_strobe_ns = 60000, // 60us
851 .disable_unbounded_requesting = false,
852 .dcc_meta_propagation_delay_us = 10,
853 .disable_timeout = true,
854 .min_disp_clk_khz = 50000,
855 .static_screen_wait_frames = 2,
856 .disable_z10 = false,
857 .ignore_pg = true,
858 .disable_stutter_for_wm_program = true,
859 .min_deep_sleep_dcfclk_khz = 8000,
860 .replay_skip_crtc_disabled = true,
861 .psr_skip_crtc_disable = true,
862 };
863
864 static const struct dc_check_config config_defaults = {
865 .enable_legacy_fast_update = false,
866 };
867
dcn42b_aux_engine_create(struct dc_context * ctx,uint32_t inst)868 static struct dce_aux *dcn42b_aux_engine_create(
869 struct dc_context *ctx,
870 uint32_t inst)
871 {
872 struct aux_engine_dce110 *aux_engine =
873 kzalloc_obj(struct aux_engine_dce110);
874
875 if (!aux_engine)
876 return NULL;
877
878 #undef REG_STRUCT
879 #define REG_STRUCT aux_engine_regs
880 aux_engine_regs_init(0),
881 aux_engine_regs_init(1),
882 aux_engine_regs_init(2);
883 /* Not in DCN42B:
884 * aux_engine_regs_init(3),
885 * aux_engine_regs_init(4);
886 */
887 dce110_aux_engine_construct(aux_engine, ctx, inst,
888 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
889 &aux_engine_regs[inst],
890 &aux_mask,
891 &aux_shift,
892 ctx->dc->caps.extended_aux_timeout_support);
893
894 return &aux_engine->base;
895 }
896
897 #define i2c_inst_regs_init(id) \
898 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
899
900 static struct dce_i2c_registers i2c_hw_regs[5];
901
902 static const struct dce_i2c_shift i2c_shifts = {
903 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
904 };
905 static const struct dce_i2c_mask i2c_masks = {
906 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)
907 };
908
909 /* ========================================================== */
910
911 /*
912 * DPIA index | Preferred Encoder | Host Router
913 * 0 | C | 0
914 * 1 | First Available | 0
915 * 2 | D | 1
916 * 3 | First Available | 1
917 * 4 | E | 2
918 * 5 | First Available | 2
919 */
920 /* ========================================================== */
921 /* DPIA is not included in DCN42B */
922 /*
923 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
924 ENGINE_ID_DIGC,
925 ENGINE_ID_DIGC,
926 ENGINE_ID_DIGD,
927 ENGINE_ID_DIGD,
928 ENGINE_ID_DIGE,
929 ENGINE_ID_DIGE
930 };
931
932 static enum engine_id dcn42b_get_preferred_eng_id_dpia(unsigned int dpia_index)
933 {
934 return dpia_to_preferred_enc_id_table[dpia_index];
935 }
936 */
937
dcn42b_i2c_hw_create(struct dc_context * ctx,uint32_t inst)938 static struct dce_i2c_hw *dcn42b_i2c_hw_create(
939 struct dc_context *ctx,
940 uint32_t inst)
941 {
942 struct dce_i2c_hw *dce_i2c_hw =
943 kzalloc_obj(struct dce_i2c_hw);
944
945 if (!dce_i2c_hw)
946 return NULL;
947
948 #undef REG_STRUCT
949 #define REG_STRUCT i2c_hw_regs
950 i2c_inst_regs_init(1);
951 /* Not in DCN42B:
952 * i2c_inst_regs_init(2),
953 * i2c_inst_regs_init(3),
954 * i2c_inst_regs_init(4),
955 * i2c_inst_regs_init(5);
956 */
957 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
958 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
959
960 return dce_i2c_hw;
961 }
962
dcn42b_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)963 static struct clock_source *dcn42b_clock_source_create(
964 struct dc_context *ctx,
965 struct dc_bios *bios,
966 enum clock_source_id id,
967 const struct dce110_clk_src_regs *regs,
968 bool dp_clk_src)
969 {
970 struct dce110_clk_src *clk_src =
971 kzalloc_obj(struct dce110_clk_src);
972
973 if (!clk_src)
974 return NULL;
975
976 if (dcn401_clk_src_construct(clk_src, ctx, bios, id,
977 regs, &cs_shift, &cs_mask)) {
978 clk_src->base.dp_clk_src = dp_clk_src;
979 return &clk_src->base;
980 }
981
982 kfree(clk_src);
983 BREAK_TO_DEBUGGER();
984 return NULL;
985 }
986
dcn42b_hubbub_create(struct dc_context * ctx)987 static struct hubbub *dcn42b_hubbub_create(struct dc_context *ctx)
988 {
989 int i;
990
991 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
992
993 if (!hubbub3)
994 return NULL;
995
996 #undef REG_STRUCT
997 #define REG_STRUCT hubbub_reg
998 hubbub_reg_init();
999
1000 #undef REG_STRUCT
1001 #define REG_STRUCT vmid_regs
1002 vmid_regs_init(0),
1003 vmid_regs_init(1),
1004 vmid_regs_init(2),
1005 vmid_regs_init(3),
1006 vmid_regs_init(4),
1007 vmid_regs_init(5),
1008 vmid_regs_init(6),
1009 vmid_regs_init(7),
1010 vmid_regs_init(8),
1011 vmid_regs_init(9),
1012 vmid_regs_init(10),
1013 vmid_regs_init(11),
1014 vmid_regs_init(12),
1015 vmid_regs_init(13),
1016 vmid_regs_init(14),
1017 vmid_regs_init(15);
1018
1019 hubbub42_construct(hubbub3, ctx,
1020 &hubbub_reg,
1021 &hubbub_shift,
1022 &hubbub_mask,
1023 DCN42_DEFAULT_DET_SIZE,
1024 8,
1025 DCN42_CRB_SIZE_KB);
1026 for (i = 0; i < res_cap_dcn42b.num_vmid; i++) {
1027 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1028
1029 vmid->ctx = ctx;
1030
1031 vmid->regs = &vmid_regs[i];
1032 vmid->shifts = &vmid_shifts;
1033 vmid->masks = &vmid_masks;
1034 }
1035
1036 return &hubbub3->base;
1037 }
1038
dcn42b_hubp_create(struct dc_context * ctx,uint32_t inst)1039 static struct hubp *dcn42b_hubp_create(
1040 struct dc_context *ctx,
1041 uint32_t inst)
1042 {
1043 struct dcn20_hubp *hubp2 =
1044 kzalloc_obj(struct dcn20_hubp);
1045
1046 if (!hubp2)
1047 return NULL;
1048
1049 #undef REG_STRUCT
1050 #define REG_STRUCT hubp_regs
1051 hubp_regs_init(0),
1052 hubp_regs_init(1),
1053 hubp_regs_init(2),
1054 hubp_regs_init(3);
1055
1056 if (hubp42_construct(hubp2, ctx, inst,
1057 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1058 return &hubp2->base;
1059
1060 BREAK_TO_DEBUGGER();
1061 kfree(hubp2);
1062 return NULL;
1063 }
1064 static const struct dc_panel_config dcn42b_panel_config_defaults = {
1065 .psr = {
1066 .disable_psr = false,
1067 .disallow_psrsu = true,
1068 .disallow_replay = false,
1069 },
1070 .ilr = {
1071 .optimize_edp_link_rate = true,
1072 },
1073 };
1074
dcn42b_dpp_destroy(struct dpp ** dpp)1075 static void dcn42b_dpp_destroy(struct dpp **dpp)
1076 {
1077 kfree(TO_DCN42_DPP(*dpp));
1078 *dpp = NULL;
1079 }
1080
dcn42b_dpp_create(struct dc_context * ctx,uint32_t inst)1081 static struct dpp *dcn42b_dpp_create(
1082 struct dc_context *ctx,
1083 uint32_t inst)
1084 {
1085 struct dcn42_dpp *dpp42b =
1086 kzalloc_obj(struct dcn42_dpp);
1087
1088 if (!dpp42b)
1089 return NULL;
1090
1091 #undef REG_STRUCT
1092 #define REG_STRUCT dpp_regs
1093 dpp_regs_init(0),
1094 dpp_regs_init(1),
1095 dpp_regs_init(2),
1096 dpp_regs_init(3);
1097
1098 if (dpp42_construct(dpp42b, ctx, inst,
1099 &dpp_regs[inst], &tf_shift, &tf_mask))
1100 return &dpp42b->base;
1101
1102 BREAK_TO_DEBUGGER();
1103 kfree(dpp42b);
1104 return NULL;
1105 }
1106
dcn42b_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1107 static struct mpc *dcn42b_mpc_create(
1108 struct dc_context *ctx,
1109 int num_mpcc,
1110 int num_rmu)
1111 {
1112 struct dcn42_mpc *mpc42b = kzalloc_obj(struct dcn42_mpc);
1113
1114 if (!mpc42b)
1115 return NULL;
1116
1117 #undef REG_STRUCT
1118 #define REG_STRUCT mpc_regs
1119 dcn_mpc_regs_init();
1120
1121 dcn42_mpc_construct(mpc42b, ctx,
1122 &mpc_regs,
1123 &mpc_shift,
1124 &mpc_mask,
1125 num_mpcc,
1126 num_rmu);
1127
1128 return &mpc42b->base;
1129 }
1130
dcn42b_opp_create(struct dc_context * ctx,uint32_t inst)1131 static struct output_pixel_processor *dcn42b_opp_create(
1132 struct dc_context *ctx, uint32_t inst)
1133 {
1134 struct dcn20_opp *opp4 =
1135 kzalloc_obj(struct dcn20_opp);
1136
1137 if (!opp4) {
1138 BREAK_TO_DEBUGGER();
1139 return NULL;
1140 }
1141
1142 #undef REG_STRUCT
1143 #define REG_STRUCT opp_regs
1144 opp_regs_init(0),
1145 opp_regs_init(1),
1146 opp_regs_init(2);
1147 //DCN42B has 3 OPP Pipes
1148 //opp_regs_init(3);
1149 dcn20_opp_construct(opp4, ctx, inst,
1150 &opp_regs[inst], &opp_shift, &opp_mask);
1151 return &opp4->base;
1152 }
1153
dcn42b_timing_generator_create(struct dc_context * ctx,uint32_t instance)1154 static struct timing_generator *dcn42b_timing_generator_create(
1155 struct dc_context *ctx,
1156 uint32_t instance)
1157 {
1158 struct optc *tgn10 =
1159 kzalloc_obj(struct optc);
1160
1161 if (!tgn10)
1162 return NULL;
1163 #undef REG_STRUCT
1164 #define REG_STRUCT optc_regs
1165 optc_regs_init(0),
1166 optc_regs_init(1),
1167 optc_regs_init(2);
1168 //optc_regs_init(3);
1169 tgn10->base.inst = instance;
1170 tgn10->base.ctx = ctx;
1171
1172 tgn10->tg_regs = &optc_regs[instance];
1173 tgn10->tg_shift = &optc_shift;
1174 tgn10->tg_mask = &optc_mask;
1175
1176 dcn42_timing_generator_init(tgn10);
1177
1178 return &tgn10->base;
1179 }
1180
1181 static const struct encoder_feature_support link_enc_feature = {
1182 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1183 .max_hdmi_pixel_clock = 600000,
1184 .hdmi_ycbcr420_supported = true,
1185 .dp_ycbcr420_supported = true,
1186 .fec_supported = true,
1187 .flags.bits.IS_HBR2_CAPABLE = true,
1188 .flags.bits.IS_HBR3_CAPABLE = true,
1189 .flags.bits.IS_TPS3_CAPABLE = true,
1190 .flags.bits.IS_TPS4_CAPABLE = true};
1191
dcn42b_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1192 static struct link_encoder *dcn42b_link_encoder_create(
1193 struct dc_context *ctx,
1194 const struct encoder_init_data *enc_init_data)
1195 {
1196 struct dcn20_link_encoder *enc20 =
1197 kzalloc_obj(struct dcn20_link_encoder);
1198
1199 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1200 return NULL;
1201
1202 #undef REG_STRUCT
1203 #define REG_STRUCT link_enc_aux_regs
1204 aux_regs_init(0),
1205 aux_regs_init(1),
1206 aux_regs_init(2);
1207 /*
1208 * Not included in DCN42B:
1209 * aux_regs_init(3),
1210 * aux_regs_init(4);
1211 */
1212 #undef REG_STRUCT
1213 #define REG_STRUCT link_enc_hpd_regs
1214 hpd_regs_init(0),
1215 hpd_regs_init(1),
1216 hpd_regs_init(2);
1217 /*
1218 * Not included in DCN42B:
1219 * hpd_regs_init(3),
1220 * hpd_regs_init(4);
1221 */
1222 #undef REG_STRUCT
1223 #define REG_STRUCT link_enc_regs
1224 link_regs_init(0, A),
1225 link_regs_init(1, B),
1226 link_regs_init(2, C);
1227 /*
1228 * Not included in DCN42B:
1229 * link_regs_init(3, D),
1230 * link_regs_init(4, E);
1231 */
1232
1233 dcn42_link_encoder_construct(enc20,
1234 enc_init_data,
1235 &link_enc_feature,
1236 &link_enc_regs[enc_init_data->transmitter],
1237 &link_enc_aux_regs[enc_init_data->channel - 1],
1238 &link_enc_hpd_regs[enc_init_data->hpd_source],
1239 &le_shift,
1240 &le_mask);
1241 return &enc20->enc10.base;
1242 }
1243
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1244 static void read_dce_straps(
1245 struct dc_context *ctx,
1246 struct resource_straps *straps)
1247 {
1248 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1249 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1250 }
1251
dcn42b_create_audio(struct dc_context * ctx,unsigned int inst)1252 static struct audio *dcn42b_create_audio(
1253 struct dc_context *ctx, unsigned int inst)
1254 {
1255
1256 #undef REG_STRUCT
1257 #define REG_STRUCT audio_regs
1258 audio_regs_init(0),
1259 audio_regs_init(1),
1260 audio_regs_init(2),
1261 audio_regs_init(3),
1262 audio_regs_init(4);
1263
1264 return dce_audio_create(ctx, inst,
1265 &audio_regs[inst], &audio_shift, &audio_mask);
1266 }
1267
dcn42b_vpg_create(struct dc_context * ctx,uint32_t inst)1268 static struct vpg *dcn42b_vpg_create(
1269 struct dc_context *ctx,
1270 uint32_t inst)
1271 {
1272 struct dcn31_vpg *vpg4 = kzalloc_obj(struct dcn31_vpg);
1273
1274 if (!vpg4)
1275 return NULL;
1276
1277 #undef REG_STRUCT
1278 #define REG_STRUCT vpg_regs
1279 vpg_regs_init(0),
1280 vpg_regs_init(1),
1281 vpg_regs_init(2),
1282 vpg_regs_init(3),
1283 vpg_regs_init(4),
1284 vpg_regs_init(5),
1285 vpg_regs_init(6),
1286 vpg_regs_init(7),
1287 vpg_regs_init(8),
1288 vpg_regs_init(9);
1289 vpg31_construct(vpg4, ctx, inst,
1290 &vpg_regs[inst],
1291 &vpg_shift,
1292 &vpg_mask);
1293
1294 return &vpg4->base;
1295 }
1296
dcn42b_apg_create(struct dc_context * ctx,uint32_t inst)1297 static struct apg *dcn42b_apg_create(
1298 struct dc_context *ctx,
1299 uint32_t inst)
1300 {
1301 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1302
1303 if (!apg31)
1304 return NULL;
1305
1306 #undef REG_STRUCT
1307 #define REG_STRUCT apg_regs
1308 apg_regs_init(0),
1309 apg_regs_init(1),
1310 apg_regs_init(2),
1311 apg_regs_init(3),
1312 apg_regs_init(4),
1313 apg_regs_init(5),
1314 apg_regs_init(6),
1315 apg_regs_init(7),
1316 apg_regs_init(8),
1317 apg_regs_init(9);
1318
1319 apg31_construct(apg31, ctx, inst,
1320 &apg_regs[inst],
1321 &apg_shift,
1322 &apg_mask);
1323
1324 return &apg31->base;
1325 }
1326
dcn42b_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1327 static struct stream_encoder *dcn42b_stream_encoder_create(
1328 enum engine_id eng_id,
1329 struct dc_context *ctx)
1330 {
1331 struct dcn10_stream_encoder *enc1;
1332 struct vpg *vpg;
1333 struct apg *apg;
1334
1335 uint32_t vpg_inst;
1336 uint32_t apg_inst;
1337
1338 /* Mapping of VPG, DME register blocks to DIO block instance */
1339 if (eng_id <= ENGINE_ID_DIGF) {
1340 vpg_inst = eng_id;
1341 apg_inst = eng_id;
1342 } else
1343 return NULL;
1344
1345 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1346 vpg = dcn42b_vpg_create(ctx, vpg_inst);
1347 apg = dcn42b_apg_create(ctx, apg_inst);
1348
1349 if (!enc1 || !vpg || !apg) {
1350 kfree(enc1);
1351 kfree(vpg);
1352 kfree(apg);
1353 return NULL;
1354 }
1355 #undef REG_STRUCT
1356 #define REG_STRUCT stream_enc_regs
1357 stream_enc_regs_init(0),
1358 stream_enc_regs_init(1),
1359 stream_enc_regs_init(2);
1360 /*
1361 * stream_enc_regs_init(3),
1362 * stream_enc_regs_init(4);
1363 */
1364
1365 dcn42_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1366 eng_id, vpg, apg,
1367 &stream_enc_regs[eng_id],
1368 &se_shift, &se_mask);
1369 return &enc1->base;
1370 }
1371
dcn42b_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1372 static struct hpo_dp_stream_encoder *dcn42b_hpo_dp_stream_encoder_create(
1373 enum engine_id eng_id,
1374 struct dc_context *ctx)
1375 {
1376 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1377 struct vpg *vpg;
1378 struct apg *apg;
1379 uint32_t hpo_dp_inst;
1380 uint32_t vpg_inst;
1381 uint32_t apg_inst;
1382
1383 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1384 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1385
1386 /* Mapping of VPG register blocks to HPO DP block instance:
1387 * VPG[6] -> HPO_DP[0]
1388 * VPG[7] -> HPO_DP[1]
1389 * VPG[8] -> HPO_DP[2]
1390 * VPG[9] -> HPO_DP[3]
1391 */
1392 //specific to DCN42B: regVPG6..regVPG9 are the four HPO DP VPGs
1393 vpg_inst = hpo_dp_inst + 6;
1394
1395 /* Mapping of APG register blocks to HPO DP block instance:
1396 * APG[6] -> HPO_DP[0]
1397 * APG[7] -> HPO_DP[1]
1398 * APG[8] -> HPO_DP[2]
1399 * APG[9] -> HPO_DP[3]
1400 */
1401 //specific to DCN42B: APG slots 6..9 correspond to HPO DP encoders 0..3
1402 apg_inst = hpo_dp_inst + 6;
1403
1404 /* allocate HPO stream encoder and create VPG sub-block */
1405 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1406 vpg = dcn42b_vpg_create(ctx, vpg_inst);
1407 apg = dcn42b_apg_create(ctx, apg_inst);
1408
1409 if (!hpo_dp_enc31 || !vpg || !apg) {
1410 kfree(hpo_dp_enc31);
1411 kfree(vpg);
1412 kfree(apg);
1413 return NULL;
1414 }
1415
1416 #undef REG_STRUCT
1417 #define REG_STRUCT hpo_dp_stream_enc_regs
1418 hpo_dp_stream_encoder_reg_init(0),
1419 hpo_dp_stream_encoder_reg_init(1),
1420 hpo_dp_stream_encoder_reg_init(2);
1421 //hpo_dp_stream_encoder_reg_init(3);
1422
1423 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1424 hpo_dp_inst, eng_id, vpg, apg,
1425 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1426 &hpo_dp_se_shift, &hpo_dp_se_mask);
1427
1428 return &hpo_dp_enc31->base;
1429 }
1430
dcn42b_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1431 static struct hpo_dp_link_encoder *dcn42b_hpo_dp_link_encoder_create(
1432 uint8_t inst,
1433 struct dc_context *ctx)
1434 {
1435 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1436
1437 /* allocate HPO link encoder */
1438 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1439 if (!hpo_dp_enc31)
1440 return NULL; /* out of memory */
1441
1442 /* DCN42B has 2 HPO DP link encoders */
1443 #undef REG_STRUCT
1444 #define REG_STRUCT hpo_dp_link_enc_regs
1445 hpo_dp_link_encoder_reg_init(0),
1446 hpo_dp_link_encoder_reg_init(1);
1447
1448 hpo_dp_link_encoder42_construct(hpo_dp_enc31, ctx, inst,
1449 &hpo_dp_link_enc_regs[inst],
1450 &hpo_dp_le_shift, &hpo_dp_le_mask);
1451
1452 return &hpo_dp_enc31->base;
1453 }
1454
dcn42b_hwseq_create(struct dc_context * ctx)1455 static struct dce_hwseq *dcn42b_hwseq_create(
1456 struct dc_context *ctx)
1457 {
1458 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1459
1460 #undef REG_STRUCT
1461 #define REG_STRUCT hwseq_reg
1462 hwseq_reg_init();
1463
1464 if (hws) {
1465 hws->ctx = ctx;
1466 hws->regs = &hwseq_reg;
1467 hws->shifts = &hwseq_shift;
1468 hws->masks = &hwseq_mask;
1469 }
1470
1471 return hws;
1472 }
1473
1474 static const struct resource_create_funcs res_create_funcs = {
1475 .read_dce_straps = read_dce_straps,
1476 .create_audio = dcn42b_create_audio,
1477 .create_stream_encoder = dcn42b_stream_encoder_create,
1478 .create_hpo_dp_stream_encoder = dcn42b_hpo_dp_stream_encoder_create,
1479 .create_hpo_dp_link_encoder = dcn42b_hpo_dp_link_encoder_create,
1480 .create_hwseq = dcn42b_hwseq_create,
1481 };
1482
dcn42b_dsc_destroy(struct display_stream_compressor ** dsc)1483 static void dcn42b_dsc_destroy(struct display_stream_compressor **dsc)
1484 {
1485 kfree(container_of(*dsc, struct dcn401_dsc, base));
1486 *dsc = NULL;
1487 }
1488
dcn42b_resource_destruct(struct dcn42b_resource_pool * pool)1489 static void dcn42b_resource_destruct(struct dcn42b_resource_pool *pool)
1490 {
1491 unsigned int i;
1492
1493 for (i = 0; i < pool->base.stream_enc_count; i++) {
1494 if (pool->base.stream_enc[i] != NULL) {
1495 if (pool->base.stream_enc[i]->vpg != NULL) {
1496 kfree(DCN31_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1497 pool->base.stream_enc[i]->vpg = NULL;
1498 }
1499 if (pool->base.stream_enc[i]->apg != NULL) {
1500 kfree(DCN31_APG_FROM_APG(pool->base.stream_enc[i]->apg));
1501 pool->base.stream_enc[i]->apg = NULL;
1502 }
1503 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1504 pool->base.stream_enc[i] = NULL;
1505 }
1506 }
1507
1508 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1509 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1510 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1511 kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1512 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1513 }
1514 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1515 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1516 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1517 }
1518 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1519 pool->base.hpo_dp_stream_enc[i] = NULL;
1520 }
1521 }
1522
1523 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1524 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1525 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1526 pool->base.hpo_dp_link_enc[i] = NULL;
1527 }
1528 }
1529
1530 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
1531 if (pool->base.dscs[i] != NULL)
1532 dcn42b_dsc_destroy(&pool->base.dscs[i]);
1533 }
1534
1535 if (pool->base.mpc != NULL) {
1536 kfree(TO_DCN20_MPC(pool->base.mpc));
1537 pool->base.mpc = NULL;
1538 }
1539 if (pool->base.hubbub != NULL) {
1540 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1541 pool->base.hubbub = NULL;
1542 }
1543 for (i = 0; i < pool->base.pipe_count; i++) {
1544 if (pool->base.dpps[i] != NULL)
1545 dcn42b_dpp_destroy(&pool->base.dpps[i]);
1546
1547 if (pool->base.ipps[i] != NULL)
1548 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1549
1550 if (pool->base.hubps[i] != NULL) {
1551 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1552 pool->base.hubps[i] = NULL;
1553 }
1554
1555 if (pool->base.irqs != NULL)
1556 dal_irq_service_destroy(&pool->base.irqs);
1557 }
1558
1559 for (i = 0; i < (unsigned int)pool->base.res_cap->num_aux; i++) {
1560 if (pool->base.engines[i] != NULL)
1561 dce110_engine_destroy(&pool->base.engines[i]);
1562 }
1563
1564 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
1565 if (pool->base.hw_i2cs[i] != NULL) {
1566 kfree(pool->base.hw_i2cs[i]);
1567 pool->base.hw_i2cs[i] = NULL;
1568 }
1569 if (pool->base.sw_i2cs[i] != NULL) {
1570 kfree(pool->base.sw_i2cs[i]);
1571 pool->base.sw_i2cs[i] = NULL;
1572 }
1573 }
1574
1575 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
1576 if (pool->base.opps[i] != NULL)
1577 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1578 }
1579
1580 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1581 if (pool->base.timing_generators[i] != NULL) {
1582 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1583 pool->base.timing_generators[i] = NULL;
1584 }
1585 }
1586
1587 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
1588 if (pool->base.dwbc[i] != NULL) {
1589 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1590 pool->base.dwbc[i] = NULL;
1591 }
1592 if (pool->base.mcif_wb[i] != NULL) {
1593 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1594 pool->base.mcif_wb[i] = NULL;
1595 }
1596 }
1597
1598 for (i = 0; i < pool->base.audio_count; i++) {
1599 if (pool->base.audios[i])
1600 dce_aud_destroy(&pool->base.audios[i]);
1601 }
1602
1603 for (i = 0; i < pool->base.clk_src_count; i++) {
1604 if (pool->base.clock_sources[i] != NULL) {
1605 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1606 pool->base.clock_sources[i] = NULL;
1607 }
1608 }
1609
1610 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
1611 if (pool->base.mpc_lut[i] != NULL) {
1612 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1613 pool->base.mpc_lut[i] = NULL;
1614 }
1615 if (pool->base.mpc_shaper[i] != NULL) {
1616 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1617 pool->base.mpc_shaper[i] = NULL;
1618 }
1619 }
1620
1621 if (pool->base.dp_clock_source != NULL) {
1622 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1623 pool->base.dp_clock_source = NULL;
1624 }
1625
1626 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1627 if (pool->base.multiple_abms[i] != NULL)
1628 dce_abm_destroy(&pool->base.multiple_abms[i]);
1629 }
1630
1631 if (pool->base.psr != NULL)
1632 dmub_psr_destroy(&pool->base.psr);
1633
1634 if (pool->base.pg_cntl != NULL)
1635 dcn_pg_cntl_destroy(&pool->base.pg_cntl);
1636 if (pool->base.replay != NULL)
1637 dmub_replay_destroy(&pool->base.replay);
1638 if (pool->base.dccg != NULL)
1639 dcn_dccg_destroy(&pool->base.dccg);
1640
1641 if (pool->base.oem_device != NULL) {
1642 struct dc *dc = pool->base.oem_device->ctx->dc;
1643
1644 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1645 }
1646 }
1647
dcn42b_build_pipe_pix_clk_params(struct pipe_ctx * pipe_ctx)1648 static void dcn42b_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
1649 {
1650 const struct dc_stream_state *stream = pipe_ctx->stream;
1651 struct dc_link *link = stream->link;
1652 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;
1653 struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params;
1654
1655 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1656
1657 if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0)
1658 pixel_clk_params->requested_pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz;
1659
1660 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)
1661 link_enc = link_enc_cfg_get_link_enc(link);
1662 if (link_enc)
1663 pixel_clk_params->encoder_object_id = link_enc->id;
1664
1665 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1666 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1667 /* TODO: un-hardcode*/
1668
1669 /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */
1670
1671 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1672 LINK_RATE_REF_FREQ_IN_KHZ;
1673 pixel_clk_params->flags.ENABLE_SS = 0;
1674 pixel_clk_params->color_depth =
1675 stream->timing.display_color_depth;
1676 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1677 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1678
1679 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1680 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1681
1682 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1683 pixel_clk_params->requested_pix_clk_100hz *= 2;
1684 if (dc_is_tmds_signal(stream->signal) &&
1685 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1686 pixel_clk_params->requested_pix_clk_100hz /= 2;
1687
1688 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1689 pipe_ctx->clock_source,
1690 &pipe_ctx->stream_res.pix_clk_params,
1691 &pipe_ctx->pll_settings);
1692
1693 pixel_clk_params->dio_se_pix_per_cycle = 1;
1694 if (dc_is_tmds_signal(stream->signal) &&
1695 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1696 pixel_clk_params->dio_se_pix_per_cycle = 2;
1697 } else if (dc_is_dp_signal(stream->signal)) {
1698 /* round up to nearest power of 2, or max at 8 pixels per cycle */
1699 if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
1700 pixel_clk_params->dio_se_pix_per_cycle = 8;
1701 } else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
1702 pixel_clk_params->dio_se_pix_per_cycle = 4;
1703 } else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
1704 pixel_clk_params->dio_se_pix_per_cycle = 2;
1705 } else {
1706 pixel_clk_params->dio_se_pix_per_cycle = 1;
1707 }
1708 }
1709 }
1710
dcn42b_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1711 static bool dcn42b_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1712 {
1713 unsigned int i;
1714 uint32_t dwb_count = pool->res_cap->num_dwb;
1715
1716 for (i = 0; i < dwb_count; i++) {
1717 struct dcn30_dwbc *dwbc42 = kzalloc_obj(struct dcn30_dwbc);
1718
1719 if (!dwbc42) {
1720 dm_error("DC: failed to create dwbc42!\n");
1721 return false;
1722 }
1723
1724 #undef REG_STRUCT
1725 #define REG_STRUCT dwbc401_regs
1726 dwbc_regs_dcn401_init(0);
1727
1728 dcn30_dwbc_construct(dwbc42, ctx,
1729 &dwbc401_regs[i],
1730 &dwbc401_shift,
1731 &dwbc401_mask,
1732 i);
1733
1734 pool->dwbc[i] = &dwbc42->base;
1735 }
1736 return true;
1737 }
1738
dcn42b_mmhubbub_init(struct dcn30_mmhubbub * mcif_wb30,struct dc_context * ctx)1739 static void dcn42b_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
1740 struct dc_context *ctx)
1741 {
1742 dcn42_mmhubbub_set_fgcg(
1743 mcif_wb30,
1744 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);
1745 }
1746
dcn42b_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1747 static bool dcn42b_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1748 {
1749 unsigned int i;
1750 uint32_t pipe_count = pool->res_cap->num_dwb;
1751
1752 for (i = 0; i < pipe_count; i++) {
1753 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1754
1755 if (!mcif_wb30) {
1756 dm_error("DC: failed to create mcif_wb30!\n");
1757 return false;
1758 }
1759
1760 #undef REG_STRUCT
1761 #define REG_STRUCT mcif_wb35_regs
1762 mcif_wb_regs_dcn3_init(0);
1763
1764 dcn35_mmhubbub_construct(mcif_wb30, ctx,
1765 &mcif_wb35_regs[i],
1766 &mcif_wb35_shift,
1767 &mcif_wb35_mask,
1768 i);
1769
1770 dcn42b_mmhubbub_init(mcif_wb30, ctx);
1771
1772 pool->mcif_wb[i] = &mcif_wb30->base;
1773 }
1774 return true;
1775 }
1776
dcn42b_dsc_create(struct dc_context * ctx,uint32_t inst)1777 static struct display_stream_compressor *dcn42b_dsc_create(
1778 struct dc_context *ctx, uint32_t inst)
1779 {
1780 struct dcn401_dsc *dsc =
1781 kzalloc_obj(struct dcn401_dsc);
1782
1783 if (!dsc) {
1784 BREAK_TO_DEBUGGER();
1785 return NULL;
1786 }
1787
1788 #undef REG_STRUCT
1789 #define REG_STRUCT dsc_regs
1790 dsc_regs_init(0),
1791 dsc_regs_init(1),
1792 dsc_regs_init(2);
1793 //Not in DCN42B: dsc_regs_init(3);
1794
1795 dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1796 dsc401_set_fgcg(dsc, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1797
1798 dsc->max_image_width = 5760;
1799
1800 return &dsc->base;
1801 }
1802
dcn42b_destroy_resource_pool(struct resource_pool ** pool)1803 static void dcn42b_destroy_resource_pool(struct resource_pool **pool)
1804 {
1805 struct dcn42b_resource_pool *dcn42b_pool = TO_DCN42B_RES_POOL(*pool);
1806
1807 dcn42b_resource_destruct(dcn42b_pool);
1808 kfree(dcn42b_pool);
1809 *pool = NULL;
1810 }
1811
1812 static struct dc_cap_funcs cap_funcs = {
1813 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap};
1814
dcn42b_update_bw_bounding_box_fpu(struct dc * dc,struct clk_bw_params * bw_params)1815 static void dcn42b_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
1816 {
1817 (void)bw_params;
1818 dc_assert_fp_enabled();
1819
1820 if (dc->current_state && dc->current_state->bw_ctx.dml2)
1821 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
1822 }
1823
dcn42b_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1824 static void dcn42b_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1825 {
1826 DC_FP_START();
1827 dcn42b_update_bw_bounding_box_fpu(dc, bw_params);
1828 DC_FP_END();
1829 }
1830
dcn42b_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1831 enum dc_status dcn42b_validate_bandwidth(struct dc *dc,
1832 struct dc_state *context,
1833 enum dc_validate_mode validate_mode)
1834 {
1835 bool out = false;
1836
1837 DC_FP_START();
1838
1839 out = dml2_validate(dc, context, context->bw_ctx.dml2,
1840 validate_mode);
1841
1842 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) {
1843 /*not required for mode enumeration*/
1844 dcn42_decide_zstate_support(dc, context);
1845 }
1846
1847 DC_FP_END();
1848
1849 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1850 }
dcn42b_prepare_mcache_programming(struct dc * dc,struct dc_state * context)1851 void dcn42b_prepare_mcache_programming(struct dc *dc,
1852 struct dc_state *context)
1853 {
1854 if (dc->debug.using_dml21) {
1855 DC_FP_START();
1856 dml2_prepare_mcache_programming(dc, context,
1857 context->power_source == DC_POWER_SOURCE_DC ?
1858 context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2);
1859 DC_FP_END();
1860 }
1861 }
1862 /* Create a minimal link encoder object not associated with a particular
1863 * physical connector.
1864 * resource_funcs.link_enc_create_minimal
1865 */
dcn42b_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1866 static struct link_encoder *dcn42b_link_enc_create_minimal(
1867 struct dc_context *ctx, enum engine_id eng_id)
1868 {
1869 struct dcn20_link_encoder *enc20;
1870
1871 if ((unsigned int)(eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc)
1872 return NULL;
1873
1874 enc20 = kzalloc_obj(struct dcn20_link_encoder);
1875 if (!enc20)
1876 return NULL;
1877
1878 dcn31_link_encoder_construct_minimal(
1879 enc20,
1880 ctx,
1881 &link_enc_feature,
1882 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1883 &le_shift,
1884 &le_mask,
1885 eng_id);
1886
1887 return &enc20->enc10.base;
1888 }
dcn42b_get_panel_config_defaults(struct dc_panel_config * panel_config)1889 static void dcn42b_get_panel_config_defaults(struct dc_panel_config *panel_config)
1890 {
1891 *panel_config = dcn42b_panel_config_defaults;
1892 }
dcn42b_get_max_hw_cursor_size(const struct dc * dc,struct dc_state * state,const struct dc_stream_state * stream)1893 static unsigned int dcn42b_get_max_hw_cursor_size(const struct dc *dc,
1894 struct dc_state *state,
1895 const struct dc_stream_state *stream)
1896 {
1897 (void)state;
1898 (void)stream;
1899
1900 return dc->caps.max_cursor_size;
1901 }
1902
1903 static struct resource_funcs dcn42b_res_pool_funcs = {
1904 .destroy = dcn42b_destroy_resource_pool,
1905 .link_enc_create = dcn42b_link_encoder_create,
1906 .link_enc_create_minimal = dcn42b_link_enc_create_minimal,
1907 .link_encs_assign = link_enc_cfg_link_encs_assign,
1908 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1909 .panel_cntl_create = dcn32_panel_cntl_create,
1910 .validate_bandwidth = dcn42b_validate_bandwidth,
1911 .calculate_wm_and_dlg = NULL,
1912 .populate_dml_pipes = NULL,
1913 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
1914 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
1915 .release_pipe = dcn20_release_pipe,
1916 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1917 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1918 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1919 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1920 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1921 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1922 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
1923 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
1924 .update_bw_bounding_box = dcn42b_update_bw_bounding_box,
1925 .patch_unknown_plane_state = dcn35_patch_unknown_plane_state,
1926 .get_panel_config_defaults = dcn42b_get_panel_config_defaults,
1927 //.get_preferred_eng_id_dpia = dcn42b_get_preferred_eng_id_dpia,
1928 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1929 .add_phantom_pipes = dcn32_add_phantom_pipes,
1930 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
1931 .prepare_mcache_programming = dcn42b_prepare_mcache_programming,
1932 .build_pipe_pix_clk_params = dcn42b_build_pipe_pix_clk_params,
1933 .get_power_profile = dcn401_get_power_profile,
1934 .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe,
1935 .get_default_tiling_info = dcn401_get_default_tiling_info,
1936 .get_max_hw_cursor_size = dcn42b_get_max_hw_cursor_size,
1937 };
1938
dcn42b_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn42b_resource_pool * pool)1939 static bool dcn42b_resource_construct(
1940 uint8_t num_virtual_links,
1941 struct dc *dc,
1942 struct dcn42b_resource_pool *pool)
1943 {
1944 int i;
1945 struct dc_context *ctx = dc->ctx;
1946 struct irq_service_init_data init_data;
1947 uint32_t num_pipes = 4;
1948
1949 #undef REG_STRUCT
1950 #define REG_STRUCT bios_regs
1951 bios_regs_init();
1952
1953 #undef REG_STRUCT
1954 #define REG_STRUCT clk_src_regs
1955 clk_src_regs_init(0, A),
1956 clk_src_regs_init(1, B),
1957 clk_src_regs_init(2, C),
1958 clk_src_regs_init(3, D),
1959 clk_src_regs_init(4, E);
1960
1961 #undef REG_STRUCT
1962 #define REG_STRUCT abm_regs
1963 abm_regs_init(0),
1964 abm_regs_init(1),
1965 abm_regs_init(2);
1966 //abm_regs_init(3);
1967 #undef REG_STRUCT
1968 #define REG_STRUCT dccg_regs
1969 dccg_regs_init();
1970
1971 ctx->dc_bios->regs = &bios_regs;
1972
1973 pool->base.res_cap = &res_cap_dcn42b;
1974
1975 /* max number of pipes for ASIC before checking for pipe fuses */
1976 num_pipes = pool->base.res_cap->num_dpp;
1977 pool->base.funcs = &dcn42b_res_pool_funcs;
1978
1979 /*************************************************
1980 * Resource + asic cap harcoding *
1981 *************************************************/
1982 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1983 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1984 pool->base.pipe_count = num_pipes;
1985 pool->base.mpcc_count = num_pipes;
1986 dc->caps.ips_v2_support = true;
1987 dc->caps.max_downscale_ratio = 600;
1988 dc->caps.i2c_speed_in_khz = 100;
1989 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
1990 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/
1991 dc->caps.max_cursor_size = 64;
1992 dc->caps.max_buffered_cursor_size = 64;
1993 dc->caps.cursor_not_scaled = true;
1994 dc->caps.min_horizontal_blanking_period = 80;
1995 dc->caps.dmdata_alloc_size = 2048;
1996 dc->caps.mall_size_per_mem_channel = 4;
1997 /* total size = mall per channel * num channels * 1024 * 1024 */
1998 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel *
1999 dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2000 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2001 dc->caps.cache_line_size = 64;
2002 dc->caps.cache_num_ways = 16;
2003
2004 /* Calculate the available MALL space */
2005 dc->caps.max_cab_allocation_bytes =
2006 dcn32_calc_num_avail_chans_for_mall(dc, dc->ctx->dc_bios->vram_info.num_chans) *
2007 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
2008 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
2009
2010 dc->caps.subvp_fw_processing_delay_us = 15;
2011 dc->caps.subvp_drr_max_vblank_margin_us = 40;
2012 dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
2013 dc->caps.subvp_swath_height_margin_lines = 16;
2014 dc->caps.subvp_pstate_allow_width_us = 20;
2015 dc->caps.subvp_vertical_int_margin_us = 30;
2016 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
2017
2018 dc->caps.max_slave_planes = 2;
2019 dc->caps.max_slave_yuv_planes = 2;
2020 dc->caps.max_slave_rgb_planes = 2;
2021 dc->caps.post_blend_color_processing = true;
2022 dc->caps.force_dp_tps4_for_cp2520 = true;
2023 if (dc->config.forceHBR2CP2520)
2024 dc->caps.force_dp_tps4_for_cp2520 = false;
2025 dc->caps.dp_hdmi21_pcon_support = true;
2026 dc->caps.dp_hpo = true;
2027 dc->caps.dp_hdmi21_pcon_support = true;
2028 dc->caps.edp_dsc_support = true;
2029 dc->caps.extended_aux_timeout_support = true;
2030 dc->caps.dmcub_support = true;
2031 dc->caps.is_apu = true;
2032 dc->caps.seamless_odm = true;
2033 dc->caps.zstate_support = true;
2034 dc->caps.ips_support = true;
2035 dc->caps.max_v_total = (1 << 15) - 1;
2036 dc->caps.vtotal_limited_by_fp2 = true;
2037
2038 /* Color pipeline capabilities */
2039 dc->caps.color.dpp.dcn_arch = 1;
2040 dc->caps.color.dpp.input_lut_shared = 0;
2041 dc->caps.color.dpp.icsc = 1;
2042 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2043 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2044 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2045 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2046 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2047 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2048 dc->caps.color.dpp.post_csc = 1;
2049 dc->caps.color.dpp.gamma_corr = 1;
2050 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2051
2052 dc->caps.color.dpp.hw_3d_lut = 0;
2053 dc->caps.color.dpp.ogam_ram = 0;
2054 // no OGAM ROM on DCN2 and later ASICs
2055 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2056 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2057 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2058 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2059 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2060 dc->caps.color.dpp.ocsc = 0;
2061
2062 dc->caps.color.mpc.gamut_remap = 1;
2063 //configurable to be before or after BLND in MPCC
2064 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;
2065 dc->caps.color.mpc.num_rmcm_3dluts = 2;
2066 dc->caps.color.mpc.ogam_ram = 1;
2067 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2068 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2069 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2070 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2071 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2072 dc->caps.color.mpc.ocsc = 1;
2073 dc->caps.color.mpc.preblend = true;
2074 dc->caps.color.mpc.mcm_3d_lut_caps.dma_3d_lut = 1;
2075 dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_9 = 1;
2076 dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_17 = 1;
2077 dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.linear_1d = 1;
2078 dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1;
2079 dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1;
2080 dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12msb = 1;
2081 dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1;
2082 dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1;
2083 dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1;
2084 dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1;
2085 dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut = 1;
2086 dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17 = 1;
2087 dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33 = 1;
2088 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.linear_1d = 1;
2089 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1;
2090 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1;
2091 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12msb = 1;
2092 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1;
2093 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1;
2094 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1;
2095 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1;
2096 dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
2097
2098 dc->caps.num_of_host_routers = 0;
2099 dc->caps.num_of_dpias_per_host_router = 0;
2100
2101 /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
2102 * to provide some margin.
2103 * It's expected for furture ASIC to have equal or higher value, in order to
2104 * have determinstic power improvement from generate to genration.
2105 * (i.e., we should not expect new ASIC generation with lower vmin rate)
2106 */
2107 dc->caps.max_disp_clock_khz_at_vmin = 650000;
2108 dc->config.use_spl = true;
2109 dc->config.prefer_easf = true;
2110
2111 dc->config.dcn_sharpness_range.sdr_rgb_min = 0;
2112 dc->config.dcn_sharpness_range.sdr_rgb_max = 1750;
2113 dc->config.dcn_sharpness_range.sdr_rgb_mid = 750;
2114 dc->config.dcn_sharpness_range.sdr_yuv_min = 0;
2115 dc->config.dcn_sharpness_range.sdr_yuv_max = 3500;
2116 dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500;
2117 dc->config.dcn_sharpness_range.hdr_rgb_min = 0;
2118 dc->config.dcn_sharpness_range.hdr_rgb_max = 2750;
2119 dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500;
2120
2121 dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0;
2122 dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250;
2123 dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250;
2124 dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0;
2125 dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500;
2126 dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500;
2127 dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0;
2128 dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750;
2129 dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500;
2130
2131 dc->config.use_pipe_ctx_sync_logic = true;
2132 dc->config.dc_mode_clk_limit_support = false;
2133 dc->config.enable_windowed_mpo_odm = true;
2134 dc->config.set_pipe_unlock_order = true; /* Need to ensure DET gets freed before allocating */
2135 /* Use psp mailbox to enable assr */
2136 dc->config.use_assr_psp_message = true;
2137 /* dcn42 and afterward always support external panel replay */
2138 dc->config.frame_update_cmd_version2 = true;
2139
2140 /* read VBIOS LTTPR caps */
2141 {
2142 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2143 enum bp_result bp_query_result;
2144 uint8_t is_vbios_lttpr_enable = 0;
2145
2146 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2147 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2148 }
2149
2150 dc->caps.vbios_lttpr_aware = true;
2151 }
2152 dc->check_config = config_defaults;
2153
2154 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2155 dc->debug = debug_defaults_drv;
2156 /*HW default is to have all the FGCG enabled, SW no need to program them*/
2157 dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;
2158 // Init the vm_helper
2159 if (dc->vm_helper)
2160 vm_helper_init(dc->vm_helper, 16);
2161
2162 /*************************************************
2163 * Create resources *
2164 *************************************************/
2165
2166 /* Clock Sources for Pixel Clock*/
2167 pool->base.clock_sources[DCN401_CLK_SRC_PLL0] =
2168 dcn42b_clock_source_create(ctx, ctx->dc_bios,
2169 CLOCK_SOURCE_COMBO_PHY_PLL0,
2170 &clk_src_regs[0], false);
2171 pool->base.clock_sources[DCN401_CLK_SRC_PLL1] =
2172 dcn42b_clock_source_create(ctx, ctx->dc_bios,
2173 CLOCK_SOURCE_COMBO_PHY_PLL1,
2174 &clk_src_regs[1], false);
2175 pool->base.clock_sources[DCN401_CLK_SRC_PLL2] =
2176 dcn42b_clock_source_create(ctx, ctx->dc_bios,
2177 CLOCK_SOURCE_COMBO_PHY_PLL2,
2178 &clk_src_regs[2], false);
2179
2180 pool->base.clk_src_count = DCN401_CLK_SRC_TOTAL;
2181
2182 /* todo: not reuse phy_pll registers */
2183 pool->base.dp_clock_source =
2184 dcn42b_clock_source_create(ctx, ctx->dc_bios,
2185 CLOCK_SOURCE_ID_DP_DTO,
2186 &clk_src_regs[0], true);
2187
2188 for (i = 0; i < (int)pool->base.clk_src_count; i++) {
2189 if (pool->base.clock_sources[i] == NULL) {
2190 dm_error("DC: failed to create clock sources!\n");
2191 BREAK_TO_DEBUGGER();
2192 goto create_fail;
2193 }
2194 }
2195
2196 /* DCCG */
2197 pool->base.dccg = dccg42_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2198 if (pool->base.dccg == NULL) {
2199 dm_error("DC: failed to create dccg!\n");
2200 BREAK_TO_DEBUGGER();
2201 goto create_fail;
2202 }
2203
2204 #undef REG_STRUCT
2205 #define REG_STRUCT pg_cntl_regs
2206 pg_cntl_dcn42b_regs_init();
2207
2208 pool->base.pg_cntl = pg_cntl42_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
2209 if (pool->base.pg_cntl == NULL) {
2210 dm_error("DC: failed to create power gate control!\n");
2211 BREAK_TO_DEBUGGER();
2212 goto create_fail;
2213 }
2214 /* IRQ Service */
2215 init_data.ctx = dc->ctx;
2216 pool->base.irqs = dal_irq_service_dcn42_create(&init_data);
2217 if (!pool->base.irqs)
2218 goto create_fail;
2219
2220 /* HUBBUB */
2221 pool->base.hubbub = dcn42b_hubbub_create(ctx);
2222 if (pool->base.hubbub == NULL) {
2223 BREAK_TO_DEBUGGER();
2224 dm_error("DC: failed to create hubbub!\n");
2225 goto create_fail;
2226 }
2227
2228 /* HUBPs, DPPs, OPPs, TGs, ABMs */
2229 /* HUBPs */
2230 for (i = 0; i < pool->base.res_cap->num_dpp; i++) {
2231 pool->base.hubps[i] = dcn42b_hubp_create(ctx, i);
2232 if (pool->base.hubps[i] == NULL) {
2233 BREAK_TO_DEBUGGER();
2234 dm_error("DC: failed to create hubps!\n");
2235 goto create_fail;
2236 }
2237 }
2238
2239 /* DPPs */
2240 for (i = 0; i < pool->base.res_cap->num_dpp; i++) {
2241 pool->base.dpps[i] = dcn42b_dpp_create(ctx, i);
2242 if (pool->base.dpps[i] == NULL) {
2243 BREAK_TO_DEBUGGER();
2244 dm_error("DC: failed to create dpps!\n");
2245 goto create_fail;
2246 }
2247 }
2248
2249 /* OPPs */
2250 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2251 pool->base.opps[i] = dcn42b_opp_create(ctx, i);
2252 if (pool->base.opps[i] == NULL) {
2253 BREAK_TO_DEBUGGER();
2254 dm_error("DC: failed to create output pixel processor!\n");
2255 goto create_fail;
2256 }
2257 }
2258
2259 /* TGs */
2260 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2261 pool->base.timing_generators[i] = dcn42b_timing_generator_create(ctx, i);
2262 if (pool->base.timing_generators[i] == NULL) {
2263 BREAK_TO_DEBUGGER();
2264 dm_error("DC: failed to create tg!\n");
2265 goto create_fail;
2266 }
2267 }
2268
2269 /* ABMs */
2270 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2271 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2272 &abm_regs[i],
2273 &abm_shift,
2274 &abm_mask);
2275 if (pool->base.multiple_abms[i] == NULL) {
2276 dm_error("DC: failed to create abm for pipe %d!\n", i);
2277 BREAK_TO_DEBUGGER();
2278 goto create_fail;
2279 }
2280 }
2281
2282 /* PSR */
2283 pool->base.psr = dmub_psr_create(ctx);
2284 if (pool->base.psr == NULL) {
2285 dm_error("DC: failed to create psr obj!\n");
2286 BREAK_TO_DEBUGGER();
2287 goto create_fail;
2288 }
2289
2290 /* Replay */
2291 pool->base.replay = dmub_replay_create(ctx);
2292 if (pool->base.replay == NULL) {
2293 dm_error("DC: failed to create replay obj!\n");
2294 BREAK_TO_DEBUGGER();
2295 goto create_fail;
2296 }
2297
2298 /* Auto Test */
2299
2300 /* MPCCs */
2301 pool->base.mpc = dcn42b_mpc_create(ctx, pool->base.mpcc_count,
2302 pool->base.res_cap->num_mpc_3dlut);
2303 if (pool->base.mpc == NULL) {
2304 BREAK_TO_DEBUGGER();
2305 dm_error("DC: failed to create mpc!\n");
2306 goto create_fail;
2307 }
2308
2309 /* DSCs */
2310 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2311 pool->base.dscs[i] = dcn42b_dsc_create(ctx, i);
2312 if (pool->base.dscs[i] == NULL) {
2313 BREAK_TO_DEBUGGER();
2314 dm_error("DC: failed to create display stream compressor %d!\n", i);
2315 goto create_fail;
2316 }
2317 }
2318
2319 /* DWB */
2320 if (!dcn42b_dwbc_create(ctx, &pool->base)) {
2321 BREAK_TO_DEBUGGER();
2322 dm_error("DC: failed to create dwbc!\n");
2323 goto create_fail;
2324 }
2325
2326 /* MMHUBBUB */
2327 if (!dcn42b_mmhubbub_create(ctx, &pool->base)) {
2328 BREAK_TO_DEBUGGER();
2329 dm_error("DC: failed to create mcif_wb!\n");
2330 goto create_fail;
2331 }
2332
2333 /* AUX */
2334 for (i = 0; i < pool->base.res_cap->num_aux; i++) {
2335 pool->base.engines[i] = dcn42b_aux_engine_create(ctx, i);
2336 if (pool->base.engines[i] == NULL) {
2337 BREAK_TO_DEBUGGER();
2338 dm_error(
2339 "DC:failed to create aux engine!!\n");
2340 goto create_fail;
2341 }
2342 }
2343
2344 /* I2C */
2345 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2346 pool->base.hw_i2cs[i] = dcn42b_i2c_hw_create(ctx, i);
2347 if (pool->base.hw_i2cs[i] == NULL) {
2348 BREAK_TO_DEBUGGER();
2349 dm_error(
2350 "DC:failed to create hw i2c!!\n");
2351 goto create_fail;
2352 }
2353 pool->base.sw_i2cs[i] = NULL;
2354 }
2355 /* DCN4.2B has 0 DPIA */
2356 /*pool->base.usb4_dpia_count = dc->caps.num_of_host_routers * dc->caps.num_of_dpias_per_host_router;
2357 if (dc->debug.dpia_debug.bits.disable_dpia)*/
2358 pool->base.usb4_dpia_count = 0;
2359
2360 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2361 if (!resource_construct(num_virtual_links, dc, &pool->base,
2362 &res_create_funcs))
2363 goto create_fail;
2364
2365 /* HW Sequencer init functions and Plane caps */
2366 dcn42b_hw_sequencer_init_functions(dc);
2367
2368 dc->caps.max_planes = pool->base.pipe_count;
2369 dc->config.dp_connector_no_native_i2c = true;
2370
2371 for (i = 0; i < (int)dc->caps.max_planes; ++i)
2372 dc->caps.planes[i] = plane_cap;
2373
2374 dc->caps.max_odm_combine_factor = 4;
2375
2376 dc->cap_funcs = cap_funcs;
2377 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
2378
2379 // For now enable SDPIF_REQUEST_RATE_LIMIT on DCN4_01 when vram_info.num_chans provided
2380 if (dc->config.sdpif_request_limit_words_per_umc == 0)
2381 dc->config.sdpif_request_limit_words_per_umc = 16;
2382
2383 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2384 /*this will use real soc clock table*/
2385 dc->dml2_options.use_native_soc_bb_construction = true;
2386 dc->dml2_options.minimize_dispclk_using_odm = false;
2387 if (dc->config.EnableMinDispClkODM)
2388 dc->dml2_options.minimize_dispclk_using_odm = true;
2389 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
2390 dc->dml2_options.map_dc_pipes_with_callbacks = true;
2391 dc->dml2_options.force_tdlut_enable = true;
2392
2393 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2394 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch =
2395 &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2396 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2397 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes =
2398 pool->base.funcs->calculate_mall_ways_from_bytes;
2399
2400 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2401 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2402 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2403 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2404
2405 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2406 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2407
2408 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2409 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2410 dc->dml2_options.mall_cfg.max_cab_allocation_bytes =
2411 dc->caps.max_cab_allocation_bytes;
2412 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2413 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2414 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2415 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2416
2417 dc->dml2_options.max_segments_per_hubp = 24;
2418 dc->dml2_options.det_segment_size = DCN42_CRB_SEGMENT_SIZE_KB;
2419 dc->dml2_options.gpuvm_enable = true;
2420 dc->dml2_options.hostvm_enable = true;
2421
2422 /* SPL */
2423 dc->caps.scl_caps.sharpener_support = true;
2424
2425 return true;
2426
2427 create_fail:
2428
2429 dcn42b_resource_destruct(pool);
2430
2431 return false;
2432 }
dcn42b_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2433 struct resource_pool *dcn42b_create_resource_pool(
2434 const struct dc_init_data *init_data,
2435 struct dc *dc)
2436 {
2437 struct dcn42b_resource_pool *pool =
2438 kzalloc_obj(struct dcn42b_resource_pool);
2439
2440 if (!pool)
2441 return NULL;
2442
2443 if (dcn42b_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
2444 return &pool->base;
2445
2446 BREAK_TO_DEBUGGER();
2447 kfree(pool);
2448 return NULL;
2449 }
2450