1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "link_encoder.h"
29 #include "stream_encoder.h"
30
31 #include "resource.h"
32 #include "include/irq_service_interface.h"
33 #include "dce110/dce110_resource.h"
34 #include "dce110/dce110_timing_generator.h"
35
36 #include "irq/dce110/irq_service_dce110.h"
37 #include "dce/dce_mem_input.h"
38 #include "dce/dce_transform.h"
39 #include "dce/dce_link_encoder.h"
40 #include "dce/dce_stream_encoder.h"
41 #include "dce/dce_audio.h"
42 #include "dce/dce_opp.h"
43 #include "dce/dce_ipp.h"
44 #include "dce/dce_clock_source.h"
45
46 #include "dce/dce_hwseq.h"
47 #include "dce112/dce112_hwseq.h"
48 #include "dce/dce_abm.h"
49 #include "dce/dce_dmcu.h"
50 #include "dce/dce_aux.h"
51 #include "dce/dce_i2c.h"
52 #include "dce/dce_panel_cntl.h"
53
54 #include "reg_helper.h"
55
56 #include "dce/dce_11_2_d.h"
57 #include "dce/dce_11_2_sh_mask.h"
58
59 #include "dce100/dce100_resource.h"
60 #include "dce112_resource.h"
61
62 #define DC_LOGGER \
63 dc->ctx->logger
64
65 #ifndef mmDP_DPHY_INTERNAL_CTRL
66 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
67 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
68 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
69 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
70 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
71 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
72 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
73 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
74 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
75 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
76 #endif
77
78 #ifndef mmBIOS_SCRATCH_2
79 #define mmBIOS_SCRATCH_0 0x05C9
80 #define mmBIOS_SCRATCH_2 0x05CB
81 #define mmBIOS_SCRATCH_3 0x05CC
82 #define mmBIOS_SCRATCH_6 0x05CF
83 #endif
84
85 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
86 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
87 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
88 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
89 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
90 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
91 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
92 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
93 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
94 #endif
95
96 #ifndef mmDP_DPHY_FAST_TRAINING
97 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
98 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
99 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
100 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
101 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
102 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
103 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
104 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
105 #endif
106
107 enum dce112_clk_src_array_id {
108 DCE112_CLK_SRC_PLL0,
109 DCE112_CLK_SRC_PLL1,
110 DCE112_CLK_SRC_PLL2,
111 DCE112_CLK_SRC_PLL3,
112 DCE112_CLK_SRC_PLL4,
113 DCE112_CLK_SRC_PLL5,
114
115 DCE112_CLK_SRC_TOTAL
116 };
117
118 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
119 {
120 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
121 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
122 },
123 {
124 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
125 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
126 },
127 {
128 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
129 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
130 },
131 {
132 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
133 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
134 },
135 {
136 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
137 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
138 },
139 {
140 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
141 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
142 }
143 };
144
145 /* set register offset */
146 #define SR(reg_name)\
147 .reg_name = mm ## reg_name
148
149 /* set register offset with instance */
150 #define SRI(reg_name, block, id)\
151 .reg_name = mm ## block ## id ## _ ## reg_name
152
153 static const struct dce_dmcu_registers dmcu_regs = {
154 DMCU_DCE110_COMMON_REG_LIST()
155 };
156
157 static const struct dce_dmcu_shift dmcu_shift = {
158 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
159 };
160
161 static const struct dce_dmcu_mask dmcu_mask = {
162 DMCU_MASK_SH_LIST_DCE110(_MASK)
163 };
164
165 static const struct dce_abm_registers abm_regs = {
166 ABM_DCE110_COMMON_REG_LIST()
167 };
168
169 static const struct dce_abm_shift abm_shift = {
170 ABM_MASK_SH_LIST_DCE110(__SHIFT)
171 };
172
173 static const struct dce_abm_mask abm_mask = {
174 ABM_MASK_SH_LIST_DCE110(_MASK)
175 };
176
177 static const struct dce110_aux_registers_shift aux_shift = {
178 DCE_AUX_MASK_SH_LIST(__SHIFT)
179 };
180
181 static const struct dce110_aux_registers_mask aux_mask = {
182 DCE_AUX_MASK_SH_LIST(_MASK)
183 };
184
185 #define ipp_regs(id)\
186 [id] = {\
187 IPP_DCE110_REG_LIST_DCE_BASE(id)\
188 }
189
190 static const struct dce_ipp_registers ipp_regs[] = {
191 ipp_regs(0),
192 ipp_regs(1),
193 ipp_regs(2),
194 ipp_regs(3),
195 ipp_regs(4),
196 ipp_regs(5)
197 };
198
199 static const struct dce_ipp_shift ipp_shift = {
200 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
201 };
202
203 static const struct dce_ipp_mask ipp_mask = {
204 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
205 };
206
207 #define transform_regs(id)\
208 [id] = {\
209 XFM_COMMON_REG_LIST_DCE110(id)\
210 }
211
212 static const struct dce_transform_registers xfm_regs[] = {
213 transform_regs(0),
214 transform_regs(1),
215 transform_regs(2),
216 transform_regs(3),
217 transform_regs(4),
218 transform_regs(5)
219 };
220
221 static const struct dce_transform_shift xfm_shift = {
222 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
223 };
224
225 static const struct dce_transform_mask xfm_mask = {
226 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
227 };
228
229 #define aux_regs(id)\
230 [id] = {\
231 AUX_REG_LIST(id)\
232 }
233
234 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
235 aux_regs(0),
236 aux_regs(1),
237 aux_regs(2),
238 aux_regs(3),
239 aux_regs(4),
240 aux_regs(5)
241 };
242
243 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
244 { DCE_PANEL_CNTL_REG_LIST() }
245 };
246
247 static const struct dce_panel_cntl_shift panel_cntl_shift = {
248 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
249 };
250
251 static const struct dce_panel_cntl_mask panel_cntl_mask = {
252 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
253 };
254
255 #define hpd_regs(id)\
256 [id] = {\
257 HPD_REG_LIST(id)\
258 }
259
260 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
261 hpd_regs(0),
262 hpd_regs(1),
263 hpd_regs(2),
264 hpd_regs(3),
265 hpd_regs(4),
266 hpd_regs(5)
267 };
268
269 #define link_regs(id)\
270 [id] = {\
271 LE_DCE110_REG_LIST(id)\
272 }
273
274 static const struct dce110_link_enc_registers link_enc_regs[] = {
275 link_regs(0),
276 link_regs(1),
277 link_regs(2),
278 link_regs(3),
279 link_regs(4),
280 link_regs(5),
281 link_regs(6),
282 };
283
284 #define stream_enc_regs(id)\
285 [id] = {\
286 SE_COMMON_REG_LIST(id),\
287 .TMDS_CNTL = 0,\
288 }
289
290 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
291 stream_enc_regs(0),
292 stream_enc_regs(1),
293 stream_enc_regs(2),
294 stream_enc_regs(3),
295 stream_enc_regs(4),
296 stream_enc_regs(5)
297 };
298
299 static const struct dce_stream_encoder_shift se_shift = {
300 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT)
301 };
302
303 static const struct dce_stream_encoder_mask se_mask = {
304 SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
305 };
306
307 #define opp_regs(id)\
308 [id] = {\
309 OPP_DCE_112_REG_LIST(id),\
310 }
311
312 static const struct dce_opp_registers opp_regs[] = {
313 opp_regs(0),
314 opp_regs(1),
315 opp_regs(2),
316 opp_regs(3),
317 opp_regs(4),
318 opp_regs(5)
319 };
320
321 static const struct dce_opp_shift opp_shift = {
322 OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
323 };
324
325 static const struct dce_opp_mask opp_mask = {
326 OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK)
327 };
328
329 #define aux_engine_regs(id)\
330 [id] = {\
331 AUX_COMMON_REG_LIST(id), \
332 .AUX_RESET_MASK = 0 \
333 }
334
335 static const struct dce110_aux_registers aux_engine_regs[] = {
336 aux_engine_regs(0),
337 aux_engine_regs(1),
338 aux_engine_regs(2),
339 aux_engine_regs(3),
340 aux_engine_regs(4),
341 aux_engine_regs(5)
342 };
343
344 #define audio_regs(id)\
345 [id] = {\
346 AUD_COMMON_REG_LIST(id)\
347 }
348
349 static const struct dce_audio_registers audio_regs[] = {
350 audio_regs(0),
351 audio_regs(1),
352 audio_regs(2),
353 audio_regs(3),
354 audio_regs(4),
355 audio_regs(5)
356 };
357
358 static const struct dce_audio_shift audio_shift = {
359 AUD_COMMON_MASK_SH_LIST(__SHIFT)
360 };
361
362 static const struct dce_audio_mask audio_mask = {
363 AUD_COMMON_MASK_SH_LIST(_MASK)
364 };
365
366 #define clk_src_regs(index, id)\
367 [index] = {\
368 CS_COMMON_REG_LIST_DCE_112(id),\
369 }
370
371 static const struct dce110_clk_src_regs clk_src_regs[] = {
372 clk_src_regs(0, A),
373 clk_src_regs(1, B),
374 clk_src_regs(2, C),
375 clk_src_regs(3, D),
376 clk_src_regs(4, E),
377 clk_src_regs(5, F)
378 };
379
380 static const struct dce110_clk_src_shift cs_shift = {
381 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
382 };
383
384 static const struct dce110_clk_src_mask cs_mask = {
385 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
386 };
387
388 static const struct bios_registers bios_regs = {
389 .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0,
390 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
391 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
392 };
393
394 static const struct resource_caps polaris_10_resource_cap = {
395 .num_timing_generator = 6,
396 .num_audio = 6,
397 .num_stream_encoder = 6,
398 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
399 .num_ddc = 6,
400 };
401
402 static const struct resource_caps polaris_11_resource_cap = {
403 .num_timing_generator = 5,
404 .num_audio = 5,
405 .num_stream_encoder = 5,
406 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
407 .num_ddc = 5,
408 };
409
410 static const struct dc_plane_cap plane_cap = {
411 .type = DC_PLANE_TYPE_DCE_RGB,
412
413 .pixel_format_support = {
414 .argb8888 = true,
415 .nv12 = false,
416 .fp16 = true
417 },
418
419 .max_upscale_factor = {
420 .argb8888 = 16000,
421 .nv12 = 1,
422 .fp16 = 1
423 },
424
425 .max_downscale_factor = {
426 .argb8888 = 250,
427 .nv12 = 1,
428 .fp16 = 1
429 },
430 64,
431 64
432 };
433
434 static const struct dc_debug_options debug_defaults = { 0 };
435
436 static const struct dc_check_config config_defaults = {
437 .enable_legacy_fast_update = true,
438 };
439
440 #define CTX ctx
441 #define REG(reg) mm ## reg
442
443 #ifndef mmCC_DC_HDMI_STRAPS
444 #define mmCC_DC_HDMI_STRAPS 0x4819
445 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
446 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
447 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
448 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
449 #endif
450
map_transmitter_id_to_phy_instance(enum transmitter transmitter)451 static int map_transmitter_id_to_phy_instance(
452 enum transmitter transmitter)
453 {
454 switch (transmitter) {
455 case TRANSMITTER_UNIPHY_A:
456 return 0;
457 case TRANSMITTER_UNIPHY_B:
458 return 1;
459 case TRANSMITTER_UNIPHY_C:
460 return 2;
461 case TRANSMITTER_UNIPHY_D:
462 return 3;
463 case TRANSMITTER_UNIPHY_E:
464 return 4;
465 case TRANSMITTER_UNIPHY_F:
466 return 5;
467 case TRANSMITTER_UNIPHY_G:
468 return 6;
469 default:
470 ASSERT(0);
471 return 0;
472 }
473 }
474
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)475 static void read_dce_straps(
476 struct dc_context *ctx,
477 struct resource_straps *straps)
478 {
479 REG_GET_2(CC_DC_HDMI_STRAPS,
480 HDMI_DISABLE, &straps->hdmi_disable,
481 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
482
483 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
484 }
485
create_audio(struct dc_context * ctx,unsigned int inst)486 static struct audio *create_audio(
487 struct dc_context *ctx, unsigned int inst)
488 {
489 return dce_audio_create(ctx, inst,
490 &audio_regs[inst], &audio_shift, &audio_mask);
491 }
492
493
dce112_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)494 static struct timing_generator *dce112_timing_generator_create(
495 struct dc_context *ctx,
496 uint32_t instance,
497 const struct dce110_timing_generator_offsets *offsets)
498 {
499 struct dce110_timing_generator *tg110 =
500 kzalloc_obj(struct dce110_timing_generator);
501
502 if (!tg110)
503 return NULL;
504
505 dce110_timing_generator_construct(tg110, ctx, instance, offsets);
506 return &tg110->base;
507 }
508
dce112_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)509 static struct stream_encoder *dce112_stream_encoder_create(
510 enum engine_id eng_id,
511 struct dc_context *ctx)
512 {
513 struct dce110_stream_encoder *enc110 =
514 kzalloc_obj(struct dce110_stream_encoder);
515
516 if (!enc110)
517 return NULL;
518
519 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
520 &stream_enc_regs[eng_id],
521 &se_shift, &se_mask);
522 return &enc110->base;
523 }
524
525 #define SRII(reg_name, block, id)\
526 .reg_name[id] = mm ## block ## id ## _ ## reg_name
527
528 static const struct dce_hwseq_registers hwseq_reg = {
529 HWSEQ_DCE112_REG_LIST()
530 };
531
532 static const struct dce_hwseq_shift hwseq_shift = {
533 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT)
534 };
535
536 static const struct dce_hwseq_mask hwseq_mask = {
537 HWSEQ_DCE112_MASK_SH_LIST(_MASK)
538 };
539
dce112_hwseq_create(struct dc_context * ctx)540 static struct dce_hwseq *dce112_hwseq_create(
541 struct dc_context *ctx)
542 {
543 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
544
545 if (hws) {
546 hws->ctx = ctx;
547 hws->regs = &hwseq_reg;
548 hws->shifts = &hwseq_shift;
549 hws->masks = &hwseq_mask;
550 }
551 return hws;
552 }
553
554 static const struct resource_create_funcs res_create_funcs = {
555 .read_dce_straps = read_dce_straps,
556 .create_audio = create_audio,
557 .create_stream_encoder = dce112_stream_encoder_create,
558 .create_hwseq = dce112_hwseq_create,
559 };
560
561 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) }
562 static const struct dce_mem_input_registers mi_regs[] = {
563 mi_inst_regs(0),
564 mi_inst_regs(1),
565 mi_inst_regs(2),
566 mi_inst_regs(3),
567 mi_inst_regs(4),
568 mi_inst_regs(5),
569 };
570
571 static const struct dce_mem_input_shift mi_shifts = {
572 MI_DCE11_2_MASK_SH_LIST(__SHIFT)
573 };
574
575 static const struct dce_mem_input_mask mi_masks = {
576 MI_DCE11_2_MASK_SH_LIST(_MASK)
577 };
578
dce112_mem_input_create(struct dc_context * ctx,uint32_t inst)579 static struct mem_input *dce112_mem_input_create(
580 struct dc_context *ctx,
581 uint32_t inst)
582 {
583 struct dce_mem_input *dce_mi = kzalloc_obj(struct dce_mem_input);
584
585 if (!dce_mi) {
586 BREAK_TO_DEBUGGER();
587 return NULL;
588 }
589
590 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
591 return &dce_mi->base;
592 }
593
dce112_transform_destroy(struct transform ** xfm)594 static void dce112_transform_destroy(struct transform **xfm)
595 {
596 kfree(TO_DCE_TRANSFORM(*xfm));
597 *xfm = NULL;
598 }
599
dce112_transform_create(struct dc_context * ctx,uint32_t inst)600 static struct transform *dce112_transform_create(
601 struct dc_context *ctx,
602 uint32_t inst)
603 {
604 struct dce_transform *transform =
605 kzalloc_obj(struct dce_transform);
606
607 if (!transform)
608 return NULL;
609
610 dce_transform_construct(transform, ctx, inst,
611 &xfm_regs[inst], &xfm_shift, &xfm_mask);
612 transform->lb_memory_size = 0x1404; /*5124*/
613 return &transform->base;
614 }
615
616 static const struct encoder_feature_support link_enc_feature = {
617 .max_hdmi_deep_color = COLOR_DEPTH_121212,
618 .max_hdmi_pixel_clock = 600000,
619 .hdmi_ycbcr420_supported = true,
620 .dp_ycbcr420_supported = false,
621 .flags.bits.IS_HBR2_CAPABLE = true,
622 .flags.bits.IS_HBR3_CAPABLE = true,
623 .flags.bits.IS_TPS3_CAPABLE = true,
624 .flags.bits.IS_TPS4_CAPABLE = true
625 };
626
dce112_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)627 static struct link_encoder *dce112_link_encoder_create(
628 struct dc_context *ctx,
629 const struct encoder_init_data *enc_init_data)
630 {
631 struct dce110_link_encoder *enc110 =
632 kzalloc_obj(struct dce110_link_encoder);
633 int link_regs_id;
634
635 if (!enc110)
636 return NULL;
637
638 link_regs_id =
639 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
640
641 dce110_link_encoder_construct(enc110,
642 enc_init_data,
643 &link_enc_feature,
644 &link_enc_regs[link_regs_id],
645 &link_enc_aux_regs[enc_init_data->channel - 1],
646 enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ?
647 NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]);
648 return &enc110->base;
649 }
650
dce112_panel_cntl_create(const struct panel_cntl_init_data * init_data)651 static struct panel_cntl *dce112_panel_cntl_create(const struct panel_cntl_init_data *init_data)
652 {
653 struct dce_panel_cntl *panel_cntl =
654 kzalloc_obj(struct dce_panel_cntl);
655
656 if (!panel_cntl)
657 return NULL;
658
659 dce_panel_cntl_construct(panel_cntl,
660 init_data,
661 &panel_cntl_regs[init_data->inst],
662 &panel_cntl_shift,
663 &panel_cntl_mask);
664
665 return &panel_cntl->base;
666 }
667
dce112_ipp_create(struct dc_context * ctx,uint32_t inst)668 static struct input_pixel_processor *dce112_ipp_create(
669 struct dc_context *ctx, uint32_t inst)
670 {
671 struct dce_ipp *ipp = kzalloc_obj(struct dce_ipp);
672
673 if (!ipp) {
674 BREAK_TO_DEBUGGER();
675 return NULL;
676 }
677
678 dce_ipp_construct(ipp, ctx, inst,
679 &ipp_regs[inst], &ipp_shift, &ipp_mask);
680 return &ipp->base;
681 }
682
dce112_opp_create(struct dc_context * ctx,uint32_t inst)683 static struct output_pixel_processor *dce112_opp_create(
684 struct dc_context *ctx,
685 uint32_t inst)
686 {
687 struct dce110_opp *opp =
688 kzalloc_obj(struct dce110_opp);
689
690 if (!opp)
691 return NULL;
692
693 dce110_opp_construct(opp,
694 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
695 return &opp->base;
696 }
697
dce112_aux_engine_create(struct dc_context * ctx,uint32_t inst)698 static struct dce_aux *dce112_aux_engine_create(
699 struct dc_context *ctx,
700 uint32_t inst)
701 {
702 struct aux_engine_dce110 *aux_engine =
703 kzalloc_obj(struct aux_engine_dce110);
704
705 if (!aux_engine)
706 return NULL;
707
708 dce110_aux_engine_construct(aux_engine, ctx, inst,
709 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
710 &aux_engine_regs[inst],
711 &aux_mask,
712 &aux_shift,
713 ctx->dc->caps.extended_aux_timeout_support);
714
715 return &aux_engine->base;
716 }
717 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
718
719 static const struct dce_i2c_registers i2c_hw_regs[] = {
720 i2c_inst_regs(1),
721 i2c_inst_regs(2),
722 i2c_inst_regs(3),
723 i2c_inst_regs(4),
724 i2c_inst_regs(5),
725 i2c_inst_regs(6),
726 };
727
728 static const struct dce_i2c_shift i2c_shifts = {
729 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
730 };
731
732 static const struct dce_i2c_mask i2c_masks = {
733 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
734 };
735
dce112_i2c_hw_create(struct dc_context * ctx,uint32_t inst)736 static struct dce_i2c_hw *dce112_i2c_hw_create(
737 struct dc_context *ctx,
738 uint32_t inst)
739 {
740 struct dce_i2c_hw *dce_i2c_hw =
741 kzalloc_obj(struct dce_i2c_hw);
742
743 if (!dce_i2c_hw)
744 return NULL;
745
746 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
747 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
748
749 return dce_i2c_hw;
750 }
dce112_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)751 static struct clock_source *dce112_clock_source_create(
752 struct dc_context *ctx,
753 struct dc_bios *bios,
754 enum clock_source_id id,
755 const struct dce110_clk_src_regs *regs,
756 bool dp_clk_src)
757 {
758 struct dce110_clk_src *clk_src =
759 kzalloc_obj(struct dce110_clk_src);
760
761 if (!clk_src)
762 return NULL;
763
764 if (dce112_clk_src_construct(clk_src, ctx, bios, id,
765 regs, &cs_shift, &cs_mask)) {
766 clk_src->base.dp_clk_src = dp_clk_src;
767 return &clk_src->base;
768 }
769
770 kfree(clk_src);
771 BREAK_TO_DEBUGGER();
772 return NULL;
773 }
774
dce112_clock_source_destroy(struct clock_source ** clk_src)775 static void dce112_clock_source_destroy(struct clock_source **clk_src)
776 {
777 kfree(TO_DCE110_CLK_SRC(*clk_src));
778 *clk_src = NULL;
779 }
780
dce112_resource_destruct(struct dce110_resource_pool * pool)781 static void dce112_resource_destruct(struct dce110_resource_pool *pool)
782 {
783 unsigned int i;
784
785 for (i = 0; i < pool->base.pipe_count; i++) {
786 if (pool->base.opps[i] != NULL)
787 dce110_opp_destroy(&pool->base.opps[i]);
788
789 if (pool->base.transforms[i] != NULL)
790 dce112_transform_destroy(&pool->base.transforms[i]);
791
792 if (pool->base.ipps[i] != NULL)
793 dce_ipp_destroy(&pool->base.ipps[i]);
794
795 if (pool->base.mis[i] != NULL) {
796 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
797 pool->base.mis[i] = NULL;
798 }
799
800 if (pool->base.timing_generators[i] != NULL) {
801 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
802 pool->base.timing_generators[i] = NULL;
803 }
804 }
805
806 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
807 if (pool->base.engines[i] != NULL)
808 dce110_engine_destroy(&pool->base.engines[i]);
809 if (pool->base.hw_i2cs[i] != NULL) {
810 kfree(pool->base.hw_i2cs[i]);
811 pool->base.hw_i2cs[i] = NULL;
812 }
813 if (pool->base.sw_i2cs[i] != NULL) {
814 kfree(pool->base.sw_i2cs[i]);
815 pool->base.sw_i2cs[i] = NULL;
816 }
817 }
818
819 for (i = 0; i < pool->base.stream_enc_count; i++) {
820 if (pool->base.stream_enc[i] != NULL)
821 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
822 }
823
824 for (i = 0; i < pool->base.clk_src_count; i++) {
825 if (pool->base.clock_sources[i] != NULL) {
826 dce112_clock_source_destroy(&pool->base.clock_sources[i]);
827 }
828 }
829
830 if (pool->base.dp_clock_source != NULL)
831 dce112_clock_source_destroy(&pool->base.dp_clock_source);
832
833 for (i = 0; i < pool->base.audio_count; i++) {
834 if (pool->base.audios[i] != NULL) {
835 dce_aud_destroy(&pool->base.audios[i]);
836 }
837 }
838
839 if (pool->base.abm != NULL)
840 dce_abm_destroy(&pool->base.abm);
841
842 if (pool->base.dmcu != NULL)
843 dce_dmcu_destroy(&pool->base.dmcu);
844
845 if (pool->base.irqs != NULL) {
846 dal_irq_service_destroy(&pool->base.irqs);
847 }
848 }
849
find_matching_pll(struct resource_context * res_ctx,const struct resource_pool * pool,const struct dc_stream_state * const stream)850 static struct clock_source *find_matching_pll(
851 struct resource_context *res_ctx,
852 const struct resource_pool *pool,
853 const struct dc_stream_state *const stream)
854 {
855 switch (stream->link->link_enc->transmitter) {
856 case TRANSMITTER_UNIPHY_A:
857 return pool->clock_sources[DCE112_CLK_SRC_PLL0];
858 case TRANSMITTER_UNIPHY_B:
859 return pool->clock_sources[DCE112_CLK_SRC_PLL1];
860 case TRANSMITTER_UNIPHY_C:
861 return pool->clock_sources[DCE112_CLK_SRC_PLL2];
862 case TRANSMITTER_UNIPHY_D:
863 return pool->clock_sources[DCE112_CLK_SRC_PLL3];
864 case TRANSMITTER_UNIPHY_E:
865 return pool->clock_sources[DCE112_CLK_SRC_PLL4];
866 case TRANSMITTER_UNIPHY_F:
867 return pool->clock_sources[DCE112_CLK_SRC_PLL5];
868 default:
869 return NULL;
870 }
871 }
872
build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)873 static enum dc_status build_mapped_resource(
874 const struct dc *dc,
875 struct dc_state *context,
876 struct dc_stream_state *stream)
877 {
878 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
879
880 if (!pipe_ctx)
881 return DC_ERROR_UNEXPECTED;
882
883 dce110_resource_build_pipe_hw_param(pipe_ctx);
884
885 resource_build_info_frame(pipe_ctx);
886
887 return DC_OK;
888 }
889
dce112_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)890 enum dc_status dce112_validate_bandwidth(
891 struct dc *dc,
892 struct dc_state *context,
893 enum dc_validate_mode validate_mode)
894 {
895 bool result = false;
896
897 DC_LOG_BANDWIDTH_CALCS(
898 "%s: start",
899 __func__);
900
901 if (bw_calcs(
902 dc->ctx,
903 dc->bw_dceip,
904 dc->bw_vbios,
905 context->res_ctx.pipe_ctx,
906 dc->res_pool->pipe_count,
907 &context->bw_ctx.bw.dce))
908 result = true;
909
910 if (!result)
911 DC_LOG_BANDWIDTH_VALIDATION(
912 "%s: Bandwidth validation failed!",
913 __func__);
914
915 if (memcmp(&dc->current_state->bw_ctx.bw.dce,
916 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
917
918 DC_LOG_BANDWIDTH_CALCS(
919 "%s: finish,\n"
920 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
921 "stutMark_b: %d stutMark_a: %d\n"
922 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
923 "stutMark_b: %d stutMark_a: %d\n"
924 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
925 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
926 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
927 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
928 ,
929 __func__,
930 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
931 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
932 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
933 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
934 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
935 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,
936 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,
937 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,
938 context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,
939 context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,
940 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,
941 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,
942 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,
943 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,
944 context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,
945 context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,
946 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,
947 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,
948 context->bw_ctx.bw.dce.stutter_mode_enable,
949 context->bw_ctx.bw.dce.cpuc_state_change_enable,
950 context->bw_ctx.bw.dce.cpup_state_change_enable,
951 context->bw_ctx.bw.dce.nbp_state_change_enable,
952 context->bw_ctx.bw.dce.all_displays_in_sync,
953 context->bw_ctx.bw.dce.dispclk_khz,
954 context->bw_ctx.bw.dce.sclk_khz,
955 context->bw_ctx.bw.dce.sclk_deep_sleep_khz,
956 context->bw_ctx.bw.dce.yclk_khz,
957 context->bw_ctx.bw.dce.blackout_recovery_time_us);
958 }
959 return result ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
960 }
961
resource_map_phy_clock_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)962 enum dc_status resource_map_phy_clock_resources(
963 const struct dc *dc,
964 struct dc_state *context,
965 struct dc_stream_state *stream)
966 {
967
968 /* acquire new resources */
969 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(
970 &context->res_ctx, stream);
971
972 if (!pipe_ctx)
973 return DC_ERROR_UNEXPECTED;
974
975 if (dc_is_dp_signal(pipe_ctx->stream->signal)
976 || dc_is_virtual_signal(pipe_ctx->stream->signal))
977 pipe_ctx->clock_source =
978 dc->res_pool->dp_clock_source;
979 else {
980 if (stream && stream->link && stream->link->link_enc)
981 pipe_ctx->clock_source = find_matching_pll(
982 &context->res_ctx, dc->res_pool,
983 stream);
984 }
985
986 if (pipe_ctx->clock_source == NULL)
987 return DC_NO_CLOCK_SOURCE_RESOURCE;
988
989 resource_reference_clock_source(
990 &context->res_ctx,
991 dc->res_pool,
992 pipe_ctx->clock_source);
993
994 return DC_OK;
995 }
996
dce112_validate_surface_sets(struct dc_state * context)997 static bool dce112_validate_surface_sets(
998 struct dc_state *context)
999 {
1000 int i;
1001
1002 for (i = 0; i < context->stream_count; i++) {
1003 if (context->stream_status[i].plane_count == 0)
1004 continue;
1005
1006 if (context->stream_status[i].plane_count > 1)
1007 return false;
1008
1009 if (context->stream_status[i].plane_states[0]->format
1010 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
1011 return false;
1012 }
1013
1014 return true;
1015 }
1016
dce112_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1017 enum dc_status dce112_add_stream_to_ctx(
1018 struct dc *dc,
1019 struct dc_state *new_ctx,
1020 struct dc_stream_state *dc_stream)
1021 {
1022 enum dc_status result;
1023
1024 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1025
1026 if (result == DC_OK)
1027 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1028
1029
1030 if (result == DC_OK)
1031 result = build_mapped_resource(dc, new_ctx, dc_stream);
1032
1033 return result;
1034 }
1035
dce112_validate_global(struct dc * dc,struct dc_state * context)1036 static enum dc_status dce112_validate_global(
1037 struct dc *dc,
1038 struct dc_state *context)
1039 {
1040 if (!dce112_validate_surface_sets(context))
1041 return DC_FAIL_SURFACE_VALIDATE;
1042
1043 return DC_OK;
1044 }
1045
dce112_destroy_resource_pool(struct resource_pool ** pool)1046 static void dce112_destroy_resource_pool(struct resource_pool **pool)
1047 {
1048 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1049
1050 dce112_resource_destruct(dce110_pool);
1051 kfree(dce110_pool);
1052 *pool = NULL;
1053 }
1054
1055 static const struct resource_funcs dce112_res_pool_funcs = {
1056 .destroy = dce112_destroy_resource_pool,
1057 .link_enc_create = dce112_link_encoder_create,
1058 .panel_cntl_create = dce112_panel_cntl_create,
1059 .validate_bandwidth = dce112_validate_bandwidth,
1060 .validate_plane = dce100_validate_plane,
1061 .add_stream_to_ctx = dce112_add_stream_to_ctx,
1062 .validate_global = dce112_validate_global,
1063 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
1064 };
1065
bw_calcs_data_update_from_pplib(struct dc * dc)1066 static void bw_calcs_data_update_from_pplib(struct dc *dc)
1067 {
1068 struct dm_pp_clock_levels_with_latency eng_clks = {0};
1069 struct dm_pp_clock_levels_with_latency mem_clks = {0};
1070 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
1071 struct dm_pp_clock_levels clks = {0};
1072 int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
1073
1074 if (!dc->bw_vbios)
1075 return;
1076
1077 if (dc->bw_vbios->memory_type == bw_def_hbm)
1078 memory_type_multiplier = MEMORY_TYPE_HBM;
1079
1080 /*do system clock TODO PPLIB: after PPLIB implement,
1081 * then remove old way
1082 */
1083 if (!dm_pp_get_clock_levels_by_type_with_latency(
1084 dc->ctx,
1085 DM_PP_CLOCK_TYPE_ENGINE_CLK,
1086 &eng_clks)) {
1087
1088 /* This is only for temporary */
1089 dm_pp_get_clock_levels_by_type(
1090 dc->ctx,
1091 DM_PP_CLOCK_TYPE_ENGINE_CLK,
1092 &clks);
1093 /* convert all the clock fro kHz to fix point mHz */
1094 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1095 clks.clocks_in_khz[clks.num_levels-1], 1000);
1096 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
1097 clks.clocks_in_khz[clks.num_levels/8], 1000);
1098 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
1099 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1100 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
1101 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1102 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
1103 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1104 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
1105 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1106 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
1107 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1108 dc->bw_vbios->low_sclk = bw_frc_to_fixed(
1109 clks.clocks_in_khz[0], 1000);
1110
1111 /*do memory clock*/
1112 dm_pp_get_clock_levels_by_type(
1113 dc->ctx,
1114 DM_PP_CLOCK_TYPE_MEMORY_CLK,
1115 &clks);
1116
1117 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1118 (int64_t)clks.clocks_in_khz[0] * memory_type_multiplier, 1000);
1119 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1120 (int64_t)clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier,
1121 1000);
1122 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1123 (int64_t)clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier,
1124 1000);
1125
1126 return;
1127 }
1128
1129 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */
1130 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1131 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
1132 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
1133 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
1134 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
1135 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
1136 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
1137 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
1138 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
1139 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
1140 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
1141 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
1142 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
1143 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
1144 dc->bw_vbios->low_sclk = bw_frc_to_fixed(
1145 eng_clks.data[0].clocks_in_khz, 1000);
1146
1147 /*do memory clock*/
1148 dm_pp_get_clock_levels_by_type_with_latency(
1149 dc->ctx,
1150 DM_PP_CLOCK_TYPE_MEMORY_CLK,
1151 &mem_clks);
1152
1153 /* we don't need to call PPLIB for validation clock since they
1154 * also give us the highest sclk and highest mclk (UMA clock).
1155 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula):
1156 * YCLK = UMACLK*m_memoryTypeMultiplier
1157 */
1158 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1159 (int64_t)mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
1160 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1161 (int64_t)mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
1162 1000);
1163 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1164 (int64_t)mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
1165 1000);
1166
1167 /* Now notify PPLib/SMU about which Watermarks sets they should select
1168 * depending on DPM state they are in. And update BW MGR GFX Engine and
1169 * Memory clock member variables for Watermarks calculations for each
1170 * Watermark Set
1171 */
1172 clk_ranges.num_wm_sets = 4;
1173 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1174 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1175 eng_clks.data[0].clocks_in_khz;
1176 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1177 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1178 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1179 mem_clks.data[0].clocks_in_khz;
1180 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1181 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1182
1183 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1184 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1185 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1186 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1187 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1188 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1189 mem_clks.data[0].clocks_in_khz;
1190 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1191 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1192
1193 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1194 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1195 eng_clks.data[0].clocks_in_khz;
1196 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1197 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1198 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1199 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1200 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1201 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1202
1203 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1204 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1205 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1206 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1207 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1208 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1209 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1210 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1211 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1212
1213 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1214 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1215 }
1216
dce112_resource_cap(struct hw_asic_id * asic_id)1217 static const struct resource_caps *dce112_resource_cap(
1218 struct hw_asic_id *asic_id)
1219 {
1220 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||
1221 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev))
1222 return &polaris_11_resource_cap;
1223 else
1224 return &polaris_10_resource_cap;
1225 }
1226
dce112_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1227 static bool dce112_resource_construct(
1228 uint8_t num_virtual_links,
1229 struct dc *dc,
1230 struct dce110_resource_pool *pool)
1231 {
1232 unsigned int i;
1233 struct dc_context *ctx = dc->ctx;
1234
1235 ctx->dc_bios->regs = &bios_regs;
1236
1237 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
1238 pool->base.funcs = &dce112_res_pool_funcs;
1239
1240 /*************************************************
1241 * Resource + asic cap harcoding *
1242 *************************************************/
1243 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1244 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1245 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1246 dc->caps.max_downscale_ratio = 200;
1247 dc->caps.i2c_speed_in_khz = 100;
1248 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1249 dc->caps.max_cursor_size = 128;
1250 dc->caps.min_horizontal_blanking_period = 80;
1251 dc->caps.dual_link_dvi = true;
1252 dc->caps.extended_aux_timeout_support = false;
1253 dc->debug = debug_defaults;
1254 dc->check_config = config_defaults;
1255
1256 /*************************************************
1257 * Create resources *
1258 *************************************************/
1259
1260 pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
1261 dce112_clock_source_create(
1262 ctx, ctx->dc_bios,
1263 CLOCK_SOURCE_COMBO_PHY_PLL0,
1264 &clk_src_regs[0], false);
1265 pool->base.clock_sources[DCE112_CLK_SRC_PLL1] =
1266 dce112_clock_source_create(
1267 ctx, ctx->dc_bios,
1268 CLOCK_SOURCE_COMBO_PHY_PLL1,
1269 &clk_src_regs[1], false);
1270 pool->base.clock_sources[DCE112_CLK_SRC_PLL2] =
1271 dce112_clock_source_create(
1272 ctx, ctx->dc_bios,
1273 CLOCK_SOURCE_COMBO_PHY_PLL2,
1274 &clk_src_regs[2], false);
1275 pool->base.clock_sources[DCE112_CLK_SRC_PLL3] =
1276 dce112_clock_source_create(
1277 ctx, ctx->dc_bios,
1278 CLOCK_SOURCE_COMBO_PHY_PLL3,
1279 &clk_src_regs[3], false);
1280 pool->base.clock_sources[DCE112_CLK_SRC_PLL4] =
1281 dce112_clock_source_create(
1282 ctx, ctx->dc_bios,
1283 CLOCK_SOURCE_COMBO_PHY_PLL4,
1284 &clk_src_regs[4], false);
1285 pool->base.clock_sources[DCE112_CLK_SRC_PLL5] =
1286 dce112_clock_source_create(
1287 ctx, ctx->dc_bios,
1288 CLOCK_SOURCE_COMBO_PHY_PLL5,
1289 &clk_src_regs[5], false);
1290 pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;
1291
1292 pool->base.dp_clock_source = dce112_clock_source_create(
1293 ctx, ctx->dc_bios,
1294 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);
1295
1296
1297 for (i = 0; i < pool->base.clk_src_count; i++) {
1298 if (pool->base.clock_sources[i] == NULL) {
1299 dm_error("DC: failed to create clock sources!\n");
1300 BREAK_TO_DEBUGGER();
1301 goto res_create_fail;
1302 }
1303 }
1304
1305 pool->base.dmcu = dce_dmcu_create(ctx,
1306 &dmcu_regs,
1307 &dmcu_shift,
1308 &dmcu_mask);
1309 if (pool->base.dmcu == NULL) {
1310 dm_error("DC: failed to create dmcu!\n");
1311 BREAK_TO_DEBUGGER();
1312 goto res_create_fail;
1313 }
1314
1315 pool->base.abm = dce_abm_create(ctx,
1316 &abm_regs,
1317 &abm_shift,
1318 &abm_mask);
1319 if (pool->base.abm == NULL) {
1320 dm_error("DC: failed to create abm!\n");
1321 BREAK_TO_DEBUGGER();
1322 goto res_create_fail;
1323 }
1324
1325 {
1326 struct irq_service_init_data init_data;
1327 init_data.ctx = dc->ctx;
1328 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1329 if (!pool->base.irqs)
1330 goto res_create_fail;
1331 }
1332
1333 for (i = 0; i < pool->base.pipe_count; i++) {
1334 pool->base.timing_generators[i] =
1335 dce112_timing_generator_create(
1336 ctx,
1337 i,
1338 &dce112_tg_offsets[i]);
1339 if (pool->base.timing_generators[i] == NULL) {
1340 BREAK_TO_DEBUGGER();
1341 dm_error("DC: failed to create tg!\n");
1342 goto res_create_fail;
1343 }
1344
1345 pool->base.mis[i] = dce112_mem_input_create(ctx, i);
1346 if (pool->base.mis[i] == NULL) {
1347 BREAK_TO_DEBUGGER();
1348 dm_error(
1349 "DC: failed to create memory input!\n");
1350 goto res_create_fail;
1351 }
1352
1353 pool->base.ipps[i] = dce112_ipp_create(ctx, i);
1354 if (pool->base.ipps[i] == NULL) {
1355 BREAK_TO_DEBUGGER();
1356 dm_error(
1357 "DC:failed to create input pixel processor!\n");
1358 goto res_create_fail;
1359 }
1360
1361 pool->base.transforms[i] = dce112_transform_create(ctx, i);
1362 if (pool->base.transforms[i] == NULL) {
1363 BREAK_TO_DEBUGGER();
1364 dm_error(
1365 "DC: failed to create transform!\n");
1366 goto res_create_fail;
1367 }
1368
1369 pool->base.opps[i] = dce112_opp_create(
1370 ctx,
1371 i);
1372 if (pool->base.opps[i] == NULL) {
1373 BREAK_TO_DEBUGGER();
1374 dm_error(
1375 "DC:failed to create output pixel processor!\n");
1376 goto res_create_fail;
1377 }
1378 }
1379
1380 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1381 pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
1382 if (pool->base.engines[i] == NULL) {
1383 BREAK_TO_DEBUGGER();
1384 dm_error(
1385 "DC:failed to create aux engine!!\n");
1386 goto res_create_fail;
1387 }
1388 pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i);
1389 if (pool->base.hw_i2cs[i] == NULL) {
1390 BREAK_TO_DEBUGGER();
1391 dm_error(
1392 "DC:failed to create i2c engine!!\n");
1393 goto res_create_fail;
1394 }
1395 pool->base.sw_i2cs[i] = NULL;
1396 }
1397
1398 if (!resource_construct(num_virtual_links, dc, &pool->base,
1399 &res_create_funcs))
1400 goto res_create_fail;
1401
1402 dc->caps.max_planes = pool->base.pipe_count;
1403
1404 for (i = 0; i < dc->caps.max_planes; ++i)
1405 dc->caps.planes[i] = plane_cap;
1406
1407 /* Create hardware sequencer */
1408 dce112_hw_sequencer_construct(dc);
1409
1410 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1411
1412 bw_calcs_data_update_from_pplib(dc);
1413
1414 return true;
1415
1416 res_create_fail:
1417 dce112_resource_destruct(pool);
1418 return false;
1419 }
1420
dce112_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1421 struct resource_pool *dce112_create_resource_pool(
1422 uint8_t num_virtual_links,
1423 struct dc *dc)
1424 {
1425 struct dce110_resource_pool *pool =
1426 kzalloc_obj(struct dce110_resource_pool);
1427
1428 if (!pool)
1429 return NULL;
1430
1431 if (dce112_resource_construct(num_virtual_links, dc, pool))
1432 return &pool->base;
1433
1434 kfree(pool);
1435 BREAK_TO_DEBUGGER();
1436 return NULL;
1437 }
1438