| /linux/Documentation/ABI/testing/ |
| H A D | debugfs-driver-dcc | 1 What: /sys/kernel/debug/dcc/.../ready
5 This file is used to check the status of the dcc
7 A 'Y' here indicates dcc is ready.
9 What: /sys/kernel/debug/dcc/.../trigger
17 What: /sys/kernel/debug/dcc/.../config_reset
22 a dcc driver to the default configuration. When '1'
27 What: /sys/kernel/debug/dcc/.../[list-number]/config
34 can be one of following dcc instructions: read,
45 echo R <addr> <n> <bus> >/sys/kernel/debug/dcc/../[list-number]/config
65 echo W <addr> <n> <bus type> > /sys/kernel/debug/dcc/../[list-number]/config
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/ |
| H A D | dcn201_hubp.c | 48 struct dc_plane_dcc_param *dcc, in hubp201_program_surface_config() argument
52 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp201_program_surface_config()
54 hubp1_program_size(hubp, format, plane_size, dcc); in hubp201_program_surface_config()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_plane.c | 267 const struct dc_plane_dcc_param *dcc, in amdgpu_dm_plane_validate_dcc() argument
278 if (!dcc->enable) in amdgpu_dm_plane_validate_dcc()
304 if (dcc->independent_64b_blks == 0 && in amdgpu_dm_plane_validate_dcc()
317 struct dc_plane_dcc_param *dcc, in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers() argument
332 dcc->enable = 1; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
333 dcc->meta_pitch = afb->base.pitches[1]; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
334 dcc->independent_64b_blks = independent_64b_blks; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
337 dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
339 dcc->dcc_ind_blk = hubp_ind_block_128b; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
341 dcc->dcc_ind_blk = hubp_ind_block_64b; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
[all …]
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| H A D | amdgpu_dm_plane.h | 52 struct dc_plane_dcc_param *dcc,
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| /linux/drivers/bus/ |
| H A D | vexpress-config.c | 108 u32 *position, u32 *dcc) in vexpress_config_get_topo() argument
116 vexpress_config_find_prop(node, "arm,vexpress,dcc", dcc); in vexpress_config_get_topo()
257 u32 site, position, dcc; in vexpress_syscfg_regmap_init() local
261 &position, &dcc); in vexpress_syscfg_regmap_init()
301 func, site, position, dcc, in vexpress_syscfg_regmap_init()
304 func->template[i] = SYS_CFGCTRL_DCC(dcc); in vexpress_syscfg_regmap_init()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_translation_helper.c | 384 surface->dcc.enable = false; in populate_dml21_dummy_surface_cfg()
385 surface->dcc.informative.dcc_rate_plane0 = 1.0; in populate_dml21_dummy_surface_cfg()
386 surface->dcc.informative.dcc_rate_plane1 = 1.0; in populate_dml21_dummy_surface_cfg()
387 surface->dcc.informative.fraction_of_zero_size_request_plane0 = 0; in populate_dml21_dummy_surface_cfg()
388 surface->dcc.informative.fraction_of_zero_size_request_plane1 = 0; in populate_dml21_dummy_surface_cfg()
454 surface->dcc.enable = plane_state->dcc.enable; in populate_dml21_surface_config_from_plane_state()
455 surface->dcc.informative.dcc_rate_plane0 = 1.0; in populate_dml21_surface_config_from_plane_state()
456 surface->dcc.informative.dcc_rate_plane1 = 1.0; in populate_dml21_surface_config_from_plane_state()
457 …surface->dcc.informative.fraction_of_zero_size_request_plane0 = plane_state->dcc.independent_64b_b… in populate_dml21_surface_config_from_plane_state()
458 …surface->dcc.informative.fraction_of_zero_size_request_plane1 = plane_state->dcc.independent_64b_b… in populate_dml21_surface_config_from_plane_state()
[all …]
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| H A D | dml21_utils.c | 307 memcpy(&phantom_plane->dcc, &main_plane->dcc, sizeof(phantom_plane->dcc)); in dml21_add_phantom_plane()
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| /linux/arch/arm64/boot/dts/xilinx/ |
| H A D | zynqmp-zcu1275-revA.dts | 22 serial1 = &dcc;
37 &dcc {
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| H A D | zynqmp-zc1254-revA.dts | 22 serial1 = &dcc;
37 &dcc {
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| H A D | zynqmp-zc1232-revA.dts | 21 serial1 = &dcc;
36 &dcc {
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| /linux/arch/arm/boot/dts/arm/ |
| H A D | vexpress-v2p-ca5s.dts | 144 dcc {
202 temp-dcc {
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| H A D | vexpress-v2p-ca15-tc1.dts | 141 dcc {
217 temp-dcc {
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| H A D | vexpress-v2p-ca15_a7.dts | 252 dcc {
373 temp-dcc {
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| H A D | vexpress-v2p-ca9.dts | 186 dcc {
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| /linux/drivers/s390/cio/ |
| H A D | qdio_main.c | 726 int dstat, int dcc) in qdio_establish_handle_irq() argument
734 if (dcc == 1) in qdio_establish_handle_irq()
754 int cstat, dstat, rc, dcc; in qdio_int_handler() local
774 dcc = scsw_cmd_is_valid_cc(&irb->scsw) ? irb->scsw.cmd.cc : 0; in qdio_int_handler()
779 rc = qdio_establish_handle_irq(irq_ptr, cstat, dstat, dcc); in qdio_int_handler()
793 else if (dcc == 1) in qdio_int_handler()
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| /linux/drivers/tty/hvc/ |
| H A D | hvc_dcc.c | 63 EARLYCON_DECLARE(dcc, dcc_early_console_setup);
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| /linux/arch/arm64/boot/dts/arm/ |
| H A D | vexpress-v2f-1xv7-ca53x2.dts | 110 dcc {
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/ |
| H A D | dml_top_display_cfg_types.h | 209 } dcc; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 386 unsigned char dcc; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_translation_helper.c | 926 out->DCCEnable[location] = in->dcc.enable; in populate_dml_surface_cfg_from_plane_state()
927 out->DCCMetaPitchY[location] = in->dcc.meta_pitch; in populate_dml_surface_cfg_from_plane_state()
928 out->DCCMetaPitchC[location] = in->dcc.meta_pitch_c; in populate_dml_surface_cfg_from_plane_state()
931 out->DCCFractionOfZeroSizeRequestsLuma[location] = in->dcc.independent_64b_blks; in populate_dml_surface_cfg_from_plane_state()
932 out->DCCFractionOfZeroSizeRequestsChroma[location] = in->dcc.independent_64b_blks_c; in populate_dml_surface_cfg_from_plane_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 1385 pipes[pipe_cnt].pipe.src.dcc = false; in dcn20_populate_dml_pipes_from_context()
1641 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; in dcn20_populate_dml_pipes_from_context()
1642 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c; in dcn20_populate_dml_pipes_from_context()
1645 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; in dcn20_populate_dml_pipes_from_context()
1647 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable; in dcn20_populate_dml_pipes_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/ |
| H A D | dml2_top_soc15.c | 534 if (!params->display_cfg->plane_descriptors[plane_index].surface.dcc.enable) in dml2_top_mcache_validate_admissability()
746 if (!params->display_config->plane_descriptors[i].surface.dcc.enable) { in dml2_top_mcache_calc_mcache_count_and_offsets()
1036 if (params->mcache_configurations[config_index].plane_descriptor->surface.dcc.enable) { in dml2_top_soc15_build_mcache_programming()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 3947 && p->display_cfg->plane_descriptors[k].surface.dcc.enable in CalculateSwathAndDETConfiguration()
4782 if (display_cfg->plane_descriptors[k].surface.dcc.enable) in CalculateTarb()
7009 if (p->display_cfg->plane_descriptors[plane_index].surface.dcc.enable && p->mrq_present) { in calculate_bytes_to_fetch_required_to_hide_latency()
7477 myPipe->DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable; in dml_core_ms_prefetch_check()
7531 …CalculatePrefetchSchedule_params->dcc_enable = display_cfg->plane_descriptors[k].surface.dcc.enabl… in dml_core_ms_prefetch_check()
7830 mode_lib->ip.dcn_mrq_present && display_cfg->plane_descriptors[k].surface.dcc.enable, in dml_core_ms_prefetch_check()
8214 …lib->ms.BytePerPixelY[k] == 8 && display_cfg->plane_descriptors[k].surface.dcc.enable == true) { /… in dml_core_mode_support()
8302 if (mode_lib->ip.dcn_mrq_present && display_cfg->plane_descriptors[k].surface.dcc.enable) { in dml_core_mode_support()
8303 …k] = (unsigned int)math_ceil2(math_max2(display_cfg->plane_descriptors[k].surface.dcc.plane0.pitch, in dml_core_mode_support()
8306 …if (mode_lib->ms.support.AlignedDCCMetaPitchY[k] > display_cfg->plane_descriptors[k].surface.dcc.p… in dml_core_mode_support()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 597 if (!pipe_ctx->plane_state->dcc.enable) { in get_dcc_visual_confirm_color()
2044 struct dc_plane_dcc_param *dcc = params->program_surface_config_params.dcc; in hwss_program_surface_config() local
2054 dcc, in hwss_program_surface_config()
3920 struct dc_plane_dcc_param *dcc, in hwss_add_hubp_program_surface_config() argument
3931 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.dcc = dcc; in hwss_add_hubp_program_surface_config()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 1389 plane_state->dcc.enable = 1; in dcn21_patch_unknown_plane_state()
1391 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024; in dcn21_patch_unknown_plane_state()
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