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/linux/tools/perf/dlfilters/
H A Ddlfilter-show-cycles.c19 static __u64 cycles[MAX_CPU][MAX_ENTRY]; variable
30 __u64 cycles[MAX_ENTRY]; member
77 e->cycles[pos] += cnt; in add_entry()
92 cycles[cpu][pos] += sample->cyc_cnt; in filter_event_early()
98 static void print_vals(__u64 cycles, __u64 delta) in print_vals() argument
101 printf("%10llu %10llu ", (unsigned long long)cycles, (unsigned long long)delta); in print_vals()
103 printf("%10llu %10s ", (unsigned long long)cycles, ""); in print_vals()
115 print_vals(cycles[cpu][pos], cycles[cpu][pos] - cycles_rpt[cpu][pos]); in filter_event()
116 cycles_rpt[cpu][pos] = cycles[cpu][pos]; in filter_event()
124 print_vals(e->cycles[pos], e->cycles[pos] - e->cycles_rpt[pos]); in filter_event()
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/linux/drivers/gpu/drm/i915/gt/
H A Dselftest_gt_pm.c56 u32 cycles[5]; in measure_clocks() local
61 cycles[i] = -read_timestamp(engine); in measure_clocks()
66 cycles[i] += read_timestamp(engine); in measure_clocks()
72 sort(cycles, 5, sizeof(*cycles), cmp_u32, NULL); in measure_clocks()
73 *out_cycles = (cycles[1] + 2 * cycles[2] + cycles[3]) / 4; in measure_clocks()
99 u32 cycles; in live_gt_clocks() local
107 measure_clocks(engine, &cycles, &dt); in live_gt_clocks()
109 time = intel_gt_clock_interval_to_ns(engine->gt, cycles); in live_gt_clocks()
113 engine->name, cycles, time, dt, expected, in live_gt_clocks()
123 if (9 * expected < 8 * cycles || 8 * expected > 9 * cycles) { in live_gt_clocks()
H A Dselftest_engine_cs.c148 u32 cycles[COUNT]; in perf_mi_bb_start() local
170 for (i = 0; i < ARRAY_SIZE(cycles); i++) { in perf_mi_bb_start()
203 cycles[i] = rq->hwsp_seqno[3] - rq->hwsp_seqno[2]; in perf_mi_bb_start()
211 engine->name, trifilter(cycles)); in perf_mi_bb_start()
276 u32 cycles[COUNT]; in perf_mi_noop() local
314 for (i = 0; i < ARRAY_SIZE(cycles); i++) { in perf_mi_noop()
358 cycles[i] = in perf_mi_noop()
369 engine->name, trifilter(cycles)); in perf_mi_noop()
/linux/tools/perf/Documentation/
H A Dintel-hybrid.txt45 For example, count the 'cycles' event on core cpus.
47 perf stat -e cpu_core/cycles/
56 For hardware events, they have pre-defined configs (e.g. 0 for cycles).
84 perf stat -e cycles -a (use system-wide in this example), two events
115 The kernel creates 'cycles' (0x400000000) on cpu0-cpu15 (core cpus),
116 and create 'cycles' (0x800000000) on cpu16-cpu23 (atom cpus).
122 6,744,979 cpu_core/cycles/
123 1,965,552 cpu_atom/cycles/
125 The first 'cycles' is core event, the second 'cycles' i
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H A Dperf-daemon.txt32 …916507 916508 ... \_ perf record --control=fifo:control,ack -m 10M -e cycles --overwrite --switc…
120 [session-cycles]
121 run = -m 10M -e cycles --overwrite --switch-output -a
136 [603350:cycles] perf record -m 10M -e cycles --overwrite --switch-output -a
149 [603350:cycles] perf record -m 10M -e cycles --overwrite --switch-output -a
150 base: /opt/perfdata/session-cycles
151 output: /opt/perfdata/session-cycles/output
152 control: /opt/perfdata/session-cycles/control
153 ack: /opt/perfdata/session-cycles/ack
173 OK cycles
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H A Dperf.data-directory-format.txt51 Samples for 'cycles' event do not have CPU attribute set. Skipping 'cpu' field.
55 … perf 15316 2060795.480902: 1 cycles: ffffffffa2caa548 native_write_msr+0x8 (vmlinux)
56 … perf 15316 2060795.480906: 1 cycles: ffffffffa2caa548 native_write_msr+0x8 (vmlinux)
57 … perf 15316 2060795.480908: 7 cycles: ffffffffa2caa548 native_write_msr+0x8 (vmlinux)
58 … perf 15316 2060795.480910: 119 cycles: ffffffffa2caa54a native_write_msr+0xa (vmlinux)
59 …perf 15316 2060795.480912: 2109 cycles: ffffffffa2c9b7b0 native_apic_msr_write+0x0 (vmlinux)
60 …perf 15316 2060795.480914: 37606 cycles: ffffffffa2f121fe perf_event_addr_filters_exec+0x2e …
61 …uname 15316 2060795.480924: 588287 cycles: ffffffffa303a56d page_counter_try_charge+0x6d (vml…
62 … uname 15316 2060795.481067: 2261945 cycles: ffffffffa301438f kmem_cache_free+0x4f (vmlinux)
63 …uname 15316 2060795.481643: 2172167 cycles: 7f1a48c393c0 _IO_un_link+0x0 (/lib/x86_64-linu…
H A Dintel-acr.txt19 cpu_atom/cycles,period=100000,acr_mask=0x3/} -- true
22 200000, the second counter, "cycles", will be reset and a sample will be
23 taken. If "cycles" is exceeded first, both counters in the group will be
30 for the first event. "cycles" is assigned an acr_mask of 0x3, meaning
44 cpu_atom/cycles,period=100000,ratio-to-prev=0.5/} -- true
52 perf record -e {cpu_atom/cycles/, \
/linux/Documentation/devicetree/bindings/mtd/
H A Dfsmc-nand.txt15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
17 cycles.
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
21 Only valid for write transactions. Zero means zero cycles,
22 255 means 255 cycles.
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
25 one cycle, 255 means 256 cycles.
26 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
28 255 means 256 cycles.
29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
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/linux/drivers/net/ethernet/mellanox/mlx4/
H A Den_clock.c44 container_of(tc, struct mlx4_en_dev, cycles); in mlx4_en_read_clock()
139 mdev->cycles.mult = mult; in mlx4_en_phc_adjfine()
208 timecounter_init(&mdev->clock, &mdev->cycles, ns); in mlx4_en_phc_settime()
275 memset(&mdev->cycles, 0, sizeof(mdev->cycles)); in mlx4_en_init_timestamp()
276 mdev->cycles.read = mlx4_en_read_clock; in mlx4_en_init_timestamp()
277 mdev->cycles.mask = CLOCKSOURCE_MASK(48); in mlx4_en_init_timestamp()
278 mdev->cycles.shift = freq_to_shift(dev->caps.hca_core_clock); in mlx4_en_init_timestamp()
279 mdev->cycles.mult = in mlx4_en_init_timestamp()
280 clocksource_khz2mult(1000 * dev->caps.hca_core_clock, mdev->cycles.shift); in mlx4_en_init_timestamp()
281 mdev->nominal_c_mult = mdev->cycles.mult; in mlx4_en_init_timestamp()
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/linux/drivers/net/wireless/ath/
H A Dhw.c144 u32 cycles, busy, rx, tx; in ath_hw_cycle_counters_update() local
151 cycles = REG_READ(ah, AR_CCCNT); in ath_hw_cycle_counters_update()
166 common->cc_ani.cycles += cycles; in ath_hw_cycle_counters_update()
171 common->cc_survey.cycles += cycles; in ath_hw_cycle_counters_update()
183 listen_time = (cc->cycles - cc->rx_frame - cc->tx_frame) / in ath_hw_get_listen_time()
/linux/arch/arm64/lib/
H A Ddelay.c41 void __delay(unsigned long cycles) in __delay() argument
46 u64 end = start + cycles; in __delay()
53 while ((__delay_cycles() - start) < cycles) in __delay()
59 while ((__delay_cycles() - start + timer_evt_period) < cycles) in __delay()
63 while ((__delay_cycles() - start) < cycles) in __delay()
/linux/drivers/pwm/
H A Dpwm-berlin.c80 u64 cycles; in berlin_pwm_config() local
82 cycles = clk_get_rate(bpc->clk); in berlin_pwm_config()
83 cycles *= period_ns; in berlin_pwm_config()
84 do_div(cycles, NSEC_PER_SEC); in berlin_pwm_config()
86 if (cycles > BERLIN_PWM_MAX_TCNT) { in berlin_pwm_config()
88 cycles >>= 12; // Prescaled by 4096 in berlin_pwm_config()
90 if (cycles > BERLIN_PWM_MAX_TCNT) in berlin_pwm_config()
94 period = cycles; in berlin_pwm_config()
95 cycles *= duty_ns; in berlin_pwm_config()
96 do_div(cycles, period_ns); in berlin_pwm_config()
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/linux/arch/xtensa/include/asm/
H A Ddelay.h40 unsigned long cycles = (usecs * (ccount_freq >> 15)) >> 5; in __udelay() local
43 while (((unsigned long)get_ccount()) - start < cycles) in __udelay()
61 unsigned long cycles = (nsec * (ccount_freq >> 15)) >> 15; in __ndelay() local
62 __delay(cycles); in __ndelay()
/linux/tools/testing/selftests/kvm/include/riscv/
H A Darch_timer.h22 #define cycles_to_usec(cycles) \ argument
23 ((u64)(cycles) * 1000000 / (timer_freq))
58 static inline void __delay(u64 cycles) in __delay() argument
62 while ((timer_get_cycles() - start) < cycles) in __delay()
/linux/tools/testing/selftests/kvm/include/loongarch/
H A Darch_timer.h14 #define cycles_to_usec(cycles) ((unsigned long)(cycles) * 1000000 / TIMER_FREQ) argument
73 static inline void __delay(u64 cycles) in __delay() argument
77 while ((timer_get_cycles() - start) < cycles) in __delay()
/linux/tools/virtio/ringtest/
H A Dmain.h21 static inline void wait_cycles(unsigned long long cycles) in wait_cycles() argument
26 while (__rdtsc() - t < cycles) {} in wait_cycles()
33 static inline void wait_cycles(unsigned long long cycles) in wait_cycles() argument
35 asm volatile("0: brctg %0,0b" : : "d" (cycles)); in wait_cycles()
43 static inline void wait_cycles(unsigned long long cycles) in wait_cycles() argument
/linux/Documentation/arch/m68k/
H A Dbuddha-driver.rst147 497ns Select (7 clock cycles) , IOR/IOW after 172ns (2 clock cycles)
152 639ns Select (9 clock cycles), IOR/IOW after 243ns (3 clock cycles)
155 781ns Select (11 clock cycles), IOR/IOW after 314ns (4 clock cycles)
158 355ns Select (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)
161 355ns Select (5 clock cycles), IOR/IOW after 172ns (2 clock cycles)
164 355ns Select (5 clock cycles), IOR/IOW after 243ns (3 clock cycles)
167 1065ns Select (15 clock cycles), IOR/IOW after 314ns (4 clock cycles)
170 355ns Select, (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)
176 781ns select, IOR/IOW after 4 clock cycles (=314ns) active.
180 system: Sometimes two more clock cycles are inserted by the
[all …]
/linux/tools/perf/util/
H A Dblock-info.c111 bi->cycles = ch->cycles; in init_block_info()
135 u64 cycles = 0; in block_info__process_sym() local
161 cycles += bi->cycles_aggr / bi->num_aggr; in block_info__process_sym()
173 *block_cycles_aggr += cycles; in block_info__process_sym()
244 static void cycles_string(u64 cycles, char *buf, int size) in cycles_string() argument
246 if (cycles >= 1000000) in cycles_string()
247 scnprintf(buf, size, "%.1fM", (double)cycles / 1000000.0); in cycles_string()
248 else if (cycles >= 1000) in cycles_string()
249 scnprintf(buf, size, "%.1fK", (double)cycles / 1000. in cycles_string()
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/linux/tools/power/cpupower/bench/
H A Dbenchmark.c113 " for %lius\n", _round + 1, config->cycles, in start_benchmark()
125 for (cycle = 0; cycle < config->cycles; cycle++) { in start_benchmark()
139 performance_time / config->cycles); in start_benchmark()
151 for (cycle = 0; cycle < config->cycles; cycle++) { in start_benchmark()
169 powersave_time / config->cycles); in start_benchmark()
H A DREADME-BENCH35 will be run X time in a row (cycles):
39 cycles=20
50 25ms load/sleep time repeated 20 times (cycles).
51 50ms load/sleep time repeated 20 times (cycles).
53 100ms load/sleep time repeated 20 times (cycles).
83 But if ondemand always kicks in in the middle of the load sleep cycles, it
116 -n, --cycles=<int> load/sleep cycles to get an average value to compare
/linux/drivers/char/hw_random/
H A Dcavium-rng-vf.c85 u64 status, cycles; in check_rng_health() local
99 cycles = status >> 1; in check_rng_health()
100 if (!cycles) in check_rng_health()
109 cycles = cycles / 2; in check_rng_health()
110 cur_err = (cycles * 1000000000) / rng->clock_rate; /* In nanosec */ in check_rng_health()
/linux/sound/firewire/
H A Damdtp-stream-trace.h17 …TP_PROTO(const struct amdtp_stream *s, u32 cycles, const __be32 *cip_header, unsigned int payload_…
18 …TP_ARGS(s, cycles, cip_header, payload_length, data_blocks, data_block_counter, packet_index, inde…
36 __entry->second = cycles / CYCLES_PER_SECOND;
37 __entry->cycle = cycles % CYCLES_PER_SECOND;
/linux/arch/arm/mach-omap1/
H A Dtimer32k.c180 static cycles_t cycles; variable
196 last_cycles = cycles; in omap_read_persistent_clock64()
197 cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; in omap_read_persistent_clock64()
199 nsecs = clocksource_cyc2ns(cycles - last_cycles, in omap_read_persistent_clock64()
/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Dspectrum_ptp.c85 struct cyclecounter cycles; member
137 container_of(cc, struct mlxsw_sp1_ptp_clock, cycles); in mlxsw_sp1_ptp_read_frc()
155 u64 cycles = (u64) nsec; in mlxsw_sp1_ptp_ns2cycles() local
157 cycles <<= tc->cc->shift; in mlxsw_sp1_ptp_ns2cycles()
158 cycles = div_u64(cycles, tc->cc->mult); in mlxsw_sp1_ptp_ns2cycles()
160 return cycles; in mlxsw_sp1_ptp_ns2cycles()
167 u64 next_sec, next_sec_in_nsec, cycles; in mlxsw_sp1_ptp_phc_settime() local
176 cycles = mlxsw_sp1_ptp_ns2cycles(&clock->tc, next_sec_in_nsec); in mlxsw_sp1_ptp_phc_settime()
179 mlxsw_reg_mtpps_vpin_pack(mtpps_pl, cycles); in mlxsw_sp1_ptp_phc_settime()
199 clock->cycles.mult = adjust_by_scaled_ppm(clock->nominal_c_mult, in mlxsw_sp1_ptp_adjfine()
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/linux/drivers/memory/
H A Dpl172.c61 int cycles; in pl172_timing_prop() local
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
66 if (cycles < 0) { in pl172_timing_prop()
67 cycles = 0; in pl172_timing_prop()
68 } else if (cycles > max) { in pl172_timing_prop()
73 writel(cycles, pl172->base + reg_offset); in pl172_timing_prop()

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