Searched refs:cx0pll (Results 1 – 5 of 5) sorted by relevance
2040 struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll; in intel_c10pll_update_pll()2072 crtc_state->dpll_hw_state.cx0pll.c10 = *tables[i]; in intel_c10pll_calc_state()2074 crtc_state->dpll_hw_state.cx0pll.use_c10 = true; in intel_c10pll_calc_state()2113 const struct intel_c10pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c10; in intel_c10_pll_program()2179 struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; in intel_c20_compute_hdmi_tmds_pll()2324 crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i]; in intel_c20pll_calc_state()2325 crtc_state->dpll_hw_state.cx0pll.use_c10 = false; in intel_c20pll_calc_state()2593 const struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; in intel_c20_pll_program()2750 val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; in intel_program_port_clock_ctl()2752 val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; in intel_program_port_clock_ctl()[all …]
279 struct intel_cx0pll_state cx0pll; member
4253 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_ddi_get_config()4255 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) in mtl_ddi_get_config()4258 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_ddi_get_config()
1234 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_crtc_compute_clock()
5666 PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll); in intel_pipe_config_compare()