Lines Matching refs:cx0pll
2093 &crtc_state->dpll_hw_state.cx0pll); in intel_c10pll_calc_state()
2099 intel_snps_hdmi_pll_compute_c10pll(&crtc_state->dpll_hw_state.cx0pll.c10, in intel_c10pll_calc_state()
2102 &crtc_state->dpll_hw_state.cx0pll); in intel_c10pll_calc_state()
2103 crtc_state->dpll_hw_state.cx0pll.use_c10 = true; in intel_c10pll_calc_state()
2241 struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; in intel_c20_compute_hdmi_tmds_pll()
2355 crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i]; in intel_c20pll_calc_state()
2357 &crtc_state->dpll_hw_state.cx0pll, in intel_c20pll_calc_state()
2359 crtc_state->dpll_hw_state.cx0pll.use_c10 = false; in intel_c20pll_calc_state()
3096 __intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll, in intel_cx0pll_enable()
3424 const struct intel_c10pll_state *mpllb_sw_state = &state->dpll_hw_state.cx0pll.c10; in intel_c10pll_state_verify()
3531 const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20; in intel_c20pll_state_verify()