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Searched refs:cs_mask (Results 1 – 25 of 30) sorted by relevance

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/linux/sound/pci/ice1712/
H A Dak4xxx.c56 if (priv->cs_mask == priv->cs_addr) { in snd_ice1712_akm4xxx_write()
58 tmp |= priv->cs_mask; /* start without chip select */ in snd_ice1712_akm4xxx_write()
60 tmp &= ~priv->cs_mask; /* chip select low */ in snd_ice1712_akm4xxx_write()
66 tmp &= ~priv->cs_mask; in snd_ice1712_akm4xxx_write()
93 if (priv->cs_mask == priv->cs_addr) { in snd_ice1712_akm4xxx_write()
96 tmp &= ~priv->cs_mask; in snd_ice1712_akm4xxx_write()
100 tmp |= priv->cs_mask; /* chip select high to trigger */ in snd_ice1712_akm4xxx_write()
102 tmp &= ~priv->cs_mask; in snd_ice1712_akm4xxx_write()
H A Ddelta.c246 priv->cs_mask = in delta_ak4524_lock()
260 priv->cs_mask = ICE1712_DELTA_1010LT_CS; in delta1010lt_ak4524_lock()
273 priv->cs_mask = in delta66e_ak4524_lock()
287 priv->cs_mask = in vx442_ak4524_lock()
439 .cs_mask = ICE1712_DELTA_AP_CS_CODEC,
460 .cs_mask = ICE1712_DELTA_AP_CS_CODEC,
482 .cs_mask = 0,
504 .cs_mask = 0,
527 .cs_mask = 0,
549 .cs_mask = 0,
H A Drevo.c238 .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1 | VT1724_REVO_CS2,
260 .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1 | VT1724_REVO_CS2,
281 .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1,
299 .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1,
349 .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS3,
H A Dews.c205 tmp = priv->cs_mask = priv->cs_addr = (1 << chip) & ICE1712_6FIRE_AK4524_CS_MASK; in dmx6fire_ak4524_lock()
343 .cs_mask = 0,
364 .cs_mask = ICE1712_EWX2496_AK4524_CS,
385 .cs_mask = 0,
H A Dhoontech.c288 .cs_mask = ICE1712_STDSP24_AK4524_CS, in snd_ice1712_value_init()
H A Dice1712.h256 unsigned int cs_mask; /* bit mask for select/deselect address */ member
H A Dphase.c102 .cs_mask = 1 << 10,
/linux/drivers/usb/host/
H A Dehci-sched.c202 ps->usecs, ps->c_usecs, ps->cs_mask); in bandwidth_dbg()
238 if (qh->ps.cs_mask & m) in reserve_release_intr_bandwidth()
890 qh->ps.cs_mask = qh->ps.period ? in qh_schedule()
896 hw->hw_info2 |= cpu_to_hc32(ehci, qh->ps.cs_mask); in qh_schedule()
1092 stream->ps.cs_mask = 1; in iso_stream_init()
1096 stream->ps.cs_mask |= tmp << (8 + 2); in iso_stream_init()
1098 stream->ps.cs_mask = smask_out[hs_transfers - 1]; in iso_stream_init()
1329 s_mask = stream->ps.cs_mask; in reserve_release_iso_bandwidth()
1394 mask = stream->ps.cs_mask << (uframe & 7); in sitd_slot_ok()
1397 if (((stream->ps.cs_mask & 0xff) << (uframe & 7)) >= (1 << 7)) in sitd_slot_ok()
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-lmcx-defs.h1625 uint64_t cs_mask:8; member
1627 uint64_t cs_mask:8;
1639 uint64_t cs_mask:8; member
1641 uint64_t cs_mask:8;
1986 uint64_t cs_mask:8; member
1988 uint64_t cs_mask:8;
2003 uint64_t cs_mask:8; member
2005 uint64_t cs_mask:8;
/linux/drivers/edac/
H A Damd64_edac.c2218 u64 cs_base, cs_mask; in f1x_lookup_addr_in_dct() local
2234 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); in f1x_lookup_addr_in_dct()
2237 csrow, cs_base, cs_mask); in f1x_lookup_addr_in_dct()
2239 cs_mask = ~cs_mask; in f1x_lookup_addr_in_dct()
2242 (in_addr & cs_mask), (cs_base & cs_mask)); in f1x_lookup_addr_in_dct()
2244 if ((in_addr & cs_mask) == (cs_base & cs_mask)) { in f1x_lookup_addr_in_dct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce100/
H A Ddce100_resource.c343 static const struct dce110_clk_src_mask cs_mask = { variable
766 regs, &cs_shift, &cs_mask)) { in dce100_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce60/
H A Ddce60_resource.c369 static const struct dce110_clk_src_mask cs_mask = { variable
800 regs, &cs_shift, &cs_mask)) { in dce60_clock_source_create()
/linux/kernel/cgroup/
H A Dcpuset.c4296 const struct cpumask *cs_mask; in cpuset_cpus_allowed_fallback()
4300 cs_mask = task_cs(tsk)->cpus_allowed; in cpuset_cpus_allowed_fallback()
4301 if (is_in_v2_mode() && cpumask_subset(cs_mask, possible_mask)) {
4302 set_cpus_allowed_force(tsk, cs_mask);
4271 const struct cpumask *cs_mask; cpuset_cpus_allowed_fallback() local
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c244 static const struct dce110_clk_src_mask cs_mask = { variable
1820 regs, &cs_shift, &cs_mask)) { in dcn31_clock_source_create()
1966 regs, &cs_shift, &cs_mask)) { in dcn30_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c235 static const struct dce110_clk_src_mask cs_mask = { variable
1761 regs, &cs_shift, &cs_mask)) { in dcn31_clock_source_create()
2038 regs, &cs_shift, &cs_mask)) { in dcn30_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c543 static const struct dce110_clk_src_mask cs_mask = { variable
555 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { in dcn303_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c559 static const struct dce110_clk_src_mask cs_mask = { variable
571 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { in dcn302_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c224 static const struct dce110_clk_src_mask cs_mask = { variable
1753 regs, &cs_shift, &cs_mask)) { in dcn31_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c223 static const struct dce110_clk_src_mask cs_mask = { variable
1858 regs, &cs_shift, &cs_mask)) { in dcn35_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c238 static const struct dce110_clk_src_mask cs_mask = { variable
1871 regs, &cs_shift, &cs_mask)) { in dcn35_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c238 static const struct dce110_clk_src_mask cs_mask = { variable
1763 regs, &cs_shift, &cs_mask)) { in dcn31_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c225 static const struct dce110_clk_src_mask cs_mask = { variable
872 regs, &cs_shift, &cs_mask)) { in dcn321_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c218 static const struct dce110_clk_src_mask cs_mask = { variable
1851 regs, &cs_shift, &cs_mask)) { in dcn35_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn60/
H A Ddcn60_resource.c228 static const struct dce110_clk_src_mask cs_mask = { variable
1070 regs, &cs_shift, &cs_mask)) { in dcn60_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c211 static const struct dce110_clk_src_mask cs_mask = { variable
889 regs, &cs_shift, &cs_mask)) { in dcn401_clock_source_create()

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