| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_vrr.c | 96 bool intel_vrr_possible(const struct intel_crtc_state *crtc_state) in intel_vrr_possible() argument
98 return crtc_state->vrr.flipline; in intel_vrr_possible()
138 static int intel_vrr_guardband_to_pipeline_full(const struct intel_crtc_state *crtc_state, in intel_vrr_guardband_to_pipeline_full() argument
142 return guardband - crtc_state->framestart_delay - 1; in intel_vrr_guardband_to_pipeline_full()
145 static int intel_vrr_pipeline_full_to_guardband(const struct intel_crtc_state *crtc_state, in intel_vrr_pipeline_full_to_guardband() argument
149 return pipeline_full + crtc_state->framestart_delay + 1; in intel_vrr_pipeline_full_to_guardband()
169 int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state) in intel_vrr_vmin_vtotal() argument
172 return crtc_state->vrr.vmin; in intel_vrr_vmin_vtotal()
175 int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state) in intel_vrr_vmax_vtotal() argument
177 return crtc_state->vrr.vmax; in intel_vrr_vmax_vtotal()
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| H A D | intel_atomic.c | 125 struct drm_crtc_state *crtc_state; in intel_digital_connector_atomic_check() local
132 crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc); in intel_digital_connector_atomic_check()
146 crtc_state->mode_changed = true; in intel_digital_connector_atomic_check()
202 struct intel_crtc_state *crtc_state; in intel_any_crtc_needs_modeset() local
204 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { in intel_any_crtc_needs_modeset()
205 if (intel_crtc_needs_modeset(crtc_state)) in intel_any_crtc_needs_modeset()
239 struct intel_crtc_state *crtc_state; in intel_crtc_duplicate_state() local
241 crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL); in intel_crtc_duplicate_state()
242 if (!crtc_state) in intel_crtc_duplicate_state()
245 __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi); in intel_crtc_duplicate_state()
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| H A D | intel_ddi.c | 135 const struct intel_crtc_state *crtc_state) in hsw_prepare_dp_ddi_buffers() argument
143 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers()
166 const struct intel_crtc_state *crtc_state) in hsw_prepare_hdmi_ddi_buffers() argument
169 int level = intel_ddi_level(encoder, crtc_state, 0); in hsw_prepare_hdmi_ddi_buffers()
175 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); in hsw_prepare_hdmi_ddi_buffers()
268 const struct intel_crtc_state *crtc_state) in icl_pll_to_ddi_clk_sel() argument
270 const struct intel_dpll *pll = crtc_state->intel_dpll; in icl_pll_to_ddi_clk_sel()
271 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
354 const struct intel_crtc_state *crtc_state) in intel_ddi_init_dp_buf_reg() argument
361 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | in intel_ddi_init_dp_buf_reg()
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| H A D | intel_dp_link_training.c | 731 const struct intel_crtc_state *crtc_state, in intel_dp_phy_voltage_max() argument
742 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state); in intel_dp_phy_voltage_max()
786 const struct intel_crtc_state *crtc_state, in intel_dp_get_lane_adjust_tx_ffe_preset() argument
794 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_tx_ffe_preset()
797 for (lane = 0; lane < crtc_state->lane_count; lane++) in intel_dp_get_lane_adjust_tx_ffe_preset()
806 const struct intel_crtc_state *crtc_state, in intel_dp_get_lane_adjust_vswing_preemph() argument
817 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_vswing_preemph()
822 for (lane = 0; lane < crtc_state->lane_count; lane++) { in intel_dp_get_lane_adjust_vswing_preemph()
834 voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy); in intel_dp_get_lane_adjust_vswing_preemph()
842 const struct intel_crtc_state *crtc_state, in intel_dp_get_lane_adjust_train() argument
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| H A D | intel_psr.c | 207 const struct intel_crtc_state *crtc_state) in intel_psr_needs_aux_io_power() argument
221 return intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && in intel_psr_needs_aux_io_power()
778 const struct intel_crtc_state *crtc_state) in _panel_replay_enable_sink() argument
789 if (crtc_state->has_sel_update) in _panel_replay_enable_sink()
792 if (crtc_state->enable_psr2_su_region_et) in _panel_replay_enable_sink()
795 if (crtc_state->req_psr2_sdp_prior_scanline) in _panel_replay_enable_sink()
807 const struct intel_crtc_state *crtc_state) in _psr_enable_sink() argument
812 if (crtc_state->has_sel_update) { in _psr_enable_sink()
822 if (crtc_state->req_psr2_sdp_prior_scanline) in _psr_enable_sink()
825 if (crtc_state->enable_psr2_su_region_et) in _psr_enable_sink()
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| H A D | intel_ddi.h | 27 const struct intel_crtc_state *crtc_state);
30 const struct intel_crtc_state *crtc_state);
32 const struct intel_crtc_state *crtc_state);
39 const struct intel_crtc_state *crtc_state);
42 struct intel_crtc_state *crtc_state,
45 const struct intel_crtc_state *crtc_state);
50 const struct intel_crtc_state *crtc_state);
52 struct intel_crtc_state *crtc_state);
55 const struct intel_crtc_state *crtc_state);
61 const struct intel_crtc_state *crtc_state);
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| H A D | intel_vdsc.h | 21 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
26 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state);
27 void intel_dsc_enable(const struct intel_crtc_state *crtc_state);
28 void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
30 void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state);
31 bool intel_dsc_enabled_on_link(const struct intel_crtc_state *crtc_state);
32 void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
36 int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state);
38 const struct intel_crtc_state *crtc_state);
40 const struct intel_crtc_state *crtc_state);
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| H A D | intel_dp_mst.c | 144 static int intel_dp_mst_max_dpt_bpp(const struct intel_crtc_state *crtc_state, in intel_dp_mst_max_dpt_bpp() argument
147 struct intel_display *display = to_intel_display(crtc_state); in intel_dp_mst_max_dpt_bpp()
149 &crtc_state->hw.adjusted_mode; in intel_dp_mst_max_dpt_bpp()
151 if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(display) >= 20 || !dsc) in intel_dp_mst_max_dpt_bpp()
174 return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72, in intel_dp_mst_max_dpt_bpp()
179 static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state, in intel_dp_mst_bw_overhead() argument
183 &crtc_state->hw.adjusted_mode; in intel_dp_mst_bw_overhead()
187 flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0; in intel_dp_mst_bw_overhead()
189 return intel_dp_link_bw_overhead(crtc_state->port_clock, in intel_dp_mst_bw_overhead()
190 crtc_state->lane_count, in intel_dp_mst_bw_overhead()
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| H A D | intel_hdmi.h | 27 const struct intel_crtc_state *crtc_state,
40 const struct intel_crtc_state *crtc_state);
43 struct intel_crtc_state *crtc_state);
45 const struct intel_crtc_state *crtc_state,
48 const struct intel_crtc_state *crtc_state,
51 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
53 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
59 int intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
66 const struct intel_crtc_state *crtc_state,
70 const struct intel_crtc_state *crtc_state,
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| H A D | intel_cursor.c | 41 static u32 intel_cursor_position(const struct intel_crtc_state *crtc_state, in intel_cursor_position() argument
56 y - crtc_state->psr2_su_area.y1); in intel_cursor_position()
137 static int intel_check_cursor(struct intel_crtc_state *crtc_state, in intel_check_cursor() argument
153 ret = intel_plane_check_clipping(plane_state, crtc_state, in intel_check_cursor()
166 -crtc_state->pipe_src.x1, in intel_check_cursor()
167 -crtc_state->pipe_src.y1); in intel_check_cursor()
198 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) in i845_cursor_ctl_crtc() argument
202 if (crtc_state->gamma_enable) in i845_cursor_ctl_crtc()
226 static int i845_check_cursor(struct intel_crtc_state *crtc_state, in i845_check_cursor() argument
234 ret = intel_check_cursor(crtc_state, plane_state); in i845_check_cursor()
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| H A D | intel_dp.c | 129 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) in intel_dp_is_uhbr() argument
131 return drm_dp_is_uhbr_rate(crtc_state->port_clock); in intel_dp_is_uhbr()
1597 const struct intel_crtc_state *crtc_state) in intel_dp_supports_dsc() argument
1602 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && in intel_dp_supports_dsc()
1603 !intel_dp_supports_fec(intel_dp, connector, crtc_state)) in intel_dp_supports_dsc()
1606 return intel_dsc_source_support(crtc_state); in intel_dp_supports_dsc()
1610 const struct intel_crtc_state *crtc_state, in intel_dp_hdmi_compute_bpc() argument
1613 int clock = crtc_state->hw.adjusted_mode.crtc_clock; in intel_dp_hdmi_compute_bpc()
1631 if (intel_hdmi_bpc_possible(crtc_state, bpc, in intel_dp_hdmi_compute_bpc()
1633 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format, in intel_dp_hdmi_compute_bpc()
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| H A D | intel_link_bw.c | 63 const struct intel_crtc_state *crtc_state = in intel_link_bw_init_limits() local
67 if ((state->base.duplicated && crtc_state) || in intel_link_bw_init_limits()
69 limits->max_bpp_x16[pipe] = crtc_state->max_link_bpp_x16; in intel_link_bw_init_limits()
70 if (intel_dsc_enabled_on_link(crtc_state)) in intel_link_bw_init_limits()
113 struct intel_crtc_state *crtc_state; in __intel_link_bw_reduce_bpp() local
119 crtc_state = intel_atomic_get_crtc_state(&state->base, in __intel_link_bw_reduce_bpp()
121 if (IS_ERR(crtc_state)) in __intel_link_bw_reduce_bpp()
122 return PTR_ERR(crtc_state); in __intel_link_bw_reduce_bpp()
124 if (crtc_state->dsc.compression_enable) in __intel_link_bw_reduce_bpp()
125 link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16; in __intel_link_bw_reduce_bpp()
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| H A D | hsw_ips.h | 16 bool hsw_ips_disable(const struct intel_crtc_state *crtc_state);
22 int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state);
25 void hsw_ips_get_config(struct intel_crtc_state *crtc_state);
28 static inline bool hsw_ips_disable(const struct intel_crtc_state *crtc_state) in hsw_ips_disable() argument
45 static inline int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state) in hsw_ips_min_cdclk() argument
54 static inline void hsw_ips_get_config(struct intel_crtc_state *crtc_state) in hsw_ips_get_config() argument
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| H A D | intel_display_types.h | 218 const struct intel_crtc_state *crtc_state,
239 const struct intel_crtc_state *crtc_state);
246 struct intel_crtc_state *crtc_state);
253 struct intel_crtc_state *crtc_state);
281 const struct intel_crtc_state *crtc_state);
291 const struct intel_crtc_state *crtc_state);
293 const struct intel_crtc_state *crtc_state,
296 const struct intel_crtc_state *crtc_state);
311 void (*enable)(const struct intel_crtc_state *crtc_state,
542 const struct intel_crtc_state *crtc_state);
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| H A D | intel_audio.h | 18 struct intel_crtc_state *crtc_state,
21 const struct intel_crtc_state *crtc_state,
27 struct intel_crtc_state *crtc_state);
30 int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state);
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| H A D | skl_universal_plane.c | 266 static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, in icl_plane_min_cdclk() argument
269 unsigned int pixel_rate = intel_plane_pixel_rate_cdclk(crtc_state, plane_state); in icl_plane_min_cdclk()
290 static int glk_plane_min_cdclk(const struct intel_crtc_state *crtc_state, in glk_plane_min_cdclk() argument
293 unsigned int pixel_rate = intel_plane_pixel_rate_cdclk(crtc_state, plane_state); in glk_plane_min_cdclk()
317 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, in skl_plane_min_cdclk() argument
320 unsigned int pixel_rate = intel_plane_pixel_rate_cdclk(crtc_state, plane_state); in skl_plane_min_cdclk()
823 const struct intel_crtc_state *crtc_state) in skl_write_plane_wm() argument
828 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; in skl_write_plane_wm()
830 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_write_plane_wm()
832 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_write_plane_wm()
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| H A D | intel_cx0_phy.c | 426 static u8 intel_c10_get_tx_vboost_lvl(const struct intel_crtc_state *crtc_state) in intel_c10_get_tx_vboost_lvl() argument
428 if (intel_crtc_has_dp_encoder(crtc_state)) { in intel_c10_get_tx_vboost_lvl()
429 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && in intel_c10_get_tx_vboost_lvl()
430 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_vboost_lvl()
431 crtc_state->port_clock == 810000)) in intel_c10_get_tx_vboost_lvl()
440 static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state) in intel_c10_get_tx_term_ctl() argument
442 if (intel_crtc_has_dp_encoder(crtc_state)) { in intel_c10_get_tx_term_ctl()
443 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && in intel_c10_get_tx_term_ctl()
444 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_term_ctl()
445 crtc_state->port_clock == 810000)) in intel_c10_get_tx_term_ctl()
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| H A D | intel_dp_mst.h | 22 bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state);
23 bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state);
37 struct intel_crtc_state *crtc_state,
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| H A D | intel_cdclk.c | 2930 static int _intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state, int pixel_rate) in _intel_pixel_rate_to_cdclk() argument
2932 struct intel_display *display = to_intel_display(crtc_state); in _intel_pixel_rate_to_cdclk()
2933 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); in _intel_pixel_rate_to_cdclk()
2939 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) in intel_pixel_rate_to_cdclk() argument
2941 return _intel_pixel_rate_to_cdclk(crtc_state, crtc_state->pixel_rate_cdclk); in intel_pixel_rate_to_cdclk()
2944 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) in intel_planes_min_cdclk() argument
2946 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_planes_min_cdclk()
2952 min_cdclk = max(min_cdclk, crtc_state->plane_min_cdclk[plane->id]); in intel_planes_min_cdclk()
2957 int intel_crtc_min_cdclk(const struct intel_crtc_state *crtc_state) in intel_crtc_min_cdclk() argument
2961 if (!crtc_state->hw.enable) in intel_crtc_min_cdclk()
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| /linux/drivers/gpu/drm/gma500/ |
| H A D | gma_display.c | 506 kfree(gma_crtc->crtc_state); in gma_crtc_destroy()
580 struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; in gma_crtc_save() local
585 if (!crtc_state) { in gma_crtc_save()
590 crtc_state->saveDSPCNTR = REG_READ(map->cntr); in gma_crtc_save()
591 crtc_state->savePIPECONF = REG_READ(map->conf); in gma_crtc_save()
592 crtc_state->savePIPESRC = REG_READ(map->src); in gma_crtc_save()
593 crtc_state->saveFP0 = REG_READ(map->fp0); in gma_crtc_save()
594 crtc_state->saveFP1 = REG_READ(map->fp1); in gma_crtc_save()
595 crtc_state->saveDPLL = REG_READ(map->dpll); in gma_crtc_save()
596 crtc_state->saveHTOTAL = REG_READ(map->htotal); in gma_crtc_save()
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| /linux/drivers/gpu/drm/ |
| H A D | drm_atomic_uapi.c | 194 struct drm_crtc_state *crtc_state; in drm_atomic_set_crtc_for_plane() local
199 crtc_state = drm_atomic_get_crtc_state(plane_state->state, in drm_atomic_set_crtc_for_plane()
201 if (WARN_ON(IS_ERR(crtc_state))) in drm_atomic_set_crtc_for_plane()
202 return PTR_ERR(crtc_state); in drm_atomic_set_crtc_for_plane()
204 crtc_state->plane_mask &= ~drm_plane_mask(plane); in drm_atomic_set_crtc_for_plane()
210 crtc_state = drm_atomic_get_crtc_state(plane_state->state, in drm_atomic_set_crtc_for_plane()
212 if (IS_ERR(crtc_state)) in drm_atomic_set_crtc_for_plane()
213 return PTR_ERR(crtc_state); in drm_atomic_set_crtc_for_plane()
214 crtc_state->plane_mask |= drm_plane_mask(plane); in drm_atomic_set_crtc_for_plane()
316 struct drm_crtc_state *crtc_state; in drm_atomic_set_crtc_for_connector() local
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| H A D | drm_atomic_state_helper.c | 74 __drm_atomic_helper_crtc_state_init(struct drm_crtc_state *crtc_state, in __drm_atomic_helper_crtc_state_init() argument
77 crtc_state->crtc = crtc; in __drm_atomic_helper_crtc_state_init()
78 crtc_state->background_color = DRM_ARGB64_PREP(0xffff, 0, 0, 0); in __drm_atomic_helper_crtc_state_init()
96 struct drm_crtc_state *crtc_state) in __drm_atomic_helper_crtc_reset() argument
98 if (crtc_state) in __drm_atomic_helper_crtc_reset()
99 __drm_atomic_helper_crtc_state_init(crtc_state, crtc); in __drm_atomic_helper_crtc_reset()
104 crtc->state = crtc_state; in __drm_atomic_helper_crtc_reset()
117 struct drm_crtc_state *crtc_state = in drm_atomic_helper_crtc_reset() local
123 __drm_atomic_helper_crtc_reset(crtc, crtc_state); in drm_atomic_helper_crtc_reset()
681 struct drm_crtc_state *crtc_state; in drm_atomic_helper_connector_tv_check() local
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| H A D | drm_bridge.c | 1066 struct drm_crtc_state *crtc_state, in drm_atomic_bridge_check() argument
1073 bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state, in drm_atomic_bridge_check()
1079 crtc_state, conn_state); in drm_atomic_bridge_check()
1083 if (!bridge->funcs->mode_fixup(bridge, &crtc_state->mode, in drm_atomic_bridge_check()
1084 &crtc_state->adjusted_mode)) in drm_atomic_bridge_check()
1093 struct drm_crtc_state *crtc_state, in select_bus_fmt_recursive() argument
1104 cur_state = drm_atomic_get_new_bridge_state(crtc_state->state, in select_bus_fmt_recursive()
1116 prev_bridge, crtc_state, in select_bus_fmt_recursive()
1144 crtc_state, in select_bus_fmt_recursive()
1162 crtc_state, conn_state, in select_bus_fmt_recursive()
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| /linux/drivers/gpu/drm/tegra/ |
| H A D | plane.c | 231 struct drm_crtc_state *crtc_state; in tegra_plane_calculate_memory_bandwidth() local
237 crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); in tegra_plane_calculate_memory_bandwidth()
238 if (!crtc_state) in tegra_plane_calculate_memory_bandwidth()
271 avg_bandwidth *= drm_mode_vrefresh(&crtc_state->adjusted_mode); in tegra_plane_calculate_memory_bandwidth()
276 peak_bandwidth = DIV_ROUND_UP(crtc_state->adjusted_mode.clock * bpp, 8); in tegra_plane_calculate_memory_bandwidth()
300 struct drm_crtc_state *crtc_state; in tegra_plane_state_add() local
305 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); in tegra_plane_state_add()
306 if (IS_ERR(crtc_state)) in tegra_plane_state_add()
307 return PTR_ERR(crtc_state); in tegra_plane_state_add()
310 err = drm_atomic_helper_check_plane_state(state, crtc_state, in tegra_plane_state_add()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_crtc.c | 65 bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state, in amdgpu_dm_crtc_modeset_required() argument
69 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); in amdgpu_dm_crtc_modeset_required()
655 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, in amdgpu_dm_crtc_helper_atomic_check() local
659 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); in amdgpu_dm_crtc_helper_atomic_check()
662 trace_amdgpu_dm_crtc_atomic_check(crtc_state); in amdgpu_dm_crtc_helper_atomic_check()
664 amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state); in amdgpu_dm_crtc_helper_atomic_check()
667 amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) { in amdgpu_dm_crtc_helper_atomic_check()
677 if (crtc_state->enable && in amdgpu_dm_crtc_helper_atomic_check()
678 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) { in amdgpu_dm_crtc_helper_atomic_check()
687 if (crtc_state->async_flip && in amdgpu_dm_crtc_helper_atomic_check()
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