Lines Matching refs:crtc_state
211 const struct intel_crtc_state *crtc_state,
247 const struct intel_crtc_state *crtc_state,
279 const struct intel_crtc_state *crtc_state,
285 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
318 const struct intel_crtc_state *crtc_state,
323 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
354 const struct intel_crtc_state *crtc_state,
360 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
396 const struct intel_crtc_state *crtc_state,
401 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
428 const struct intel_crtc_state *crtc_state,
434 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
468 const struct intel_crtc_state *crtc_state,
473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
504 const struct intel_crtc_state *crtc_state,
510 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
536 if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr &&
537 !crtc_state->has_panel_replay && type == DP_SDP_VSC))
548 const struct intel_crtc_state *crtc_state,
552 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
606 const struct intel_crtc_state *crtc_state)
613 val = dig_port->infoframes_enabled(encoder, crtc_state);
649 const struct intel_crtc_state *crtc_state,
657 if ((crtc_state->infoframes.enable &
674 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
678 const struct intel_crtc_state *crtc_state,
686 if ((crtc_state->infoframes.enable &
690 dig_port->read_infoframe(encoder, crtc_state,
712 struct intel_crtc_state *crtc_state,
715 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
717 &crtc_state->hw.adjusted_mode;
721 if (!crtc_state->has_infoframe)
724 crtc_state->infoframes.enable |=
732 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
734 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
742 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
743 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
745 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
748 crtc_state->limited_color_range ?
769 struct intel_crtc_state *crtc_state,
772 struct intel_display *display = to_intel_display(crtc_state);
773 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
776 if (!crtc_state->has_infoframe)
779 crtc_state->infoframes.enable |=
801 struct intel_crtc_state *crtc_state,
805 &crtc_state->infoframes.hdmi.vendor.hdmi;
810 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
813 crtc_state->infoframes.enable |=
818 &crtc_state->hw.adjusted_mode);
831 struct intel_crtc_state *crtc_state,
835 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
841 if (!crtc_state->has_infoframe)
847 crtc_state->infoframes.enable |=
866 const struct intel_crtc_state *crtc_state,
923 intel_write_infoframe(encoder, crtc_state,
925 &crtc_state->infoframes.avi);
926 intel_write_infoframe(encoder, crtc_state,
928 &crtc_state->infoframes.spd);
929 intel_write_infoframe(encoder, crtc_state,
931 &crtc_state->infoframes.hdmi);
978 const struct intel_crtc_state *crtc_state,
982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
985 if ((crtc_state->infoframes.enable &
990 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);
998 intel_de_write(display, reg, crtc_state->infoframes.gcp);
1004 struct intel_crtc_state *crtc_state)
1007 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1010 if ((crtc_state->infoframes.enable &
1015 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);
1023 crtc_state->infoframes.gcp = intel_de_read(display, reg);
1027 struct intel_crtc_state *crtc_state,
1032 if (display->platform.g4x || !crtc_state->has_infoframe)
1035 crtc_state->infoframes.enable |=
1039 if (crtc_state->pipe_bpp > 24)
1040 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1043 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1044 &crtc_state->hw.adjusted_mode))
1045 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1050 const struct intel_crtc_state *crtc_state,
1054 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1090 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1096 intel_write_infoframe(encoder, crtc_state,
1098 &crtc_state->infoframes.avi);
1099 intel_write_infoframe(encoder, crtc_state,
1101 &crtc_state->infoframes.spd);
1102 intel_write_infoframe(encoder, crtc_state,
1104 &crtc_state->infoframes.hdmi);
1109 const struct intel_crtc_state *crtc_state,
1113 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1139 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1145 intel_write_infoframe(encoder, crtc_state,
1147 &crtc_state->infoframes.avi);
1148 intel_write_infoframe(encoder, crtc_state,
1150 &crtc_state->infoframes.spd);
1151 intel_write_infoframe(encoder, crtc_state,
1153 &crtc_state->infoframes.hdmi);
1158 const struct intel_crtc_state *crtc_state,
1162 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1197 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1203 intel_write_infoframe(encoder, crtc_state,
1205 &crtc_state->infoframes.avi);
1206 intel_write_infoframe(encoder, crtc_state,
1208 &crtc_state->infoframes.spd);
1209 intel_write_infoframe(encoder, crtc_state,
1211 &crtc_state->infoframes.hdmi);
1215 const struct intel_crtc_state *crtc_state,
1220 crtc_state->cpu_transcoder);
1223 if ((crtc_state->infoframes.enable &
1233 intel_write_infoframe(encoder, crtc_state,
1235 &crtc_state->infoframes.drm);
1240 const struct intel_crtc_state *crtc_state,
1245 crtc_state->cpu_transcoder);
1249 crtc_state->cpu_transcoder);
1262 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1268 intel_write_infoframe(encoder, crtc_state,
1270 &crtc_state->infoframes.avi);
1271 intel_write_infoframe(encoder, crtc_state,
1273 &crtc_state->infoframes.spd);
1274 intel_write_infoframe(encoder, crtc_state,
1276 &crtc_state->infoframes.hdmi);
1277 intel_write_infoframe(encoder, crtc_state,
1279 &crtc_state->infoframes.drm);
1842 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
1844 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
2073 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
2076 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
2082 if (connector_state->base.crtc != crtc_state->uapi.crtc)
2086 crtc_state->sink_format))
2093 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
2095 struct intel_display *display = to_intel_display(crtc_state);
2097 &crtc_state->hw.adjusted_mode;
2103 if (intel_hdmi_is_ycbcr420(crtc_state) &&
2109 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink);
2113 struct intel_crtc_state *crtc_state,
2123 bpc = max(crtc_state->pipe_bpp / 3, 8);
2135 crtc_state->sink_format);
2137 if (hdmi_bpc_possible(crtc_state, bpc) &&
2140 crtc_state->has_hdmi_sink) == MODE_OK)
2148 struct intel_crtc_state *crtc_state,
2153 &crtc_state->hw.adjusted_mode;
2159 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
2164 crtc_state->port_clock =
2165 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format);
2172 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
2176 bpc, crtc_state->pipe_bpp);
2181 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2187 &crtc_state->hw.adjusted_mode;
2191 * crtc_state->limited_color_range only applies to RGB,
2196 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2201 return crtc_state->has_hdmi_sink &&
2210 const struct intel_crtc_state *crtc_state,
2217 if (!crtc_state->has_hdmi_sink)
2227 intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state,
2231 if (!crtc_state->has_hdmi_sink)
2241 intel_hdmi_output_format(const struct intel_crtc_state *crtc_state)
2243 return crtc_state->sink_format;
2247 struct intel_crtc_state *crtc_state,
2253 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2258 crtc_state->sink_format =
2259 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only);
2261 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) {
2264 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2267 crtc_state->output_format = intel_hdmi_output_format(crtc_state);
2268 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2270 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2271 !crtc_state->has_hdmi_sink ||
2276 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2277 crtc_state->output_format = intel_hdmi_output_format(crtc_state);
2278 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2284 static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state)
2286 return crtc_state->uapi.encoder_mask &&
2287 !is_power_of_2(crtc_state->uapi.encoder_mask);
2310 const struct intel_crtc_state *crtc_state,
2316 !intel_hdmi_is_cloned(crtc_state);
3140 * @crtc_state: intel crtc_state
3150 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
3172 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
3183 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3184 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
3239 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);