Lines Matching refs:crtc_state
375 static int i9xx_pll_refclk(const struct intel_crtc_state *crtc_state)
377 struct intel_display *display = to_intel_display(crtc_state);
378 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
423 void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state)
425 struct intel_display *display = to_intel_display(crtc_state);
426 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
427 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
432 int refclk = i9xx_pll_refclk(crtc_state);
512 crtc_state->port_clock = port_clock;
515 void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
517 struct intel_display *display = to_intel_display(crtc_state);
518 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
521 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
540 crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);
543 void chv_crtc_clock_get(struct intel_crtc_state *crtc_state)
545 struct intel_display *display = to_intel_display(crtc_state);
546 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
549 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
574 crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock);
621 const struct intel_crtc_state *crtc_state,
624 struct intel_display *display = to_intel_display(crtc_state);
626 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
655 struct intel_crtc_state *crtc_state,
660 struct intel_display *display = to_intel_display(crtc_state);
666 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
713 struct intel_crtc_state *crtc_state,
718 struct intel_display *display = to_intel_display(crtc_state);
724 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
769 struct intel_crtc_state *crtc_state,
774 struct intel_display *display = to_intel_display(crtc_state);
783 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
863 struct intel_crtc_state *crtc_state,
868 struct intel_display *display = to_intel_display(crtc_state);
920 struct intel_crtc_state *crtc_state,
925 struct intel_display *display = to_intel_display(crtc_state);
976 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
982 return chv_find_best_dpll(limit, crtc_state,
983 crtc_state->port_clock, refclk,
997 static u32 i965_dpll_md(const struct intel_crtc_state *crtc_state)
999 return (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1002 static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state,
1006 struct intel_display *display = to_intel_display(crtc_state);
1011 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
1018 dpll |= (crtc_state->pixel_multiplier - 1)
1022 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
1023 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1026 if (intel_crtc_has_dp_encoder(crtc_state))
1060 if (crtc_state->sdvo_tv_clock)
1062 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1071 static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
1075 struct intel_display *display = to_intel_display(crtc_state);
1076 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1086 hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock);
1089 hw_state->dpll_md = i965_dpll_md(crtc_state);
1092 static u32 i8xx_dpll(const struct intel_crtc_state *crtc_state,
1096 struct intel_display *display = to_intel_display(crtc_state);
1101 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1127 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
1130 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1139 static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
1143 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1148 hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock);
1155 struct intel_crtc_state *crtc_state =
1158 intel_get_crtc_new_encoder(state, crtc_state);
1162 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1170 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1174 if (!crtc_state->has_pch_encoder)
1175 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1184 struct intel_crtc_state *crtc_state =
1187 intel_get_crtc_new_encoder(state, crtc_state);
1190 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1199 struct intel_crtc_state *crtc_state =
1202 intel_get_crtc_new_encoder(state, crtc_state);
1205 ret = intel_mpllb_calc_state(crtc_state, encoder);
1209 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1217 struct intel_crtc_state *crtc_state =
1220 intel_get_crtc_new_encoder(state, crtc_state);
1223 ret = intel_cx0pll_calc_state(crtc_state, encoder);
1228 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
1230 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1235 static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)
1237 struct intel_display *display = to_intel_display(crtc_state);
1239 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1244 if (crtc_state->sdvo_tv_clock)
1266 static u32 ilk_dpll(const struct intel_crtc_state *crtc_state,
1270 struct intel_display *display = to_intel_display(crtc_state);
1275 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
1280 dpll |= (crtc_state->pixel_multiplier - 1)
1283 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
1284 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1287 if (intel_crtc_has_dp_encoder(crtc_state))
1305 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1329 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1338 static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
1342 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1343 int factor = ilk_fb_cb_factor(crtc_state);
1348 hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock);
1355 struct intel_crtc_state *crtc_state =
1362 if (!crtc_state->has_pch_encoder)
1365 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1388 if (!crtc_state->clock_set &&
1389 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1390 refclk, NULL, &crtc_state->dpll))
1393 i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1395 ilk_compute_dpll(crtc_state, &crtc_state->dpll,
1396 &crtc_state->dpll);
1402 crtc_state->port_clock = crtc_state->dpll.dot;
1403 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1411 struct intel_crtc_state *crtc_state =
1415 if (!crtc_state->has_pch_encoder)
1421 static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
1423 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1433 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1439 void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
1441 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1443 hw_state->dpll = vlv_dpll(crtc_state);
1444 hw_state->dpll_md = i965_dpll_md(crtc_state);
1447 static u32 chv_dpll(const struct intel_crtc_state *crtc_state)
1449 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1459 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1465 void chv_compute_dpll(struct intel_crtc_state *crtc_state)
1467 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1469 hw_state->dpll = chv_dpll(crtc_state);
1470 hw_state->dpll_md = i965_dpll_md(crtc_state);
1476 struct intel_crtc_state *crtc_state =
1481 if (!crtc_state->clock_set &&
1482 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1483 refclk, NULL, &crtc_state->dpll))
1486 chv_calc_dpll_params(refclk, &crtc_state->dpll);
1488 chv_compute_dpll(crtc_state);
1491 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1494 crtc_state->port_clock = crtc_state->dpll.dot;
1495 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1503 struct intel_crtc_state *crtc_state =
1508 if (!crtc_state->clock_set &&
1509 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1510 refclk, NULL, &crtc_state->dpll))
1513 vlv_calc_dpll_params(refclk, &crtc_state->dpll);
1515 vlv_compute_dpll(crtc_state);
1518 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1521 crtc_state->port_clock = crtc_state->dpll.dot;
1522 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1531 struct intel_crtc_state *crtc_state =
1536 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1548 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
1549 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1551 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
1558 if (!crtc_state->clock_set &&
1559 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1560 refclk, NULL, &crtc_state->dpll))
1563 i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1565 i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1566 &crtc_state->dpll);
1568 crtc_state->port_clock = crtc_state->dpll.dot;
1570 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_TVOUT))
1571 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1580 struct intel_crtc_state *crtc_state =
1585 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1598 if (!crtc_state->clock_set &&
1599 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1600 refclk, NULL, &crtc_state->dpll))
1603 pnv_calc_dpll_params(refclk, &crtc_state->dpll);
1605 i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1606 &crtc_state->dpll);
1608 crtc_state->port_clock = crtc_state->dpll.dot;
1609 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1618 struct intel_crtc_state *crtc_state =
1623 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1636 if (!crtc_state->clock_set &&
1637 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1638 refclk, NULL, &crtc_state->dpll))
1641 i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1643 i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1644 &crtc_state->dpll);
1646 crtc_state->port_clock = crtc_state->dpll.dot;
1648 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_TVOUT))
1649 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1658 struct intel_crtc_state *crtc_state =
1663 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1672 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
1678 if (!crtc_state->clock_set &&
1679 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1680 refclk, NULL, &crtc_state->dpll))
1683 i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1685 i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
1686 &crtc_state->dpll);
1688 crtc_state->port_clock = crtc_state->dpll.dot;
1689 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1740 struct intel_crtc_state *crtc_state =
1744 drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));
1746 memset(&crtc_state->dpll_hw_state, 0,
1747 sizeof(crtc_state->dpll_hw_state));
1749 if (!crtc_state->hw.enable)
1766 struct intel_crtc_state *crtc_state =
1770 drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));
1771 drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->intel_dpll);
1773 if (!crtc_state->hw.enable || crtc_state->intel_dpll)
1822 void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
1824 struct intel_display *display = to_intel_display(crtc_state);
1825 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1826 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1830 assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
1901 static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
1903 struct intel_display *display = to_intel_display(crtc_state);
1904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1905 const struct dpll *clock = &crtc_state->dpll;
1950 if (crtc_state->port_clock == 162000 ||
1951 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) ||
1952 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1957 if (intel_crtc_has_dp_encoder(crtc_state)) {
1973 if (intel_crtc_has_dp_encoder(crtc_state))
1982 static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)
1984 struct intel_display *display = to_intel_display(crtc_state);
1985 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1986 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1997 void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
1999 struct intel_display *display = to_intel_display(crtc_state);
2000 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2001 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
2004 assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
2014 vlv_prepare_pll(crtc_state);
2015 _vlv_enable_pll(crtc_state);
2022 static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
2024 struct intel_display *display = to_intel_display(crtc_state);
2025 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2026 const struct dpll *clock = &crtc_state->dpll;
2111 static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
2113 struct intel_display *display = to_intel_display(crtc_state);
2114 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2115 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
2143 void chv_enable_pll(const struct intel_crtc_state *crtc_state)
2145 struct intel_display *display = to_intel_display(crtc_state);
2146 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2147 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
2150 assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
2160 chv_prepare_pll(crtc_state);
2161 _chv_enable_pll(crtc_state);
2205 struct intel_crtc_state *crtc_state;
2207 crtc_state = intel_crtc_state_alloc(crtc);
2208 if (!crtc_state)
2211 crtc_state->cpu_transcoder = (enum transcoder)pipe;
2212 crtc_state->pixel_multiplier = 1;
2213 crtc_state->dpll = *dpll;
2214 crtc_state->output_types = BIT(INTEL_OUTPUT_EDP);
2217 chv_compute_dpll(crtc_state);
2218 chv_enable_pll(crtc_state);
2220 vlv_compute_dpll(crtc_state);
2221 vlv_enable_pll(crtc_state);
2224 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
2272 void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
2274 struct intel_display *display = to_intel_display(crtc_state);
2275 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2283 assert_transcoder_disabled(display, crtc_state->cpu_transcoder);