Searched refs:clock_table (Results 1 – 8 of 8) sorted by relevance
632 const DpmClocks314_t *clock_table) in dcn314_clk_mgr_helper_populate_bw_params() argument641 for (i = 0; i < clock_table->NumDfPstatesEnabled; i++) { in dcn314_clk_mgr_helper_populate_bw_params()642 if (is_valid_clock_value(clock_table->DfPstateTable[i].FClk) && in dcn314_clk_mgr_helper_populate_bw_params()643 clock_table->DfPstateTable[i].FClk > max_fclk) { in dcn314_clk_mgr_helper_populate_bw_params()644 max_fclk = clock_table->DfPstateTable[i].FClk; in dcn314_clk_mgr_helper_populate_bw_params()653 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn314_clk_mgr_helper_populate_bw_params()654 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn314_clk_mgr_helper_populate_bw_params()655 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()656 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()663 for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) { in dcn314_clk_mgr_helper_populate_bw_params()[all …]
540 const DpmClocks_t *clock_table, in find_clk_for_voltage() argument549 if (clock_table->SocVoltage[i] == voltage) { in find_clk_for_voltage()551 } else if (clock_table->SocVoltage[i] >= max_voltage && in find_clk_for_voltage()552 clock_table->SocVoltage[i] < voltage) { in find_clk_for_voltage()553 max_voltage = clock_table->SocVoltage[i]; in find_clk_for_voltage()564 const DpmClocks_t *clock_table) in dcn31_clk_mgr_helper_populate_bw_params() argument579 if (clock_table->DfPstateTable[i].FClk != 0) { in dcn31_clk_mgr_helper_populate_bw_params()594 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn31_clk_mgr_helper_populate_bw_params()595 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn31_clk_mgr_helper_populate_bw_params()596 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn31_clk_mgr_helper_populate_bw_params()[all …]
1041 DpmClocks_t_dcn35 *clock_table) in dcn35_clk_mgr_helper_populate_bw_params() argument1052 num_memps = (clock_table->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS) ? NUM_MEM_PSTATE_LEVELS : in dcn35_clk_mgr_helper_populate_bw_params()1053 clock_table->NumMemPstatesEnabled; in dcn35_clk_mgr_helper_populate_bw_params()1055 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[entry_idx]); in dcn35_clk_mgr_helper_populate_bw_params()1067 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[entry_idx]); in dcn35_clk_mgr_helper_populate_bw_params()1076 ASSERT(clock_table->NumMemPstatesEnabled && in dcn35_clk_mgr_helper_populate_bw_params()1081 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn35_clk_mgr_helper_populate_bw_params()1082 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn35_clk_mgr_helper_populate_bw_params()1083 max_dispclk = find_max_clk_value(clock_table->DispClocks, in dcn35_clk_mgr_helper_populate_bw_params()1084 clock_table->NumDispClkLevelsEnabled); in dcn35_clk_mgr_helper_populate_bw_params()[all …]
1653 static int smu_v15_0_0_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table) in smu_v15_0_0_get_dpm_table() argument1660 …clock_table->SocClocks[idx].Freq = (idx < clk_table->NumSocClkLevelsEnabled) ? clk_table->SocClock… in smu_v15_0_0_get_dpm_table()1661 clock_table->SocClocks[idx].Vol = 0; in smu_v15_0_0_get_dpm_table()1665 …clock_table->VPEClocks[idx].Freq = (idx < clk_table->VpeClkLevelsEnabled) ? clk_table->VPEClocks[i… in smu_v15_0_0_get_dpm_table()1666 clock_table->VPEClocks[idx].Vol = 0; in smu_v15_0_0_get_dpm_table()1672 static int smu_v15_0_5_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table) in smu_v15_0_5_get_dpm_table() argument1682 clock_table->SocClocks[idx].Freq = in smu_v15_0_5_get_dpm_table()1684 clock_table->SocClocks[idx].Vol = 0; in smu_v15_0_5_get_dpm_table()1688 clock_table->VPEClocks[idx].Freq = in smu_v15_0_5_get_dpm_table()1690 clock_table->VPEClocks[idx].Vol = 0; in smu_v15_0_5_get_dpm_table()[all …]
286 struct dpm_clocks *clock_table);306 struct dpm_clocks *clock_table);
297 DpmClocks_t clock_table; member
2031 struct dpm_clocks *clock_table) in amdgpu_dpm_get_dpm_clock_table() argument2041 clock_table); in amdgpu_dpm_get_dpm_clock_table()
528 struct dpm_clocks *clock_table);