| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| H A D | smu_v13_0_5_ppt.c | 413 struct pp_smu_wm_range_sets *clock_ranges) in smu_v13_0_5_set_watermarks_table() argument
419 if (!table || !clock_ranges) in smu_v13_0_5_set_watermarks_table()
422 if (clock_ranges) { in smu_v13_0_5_set_watermarks_table()
423 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in smu_v13_0_5_set_watermarks_table()
424 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in smu_v13_0_5_set_watermarks_table()
427 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in smu_v13_0_5_set_watermarks_table()
429 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in smu_v13_0_5_set_watermarks_table()
431 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in smu_v13_0_5_set_watermarks_table()
433 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in smu_v13_0_5_set_watermarks_table()
435 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in smu_v13_0_5_set_watermarks_table()
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| H A D | smu_v13_0_4_ppt.c | 670 struct pp_smu_wm_range_sets *clock_ranges) in smu_v13_0_4_set_watermarks_table() argument
676 if (!table || !clock_ranges) in smu_v13_0_4_set_watermarks_table()
679 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in smu_v13_0_4_set_watermarks_table()
680 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in smu_v13_0_4_set_watermarks_table()
683 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in smu_v13_0_4_set_watermarks_table()
685 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in smu_v13_0_4_set_watermarks_table()
687 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in smu_v13_0_4_set_watermarks_table()
689 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in smu_v13_0_4_set_watermarks_table()
691 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in smu_v13_0_4_set_watermarks_table()
694 clock_ranges->reader_wm_sets[i].wm_inst; in smu_v13_0_4_set_watermarks_table()
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| H A D | yellow_carp_ppt.c | 504 struct pp_smu_wm_range_sets *clock_ranges) in yellow_carp_set_watermarks_table() argument
510 if (!table || !clock_ranges) in yellow_carp_set_watermarks_table()
513 if (clock_ranges) { in yellow_carp_set_watermarks_table()
514 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in yellow_carp_set_watermarks_table()
515 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in yellow_carp_set_watermarks_table()
518 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in yellow_carp_set_watermarks_table()
520 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in yellow_carp_set_watermarks_table()
522 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in yellow_carp_set_watermarks_table()
524 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in yellow_carp_set_watermarks_table()
526 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in yellow_carp_set_watermarks_table()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| H A D | renoir_ppt.c | 1055 struct pp_smu_wm_range_sets *clock_ranges) in renoir_set_watermarks_table() argument
1061 if (clock_ranges) { in renoir_set_watermarks_table()
1062 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in renoir_set_watermarks_table()
1063 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in renoir_set_watermarks_table()
1067 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in renoir_set_watermarks_table()
1069 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in renoir_set_watermarks_table()
1071 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in renoir_set_watermarks_table()
1073 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in renoir_set_watermarks_table()
1075 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in renoir_set_watermarks_table()
1078 clock_ranges->reader_wm_sets[i].wm_inst; in renoir_set_watermarks_table()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu15/ |
| H A D | smu_v15_0_0_ppt.c | 574 struct pp_smu_wm_range_sets *clock_ranges) in smu_v15_0_0_set_watermarks_table() argument
580 if (!table || !clock_ranges) in smu_v15_0_0_set_watermarks_table()
583 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in smu_v15_0_0_set_watermarks_table()
584 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in smu_v15_0_0_set_watermarks_table()
587 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in smu_v15_0_0_set_watermarks_table()
589 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in smu_v15_0_0_set_watermarks_table()
591 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in smu_v15_0_0_set_watermarks_table()
593 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in smu_v15_0_0_set_watermarks_table()
595 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in smu_v15_0_0_set_watermarks_table()
598 clock_ranges->reader_wm_sets[i].wm_inst; in smu_v15_0_0_set_watermarks_table()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| H A D | smu_v14_0_0_ppt.c | 487 struct pp_smu_wm_range_sets *clock_ranges) in smu_v14_0_0_set_watermarks_table() argument
493 if (!table || !clock_ranges) in smu_v14_0_0_set_watermarks_table()
496 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in smu_v14_0_0_set_watermarks_table()
497 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in smu_v14_0_0_set_watermarks_table()
500 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in smu_v14_0_0_set_watermarks_table()
502 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in smu_v14_0_0_set_watermarks_table()
504 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in smu_v14_0_0_set_watermarks_table()
506 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in smu_v14_0_0_set_watermarks_table()
508 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in smu_v14_0_0_set_watermarks_table()
511 clock_ranges->reader_wm_sets[i].wm_inst; in smu_v14_0_0_set_watermarks_table()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | vangogh_ppt.c | 1598 struct pp_smu_wm_range_sets *clock_ranges) in vangogh_set_watermarks_table() argument
1604 if (!table || !clock_ranges) in vangogh_set_watermarks_table()
1607 if (clock_ranges) { in vangogh_set_watermarks_table()
1608 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in vangogh_set_watermarks_table()
1609 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in vangogh_set_watermarks_table()
1612 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in vangogh_set_watermarks_table()
1614 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in vangogh_set_watermarks_table()
1616 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in vangogh_set_watermarks_table()
1618 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in vangogh_set_watermarks_table()
1620 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in vangogh_set_watermarks_table()
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| H A D | navi10_ppt.c | 1918 struct pp_smu_wm_range_sets *clock_ranges) in navi10_set_watermarks_table() argument
1924 if (clock_ranges) { in navi10_set_watermarks_table()
1925 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in navi10_set_watermarks_table()
1926 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in navi10_set_watermarks_table()
1929 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in navi10_set_watermarks_table()
1931 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in navi10_set_watermarks_table()
1933 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in navi10_set_watermarks_table()
1935 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in navi10_set_watermarks_table()
1937 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in navi10_set_watermarks_table()
1940 clock_ranges->reader_wm_sets[i].wm_inst; in navi10_set_watermarks_table()
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| H A D | sienna_cichlid_ppt.c | 1834 struct pp_smu_wm_range_sets *clock_ranges) in sienna_cichlid_set_watermarks_table() argument
1840 if (clock_ranges) { in sienna_cichlid_set_watermarks_table()
1841 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in sienna_cichlid_set_watermarks_table()
1842 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in sienna_cichlid_set_watermarks_table()
1845 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in sienna_cichlid_set_watermarks_table()
1847 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in sienna_cichlid_set_watermarks_table()
1849 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in sienna_cichlid_set_watermarks_table()
1851 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in sienna_cichlid_set_watermarks_table()
1853 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in sienna_cichlid_set_watermarks_table()
1856 clock_ranges->reader_wm_sets[i].wm_inst; in sienna_cichlid_set_watermarks_table()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/ |
| H A D | amd_powerplay.c | 1121 void *clock_ranges) in pp_set_watermarks_for_clocks_ranges() argument
1125 if (!hwmgr || !hwmgr->pm_en || !clock_ranges) in pp_set_watermarks_for_clocks_ranges()
1129 clock_ranges); in pp_set_watermarks_for_clocks_ranges()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu10_hwmgr.c | 1371 void *clock_ranges) in smu10_set_watermarks_for_clocks_ranges() argument
1374 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; in smu10_set_watermarks_for_clocks_ranges()
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| H A D | vega12_hwmgr.c | 2008 void *clock_ranges) in vega12_set_watermarks_for_clocks_ranges() argument
2012 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; in vega12_set_watermarks_for_clocks_ranges()
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| H A D | vega20_hwmgr.c | 2949 void *clock_ranges) in vega20_set_watermarks_for_clocks_ranges() argument
2953 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; in vega20_set_watermarks_for_clocks_ranges()
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| /linux/drivers/gpu/drm/amd/include/ |
| H A D | kgd_pp_interface.h | 491 void *clock_ranges);
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| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/ |
| H A D | amdgpu_smu.h | 1020 struct pp_smu_wm_range_sets *clock_ranges);
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| /linux/drivers/gpu/drm/amd/pm/swsmu/ |
| H A D | amdgpu_smu.c | 2711 struct pp_smu_wm_range_sets *clock_ranges) in smu_set_watermarks_for_clock_ranges() argument
2721 return smu_set_watermarks_table(smu, clock_ranges); in smu_set_watermarks_for_clock_ranges()
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