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Searched refs:clk_type (Results 1 – 25 of 46) sorted by relevance

12

/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_0_ppt.c637 enum smu_clk_type clk_type, in smu_v14_0_1_get_dpm_freq_by_index() argument
643 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v14_0_1_get_dpm_freq_by_index()
646 switch (clk_type) { in smu_v14_0_1_get_dpm_freq_by_index()
691 enum smu_clk_type clk_type, in smu_v14_0_0_get_dpm_freq_by_index() argument
697 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v14_0_0_get_dpm_freq_by_index()
700 switch (clk_type) { in smu_v14_0_0_get_dpm_freq_by_index()
735 enum smu_clk_type clk_type, in smu_v14_0_common_get_dpm_freq_by_index() argument
740 smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq); in smu_v14_0_common_get_dpm_freq_by_index()
741 else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1) in smu_v14_0_common_get_dpm_freq_by_index()
742 smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq); in smu_v14_0_common_get_dpm_freq_by_index()
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H A Dsmu_v14_0.c1092 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v14_0_get_dpm_ultimate_freq() argument
1099 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v14_0_get_dpm_ultimate_freq()
1100 switch (clk_type) { in smu_v14_0_get_dpm_ultimate_freq()
1128 clk_type); in smu_v14_0_get_dpm_ultimate_freq()
1161 enum smu_clk_type clk_type, in smu_v14_0_set_soft_freq_limited_range() argument
1169 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v14_0_set_soft_freq_limited_range()
1174 clk_type); in smu_v14_0_set_soft_freq_limited_range()
1206 enum smu_clk_type clk_type, in smu_v14_0_set_hard_freq_limited_range() argument
1216 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v14_0_set_hard_freq_limited_range()
1221 clk_type); in smu_v14_0_set_hard_freq_limited_range()
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H A Dsmu_v14_0_2_ppt.c466 dpm_table->clk_type = SMU_SOCCLK; in smu_v14_0_2_set_default_dpm_table()
481 dpm_table->clk_type = SMU_GFXCLK; in smu_v14_0_2_set_default_dpm_table()
512 dpm_table->clk_type = SMU_UCLK; in smu_v14_0_2_set_default_dpm_table()
527 dpm_table->clk_type = SMU_FCLK; in smu_v14_0_2_set_default_dpm_table()
542 dpm_table->clk_type = SMU_VCLK; in smu_v14_0_2_set_default_dpm_table()
557 dpm_table->clk_type = SMU_DCLK; in smu_v14_0_2_set_default_dpm_table()
572 dpm_table->clk_type = SMU_DCEFCLK; in smu_v14_0_2_set_default_dpm_table()
741 enum smu_clk_type clk_type, in smu_v14_0_2_get_dpm_ultimate_freq() argument
749 switch (clk_type) { in smu_v14_0_2_get_dpm_ultimate_freq()
876 enum smu_clk_type clk_type, in smu_v14_0_2_get_current_clk_freq_by_table() argument
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c601 enum smu_clk_type clk_type, in smu_v13_0_5_get_current_clk_freq() argument
606 switch (clk_type) { in smu_v13_0_5_get_current_clk_freq()
632 enum smu_clk_type clk_type, in smu_v13_0_5_get_dpm_level_count() argument
637 switch (clk_type) { in smu_v13_0_5_get_dpm_level_count()
661 enum smu_clk_type clk_type, in smu_v13_0_5_get_dpm_freq_by_index() argument
667 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_5_get_dpm_freq_by_index()
670 switch (clk_type) { in smu_v13_0_5_get_dpm_freq_by_index()
705 enum smu_clk_type clk_type) in smu_v13_0_5_clk_dpm_is_enabled() argument
709 switch (clk_type) { in smu_v13_0_5_clk_dpm_is_enabled()
734 enum smu_clk_type clk_type, in smu_v13_0_5_get_dpm_ultimate_freq() argument
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H A Dsmu_v13_0_4_ppt.c394 enum smu_clk_type clk_type, in smu_v13_0_4_get_current_clk_freq() argument
399 switch (clk_type) { in smu_v13_0_4_get_current_clk_freq()
430 enum smu_clk_type clk_type, in smu_v13_0_4_get_dpm_freq_by_index() argument
436 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_4_get_dpm_freq_by_index()
439 switch (clk_type) { in smu_v13_0_4_get_dpm_freq_by_index()
474 enum smu_clk_type clk_type, in smu_v13_0_4_get_dpm_level_count() argument
479 switch (clk_type) { in smu_v13_0_4_get_dpm_level_count()
503 enum smu_clk_type clk_type, char *buf, in smu_v13_0_4_emit_clk_levels() argument
510 switch (clk_type) { in smu_v13_0_4_emit_clk_levels()
529 ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value); in smu_v13_0_4_emit_clk_levels()
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H A Dyellow_carp_ppt.c732 enum smu_clk_type clk_type, in yellow_carp_get_current_clk_freq() argument
737 switch (clk_type) { in yellow_carp_get_current_clk_freq()
766 enum smu_clk_type clk_type, in yellow_carp_get_dpm_level_count() argument
771 switch (clk_type) { in yellow_carp_get_dpm_level_count()
795 enum smu_clk_type clk_type, in yellow_carp_get_dpm_freq_by_index() argument
801 if (!clk_table || clk_type >= SMU_CLK_COUNT) in yellow_carp_get_dpm_freq_by_index()
804 switch (clk_type) { in yellow_carp_get_dpm_freq_by_index()
839 enum smu_clk_type clk_type) in yellow_carp_clk_dpm_is_enabled() argument
843 switch (clk_type) { in yellow_carp_clk_dpm_is_enabled()
868 enum smu_clk_type clk_type, in yellow_carp_get_dpm_ultimate_freq() argument
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H A Dsmu_v13_0.c1482 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v13_0_get_dpm_ultimate_freq() argument
1489 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v13_0_get_dpm_ultimate_freq()
1490 ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit); in smu_v13_0_get_dpm_ultimate_freq()
1505 clk_type); in smu_v13_0_get_dpm_ultimate_freq()
1538 enum smu_clk_type clk_type, in smu_v13_0_set_soft_freq_limited_range() argument
1546 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v13_0_set_soft_freq_limited_range()
1551 clk_type); in smu_v13_0_set_soft_freq_limited_range()
1785 enum smu_clk_type clk_type, in smu_v13_0_get_boot_freq_by_index() argument
1790 switch (clk_type) { in smu_v13_0_get_boot_freq_by_index()
1819 enum smu_clk_type clk_type, uint16_t level, in smu_v13_0_get_dpm_freq_by_index() argument
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H A Dsmu_v13_0_7_ppt.c596 dpm_table->clk_type = SMU_SOCCLK; in smu_v13_0_7_set_default_dpm_table()
611 dpm_table->clk_type = SMU_GFXCLK; in smu_v13_0_7_set_default_dpm_table()
633 dpm_table->clk_type = SMU_UCLK; in smu_v13_0_7_set_default_dpm_table()
648 dpm_table->clk_type = SMU_FCLK; in smu_v13_0_7_set_default_dpm_table()
663 dpm_table->clk_type = SMU_VCLK; in smu_v13_0_7_set_default_dpm_table()
678 dpm_table->clk_type = SMU_DCLK; in smu_v13_0_7_set_default_dpm_table()
693 dpm_table->clk_type = SMU_DCEFCLK; in smu_v13_0_7_set_default_dpm_table()
865 enum smu_clk_type clk_type, in smu_v13_0_7_get_dpm_ultimate_freq() argument
873 switch (clk_type) { in smu_v13_0_7_get_dpm_ultimate_freq()
1001 enum smu_clk_type clk_type, in smu_v13_0_7_get_current_clk_freq_by_table() argument
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0_0_ppt.c715 enum smu_clk_type clk_type, in smu_v15_0_0_get_dpm_freq_by_index() argument
721 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v15_0_0_get_dpm_freq_by_index()
724 switch (clk_type) { in smu_v15_0_0_get_dpm_freq_by_index()
759 enum smu_clk_type clk_type, in smu_v15_0_common_get_dpm_freq_by_index() argument
763 smu_v15_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq); in smu_v15_0_common_get_dpm_freq_by_index()
769 enum smu_clk_type clk_type) in smu_v15_0_0_clk_dpm_is_enabled() argument
773 switch (clk_type) { in smu_v15_0_0_clk_dpm_is_enabled()
800 enum smu_clk_type clk_type, in smu_v15_0_0_get_dpm_ultimate_freq() argument
809 if (!smu_v15_0_0_clk_dpm_is_enabled(smu, clk_type)) { in smu_v15_0_0_get_dpm_ultimate_freq()
810 switch (clk_type) { in smu_v15_0_0_get_dpm_ultimate_freq()
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H A Dsmu_v15_0.c976 int smu_v15_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v15_0_get_dpm_ultimate_freq() argument
983 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v15_0_get_dpm_ultimate_freq()
984 switch (clk_type) { in smu_v15_0_get_dpm_ultimate_freq()
1012 clk_type); in smu_v15_0_get_dpm_ultimate_freq()
1045 enum smu_clk_type clk_type, in smu_v15_0_set_soft_freq_limited_range() argument
1053 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v15_0_set_soft_freq_limited_range()
1058 clk_type); in smu_v15_0_set_soft_freq_limited_range()
1089 enum smu_clk_type clk_type, in smu_v15_0_set_hard_freq_limited_range() argument
1099 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v15_0_set_hard_freq_limited_range()
1104 clk_type); in smu_v15_0_set_hard_freq_limited_range()
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c195 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, in renoir_get_dpm_clk_limited() argument
200 if (!clk_table || clk_type >= SMU_CLK_COUNT) in renoir_get_dpm_clk_limited()
203 switch (clk_type) { in renoir_get_dpm_clk_limited()
274 enum smu_clk_type clk_type, in renoir_get_dpm_ultimate_freq() argument
282 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in renoir_get_dpm_ultimate_freq()
283 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
318 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
330 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); in renoir_get_dpm_ultimate_freq()
335 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max); in renoir_get_dpm_ultimate_freq()
346 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dvangogh_ppt.c523 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, in vangogh_get_dpm_clk_limited() argument
528 if (!clk_table || clk_type >= SMU_CLK_COUNT) in vangogh_get_dpm_clk_limited()
531 switch (clk_type) { in vangogh_get_dpm_clk_limited()
567 enum smu_clk_type clk_type, char *buf, in vangogh_emit_legacy_clk_levels() argument
583 switch (clk_type) { in vangogh_emit_legacy_clk_levels()
638 switch (clk_type) { in vangogh_emit_legacy_clk_levels()
645 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; in vangogh_emit_legacy_clk_levels()
646 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value); in vangogh_emit_legacy_clk_levels()
670 enum smu_clk_type clk_type, char *buf, in vangogh_emit_clk_levels() argument
686 switch (clk_type) { in vangogh_emit_clk_levels()
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H A Dcyan_skillfish_ppt.c263 enum smu_clk_type clk_type, in cyan_skillfish_get_current_clk_freq() argument
268 switch (clk_type) { in cyan_skillfish_get_current_clk_freq()
294 enum smu_clk_type clk_type, char *buf, in cyan_skillfish_emit_clk_levels() argument
301 switch (clk_type) { in cyan_skillfish_emit_clk_levels()
328 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_emit_clk_levels()
335 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_emit_clk_levels()
542 enum smu_clk_type clk_type, in cyan_skillfish_get_dpm_ultimate_freq() argument
549 switch (clk_type) { in cyan_skillfish_get_dpm_ultimate_freq()
556 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &low); in cyan_skillfish_get_dpm_ultimate_freq()
H A Dsmu_v11_0.c1062 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu_v11_0_display_clock_voltage_request() local
1069 switch (clk_type) { in smu_v11_0_display_clock_voltage_request()
1715 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v11_0_get_dpm_ultimate_freq() argument
1722 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v11_0_get_dpm_ultimate_freq()
1723 switch (clk_type) { in smu_v11_0_get_dpm_ultimate_freq()
1751 clk_type); in smu_v11_0_get_dpm_ultimate_freq()
1775 enum smu_clk_type clk_type, in smu_v11_0_set_soft_freq_limited_range() argument
1783 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v11_0_set_soft_freq_limited_range()
1788 clk_type); in smu_v11_0_set_soft_freq_limited_range()
1819 enum smu_clk_type clk_type, in smu_v11_0_set_hard_freq_limited_range() argument
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H A Dnavi10_ppt.c970 dpm_table->clk_type = SMU_SOCCLK; in navi10_set_default_dpm_table()
987 dpm_table->clk_type = SMU_GFXCLK; in navi10_set_default_dpm_table()
1004 dpm_table->clk_type = SMU_UCLK; in navi10_set_default_dpm_table()
1021 dpm_table->clk_type = SMU_VCLK; in navi10_set_default_dpm_table()
1038 dpm_table->clk_type = SMU_DCLK; in navi10_set_default_dpm_table()
1055 dpm_table->clk_type = SMU_DCEFCLK; in navi10_set_default_dpm_table()
1072 dpm_table->clk_type = SMU_PIXCLK; in navi10_set_default_dpm_table()
1089 dpm_table->clk_type = SMU_DISPCLK; in navi10_set_default_dpm_table()
1106 dpm_table->clk_type = SMU_PHYCLK; in navi10_set_default_dpm_table()
1170 enum smu_clk_type clk_type, in navi10_get_current_clk_freq_by_table() argument
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H A Dsienna_cichlid_ppt.c965 dpm_table->clk_type = SMU_SOCCLK; in sienna_cichlid_set_default_dpm_table()
983 dpm_table->clk_type = SMU_GFXCLK; in sienna_cichlid_set_default_dpm_table()
1000 dpm_table->clk_type = SMU_UCLK; in sienna_cichlid_set_default_dpm_table()
1017 dpm_table->clk_type = SMU_FCLK; in sienna_cichlid_set_default_dpm_table()
1038 dpm_table->clk_type = i ? SMU_VCLK1 : SMU_VCLK; in sienna_cichlid_set_default_dpm_table()
1060 dpm_table->clk_type = i ? SMU_DCLK1 : SMU_DCLK; in sienna_cichlid_set_default_dpm_table()
1079 dpm_table->clk_type = SMU_DCEFCLK; in sienna_cichlid_set_default_dpm_table()
1096 dpm_table->clk_type = SMU_PIXCLK; in sienna_cichlid_set_default_dpm_table()
1113 dpm_table->clk_type = SMU_DISPCLK; in sienna_cichlid_set_default_dpm_table()
1130 dpm_table->clk_type = SMU_PHYCLK; in sienna_cichlid_set_default_dpm_table()
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/linux/drivers/clk/imx/
H A Dclk-scu.h36 int num_parents, u32 rsrc_id, u8 clk_type);
40 u32 rsrc_id, u8 clk_type);
54 u8 clk_type) in imx_clk_scu() argument
56 return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type); in imx_clk_scu()
60 int num_parents, u32 rsrc_id, u8 clk_type) in imx_clk_scu2() argument
62 return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type); in imx_clk_scu2()
H A Dclk-scu.c33 u8 clk_type; member
52 u8 clk_type; member
253 msg.data.req.clk = clk->clk_type; in clk_scu_recalc_rate()
326 msg.clk = clk->clk_type; in clk_scu_set_rate()
344 msg.data.req.clk = clk->clk_type; in clk_scu_get_parent()
371 msg.clk = clk->clk_type; in clk_scu_set_parent()
416 clk->clk_type, true, false); in clk_scu_prepare()
431 clk->clk_type, false, false); in clk_scu_unprepare()
463 u32 rsrc_id, u8 clk_type) in __imx_clk_scu() argument
475 clk->clk_type = clk_type; in __imx_clk_scu()
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/linux/drivers/gpu/drm/amd/pm/swsmu/
H A Damdgpu_smu.c64 enum smu_clk_type clk_type,
146 enum smu_clk_type clk_type; in smu_set_soft_freq_range() local
149 clk_type = smu_convert_to_smuclk(type); in smu_set_soft_freq_range()
150 if (clk_type == SMU_CLK_COUNT) in smu_set_soft_freq_range()
155 clk_type, in smu_set_soft_freq_range()
164 enum smu_clk_type clk_type, in smu_get_dpm_freq_range() argument
175 clk_type, in smu_get_dpm_freq_range()
524 enum smu_clk_type clk_type; in smu_restore_dpm_user_profile() local
526 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { in smu_restore_dpm_user_profile()
531 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && in smu_restore_dpm_user_profile()
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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Dsmu_v15_0.h183 int smu_v15_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
186 int smu_v15_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
190 enum smu_clk_type clk_type,
201 enum smu_clk_type clk_type,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr.h115 unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);
/linux/drivers/phy/
H A Dphy-xgene.c535 enum clk_type_t clk_type; /* Input clock selection */ member
706 enum clk_type_t clk_type) in xgene_phy_cfg_cmu_clk_type() argument
719 if (clk_type == CLK_EXT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
729 } else if (clk_type == CLK_INT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
739 } else if (clk_type == CLK_INT_SING) { in xgene_phy_cfg_cmu_clk_type()
760 enum clk_type_t clk_type) in xgene_phy_sata_cfg_cmu_core() argument
806 if (clk_type == CLK_EXT_DIFF) in xgene_phy_sata_cfg_cmu_core()
1137 enum clk_type_t clk_type) in xgene_phy_cal_rdy_chk() argument
1237 enum clk_type_t clk_type) in xgene_phy_pdwn_force_vco() argument
1254 enum clk_type_t clk_type, int ssc_enable) in xgene_phy_hw_init_sata() argument
[all …]
/linux/drivers/input/
H A Devdev.c49 enum input_clock_type clk_type; member
146 struct timespec64 ts = ktime_to_timespec64(ev_time[client->clk_type]); in __evdev_queue_syn_dropped()
177 enum input_clock_type clk_type; in evdev_set_clk_type() local
182 clk_type = INPUT_CLK_REAL; in evdev_set_clk_type()
185 clk_type = INPUT_CLK_MONO; in evdev_set_clk_type()
188 clk_type = INPUT_CLK_BOOT; in evdev_set_clk_type()
194 if (client->clk_type != clk_type) { in evdev_set_clk_type()
195 client->clk_type = clk_type; in evdev_set_clk_type()
256 ts = ktime_to_timespec64(ev_time[client->clk_type]); in evdev_pass_values()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
H A Ddce120_clk_mgr.c98 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK; in dce12_update_clocks()
113 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK; in dce12_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h103 enum clk_type { enum
342 unsigned int (*get_max_clock_khz)(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);

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