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Searched refs:clk_type (Results 1 – 25 of 28) sorted by relevance

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/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_4_ppt.c389 enum smu_clk_type clk_type, in smu_v13_0_4_get_current_clk_freq() argument
394 switch (clk_type) { in smu_v13_0_4_get_current_clk_freq()
425 enum smu_clk_type clk_type, in smu_v13_0_4_get_dpm_freq_by_index() argument
431 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_4_get_dpm_freq_by_index()
434 switch (clk_type) { in smu_v13_0_4_get_dpm_freq_by_index()
469 enum smu_clk_type clk_type, in smu_v13_0_4_get_dpm_level_count() argument
474 switch (clk_type) { in smu_v13_0_4_get_dpm_level_count()
498 enum smu_clk_type clk_type, char *buf) in smu_v13_0_4_print_clk_levels() argument
506 switch (clk_type) { in smu_v13_0_4_print_clk_levels()
525 ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value); in smu_v13_0_4_print_clk_levels()
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H A Dsmu_v13_0.c1483 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v13_0_get_dpm_ultimate_freq() argument
1490 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v13_0_get_dpm_ultimate_freq()
1491 ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit); in smu_v13_0_get_dpm_ultimate_freq()
1506 clk_type); in smu_v13_0_get_dpm_ultimate_freq()
1539 enum smu_clk_type clk_type, in smu_v13_0_set_soft_freq_limited_range() argument
1547 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v13_0_set_soft_freq_limited_range()
1552 clk_type); in smu_v13_0_set_soft_freq_limited_range()
1791 enum smu_clk_type clk_type, in smu_v13_0_get_boot_freq_by_index() argument
1796 switch (clk_type) { in smu_v13_0_get_boot_freq_by_index()
1825 enum smu_clk_type clk_type, uint16_t level, in smu_v13_0_get_dpm_freq_by_index() argument
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H A Dsmu_v13_0_6_ppt.c252 enum smu_clk_type clk_type; member
881 enum smu_clk_type clk_type, in smu_v13_0_6_get_dpm_ultimate_freq() argument
894 switch (clk_type) { in smu_v13_0_6_get_dpm_ultimate_freq()
931 if (!(clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)) { in smu_v13_0_6_get_dpm_ultimate_freq()
933 smu, CMN2ASIC_MAPPING_CLK, clk_type); in smu_v13_0_6_get_dpm_ultimate_freq()
942 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK) in smu_v13_0_6_get_dpm_ultimate_freq()
953 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK) in smu_v13_0_6_get_dpm_ultimate_freq()
966 enum smu_clk_type clk_type, in smu_v13_0_6_get_dpm_level_count() argument
971 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, levels); in smu_v13_0_6_get_dpm_level_count()
1056 smu, dpm_map[j].clk_type, &levels); in smu_v13_0_6_set_default_dpm_table()
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H A Daldebaran_ppt.c346 enum smu_clk_type clk_type, in aldebaran_get_dpm_ultimate_freq() argument
354 switch (clk_type) { in aldebaran_get_dpm_ultimate_freq()
394 return smu_v13_0_get_dpm_ultimate_freq(smu, clk_type, min, max); in aldebaran_get_dpm_ultimate_freq()
762 enum smu_clk_type clk_type, in aldebaran_get_current_clk_freq_by_table() argument
773 clk_type); in aldebaran_get_current_clk_freq_by_table()
1360 enum smu_clk_type clk_type, in aldebaran_set_soft_freq_limited_range() argument
1373 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) in aldebaran_set_soft_freq_limited_range()
/linux/drivers/gpu/drm/amd/pm/swsmu/
H A Damdgpu_smu.c63 enum smu_clk_type clk_type,
145 enum smu_clk_type clk_type; in smu_set_soft_freq_range() local
148 clk_type = smu_convert_to_smuclk(type); in smu_set_soft_freq_range()
149 if (clk_type == SMU_CLK_COUNT) in smu_set_soft_freq_range()
154 clk_type, in smu_set_soft_freq_range()
163 enum smu_clk_type clk_type, in smu_get_dpm_freq_range() argument
174 clk_type, in smu_get_dpm_freq_range()
520 enum smu_clk_type clk_type; in smu_restore_dpm_user_profile() local
522 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { in smu_restore_dpm_user_profile()
527 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && in smu_restore_dpm_user_profile()
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H A Dsmu_cmn.h107 enum smu_clk_type clk_type);
H A Dsmu_cmn.c646 enum smu_clk_type clk_type) in smu_cmn_clk_dpm_is_enabled() argument
650 switch (clk_type) { in smu_cmn_clk_dpm_is_enabled()
/linux/drivers/clk/imx/
H A Dclk-scu.h34 int num_parents, u32 rsrc_id, u8 clk_type);
38 u32 rsrc_id, u8 clk_type);
52 u8 clk_type) in imx_clk_scu() argument
54 return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type); in imx_clk_scu()
58 int num_parents, u32 rsrc_id, u8 clk_type) in imx_clk_scu2() argument
60 return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type); in imx_clk_scu2()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c111 enum dm_pp_clock_type clk_type, in get_default_clock_levels() argument
120 switch (clk_type) { in get_default_clock_levels()
294 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type() argument
303 dc_to_pp_clock_type(clk_type), &pp_clks)) { in dm_pp_get_clock_levels_by_type()
305 get_default_clock_levels(clk_type, dc_clks); in dm_pp_get_clock_levels_by_type()
309 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type); in dm_pp_get_clock_levels_by_type()
332 if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) { in dm_pp_get_clock_levels_by_type()
345 } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) { in dm_pp_get_clock_levels_by_type()
361 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type_with_latency() argument
369 dc_to_pp_clock_type(clk_type), in dm_pp_get_clock_levels_by_type_with_latency()
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dcyan_skillfish_ppt.c260 enum smu_clk_type clk_type, in cyan_skillfish_get_current_clk_freq() argument
265 switch (clk_type) { in cyan_skillfish_get_current_clk_freq()
291 enum smu_clk_type clk_type, in cyan_skillfish_print_clk_levels() argument
300 switch (clk_type) { in cyan_skillfish_print_clk_levels()
327 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_print_clk_levels()
334 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_print_clk_levels()
536 enum smu_clk_type clk_type, in cyan_skillfish_get_dpm_ultimate_freq() argument
543 switch (clk_type) { in cyan_skillfish_get_dpm_ultimate_freq()
550 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &low); in cyan_skillfish_get_dpm_ultimate_freq()
H A Dsmu_v11_0.c1057 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu_v11_0_display_clock_voltage_request() local
1064 switch (clk_type) { in smu_v11_0_display_clock_voltage_request()
1710 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v11_0_get_dpm_ultimate_freq() argument
1717 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v11_0_get_dpm_ultimate_freq()
1718 switch (clk_type) { in smu_v11_0_get_dpm_ultimate_freq()
1746 clk_type); in smu_v11_0_get_dpm_ultimate_freq()
1770 enum smu_clk_type clk_type, in smu_v11_0_set_soft_freq_limited_range() argument
1778 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v11_0_set_soft_freq_limited_range()
1783 clk_type); in smu_v11_0_set_soft_freq_limited_range()
1814 enum smu_clk_type clk_type, in smu_v11_0_set_hard_freq_limited_range() argument
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0.c1094 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v14_0_get_dpm_ultimate_freq() argument
1101 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v14_0_get_dpm_ultimate_freq()
1102 switch (clk_type) { in smu_v14_0_get_dpm_ultimate_freq()
1130 clk_type); in smu_v14_0_get_dpm_ultimate_freq()
1163 enum smu_clk_type clk_type, in smu_v14_0_set_soft_freq_limited_range() argument
1171 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v14_0_set_soft_freq_limited_range()
1176 clk_type); in smu_v14_0_set_soft_freq_limited_range()
1207 enum smu_clk_type clk_type, in smu_v14_0_set_hard_freq_limited_range() argument
1217 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v14_0_set_hard_freq_limited_range()
1222 clk_type); in smu_v14_0_set_hard_freq_limited_range()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr.h115 unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);
H A Ddcn401_clk_mgr.c1503 unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type) in dcn401_get_max_clock_khz() argument
1509 switch (clk_type) { in dcn401_get_max_clock_khz()
/linux/drivers/input/
H A Devdev.c49 enum input_clock_type clk_type; member
146 struct timespec64 ts = ktime_to_timespec64(ev_time[client->clk_type]); in __evdev_queue_syn_dropped()
177 enum input_clock_type clk_type; in evdev_set_clk_type() local
182 clk_type = INPUT_CLK_REAL; in evdev_set_clk_type()
185 clk_type = INPUT_CLK_MONO; in evdev_set_clk_type()
188 clk_type = INPUT_CLK_BOOT; in evdev_set_clk_type()
194 if (client->clk_type != clk_type) { in evdev_set_clk_type()
195 client->clk_type = clk_type; in evdev_set_clk_type()
256 ts = ktime_to_timespec64(ev_time[client->clk_type]); in evdev_pass_values()
/linux/drivers/phy/
H A Dphy-xgene.c535 enum clk_type_t clk_type; /* Input clock selection */ member
706 enum clk_type_t clk_type) in xgene_phy_cfg_cmu_clk_type() argument
719 if (clk_type == CLK_EXT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
729 } else if (clk_type == CLK_INT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
739 } else if (clk_type == CLK_INT_SING) { in xgene_phy_cfg_cmu_clk_type()
760 enum clk_type_t clk_type) in xgene_phy_sata_cfg_cmu_core() argument
806 if (clk_type == CLK_EXT_DIFF) in xgene_phy_sata_cfg_cmu_core()
1137 enum clk_type_t clk_type) in xgene_phy_cal_rdy_chk() argument
1237 enum clk_type_t clk_type) in xgene_phy_pdwn_force_vco() argument
1254 enum clk_type_t clk_type, int ssc_enable) in xgene_phy_hw_init_sata() argument
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
H A Ddce120_clk_mgr.c98 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK; in dce12_update_clocks()
113 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK; in dce12_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h103 enum clk_type { enum
342 unsigned int (*get_max_clock_khz)(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Damdgpu_smu.h672 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
685 …int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset…
693 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
716 enum smu_clk_type clk_type,
1269 …int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, u…
1275 …int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t m…
1642 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1645 int smu_set_soft_freq_range(struct smu_context *smu, enum pp_clock_type clk_type,
/linux/drivers/gpu/drm/amd/amdgpu/
H A Datombios_crtc.h41 u32 freq, u8 clk_type, u8 clk_src);
H A Datombios_crtc.c526 u32 freq, u8 clk_type, u8 clk_src) in amdgpu_atombios_crtc_set_dce_clock() argument
545 args.v2_1.asParam.ucDCEClkType = clk_type; in amdgpu_atombios_crtc_set_dce_clock()
/linux/drivers/clk/zynqmp/
H A Dclkc.c43 enum clk_type { enum
74 enum clk_type type;
/linux/drivers/media/dvb-frontends/
H A Dmxl5xx.c1382 u32 clk_type = 0; in config_ts() local
1465 clk_type = 1; in config_ts()
1472 clk_type); in config_ts()
1474 update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type); in config_ts()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clk_mgr.c767 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK; in dce12_update_clocks()
782 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK; in dce12_update_clocks()
/linux/sound/soc/codecs/
H A Dwcd9335.c324 enum wcd_clock_type clk_type; member
4078 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) || in wcd9335_enable_mclk()
4079 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) { in wcd9335_enable_mclk()
4081 wcd->clk_type); in wcd9335_enable_mclk()
4110 wcd->clk_type = WCD_CLK_MCLK; in wcd9335_enable_mclk()
4126 wcd->clk_type = WCD_CLK_RCO; in wcd9335_disable_mclk()
4131 wcd->clk_type = WCD_CLK_OFF; in wcd9335_disable_mclk()

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