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Searched refs:clk_type (Results 1 – 25 of 30) sorted by relevance

12

/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_0_ppt.c640 enum smu_clk_type clk_type, in smu_v14_0_1_get_dpm_freq_by_index() argument
646 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v14_0_1_get_dpm_freq_by_index()
649 switch (clk_type) { in smu_v14_0_1_get_dpm_freq_by_index()
694 enum smu_clk_type clk_type, in smu_v14_0_0_get_dpm_freq_by_index() argument
700 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v14_0_0_get_dpm_freq_by_index()
703 switch (clk_type) { in smu_v14_0_0_get_dpm_freq_by_index()
738 enum smu_clk_type clk_type, in smu_v14_0_common_get_dpm_freq_by_index() argument
743 smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq); in smu_v14_0_common_get_dpm_freq_by_index()
744 else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1) in smu_v14_0_common_get_dpm_freq_by_index()
745 smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq); in smu_v14_0_common_get_dpm_freq_by_index()
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H A Dsmu_v14_0.c1031 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v14_0_get_dpm_ultimate_freq() argument
1038 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v14_0_get_dpm_ultimate_freq()
1039 switch (clk_type) { in smu_v14_0_get_dpm_ultimate_freq()
1067 clk_type); in smu_v14_0_get_dpm_ultimate_freq()
1100 enum smu_clk_type clk_type, in smu_v14_0_set_soft_freq_limited_range() argument
1108 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v14_0_set_soft_freq_limited_range()
1113 clk_type); in smu_v14_0_set_soft_freq_limited_range()
1145 enum smu_clk_type clk_type, in smu_v14_0_set_hard_freq_limited_range() argument
1155 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v14_0_set_hard_freq_limited_range()
1160 clk_type); in smu_v14_0_set_hard_freq_limited_range()
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H A Dsmu_v14_0_2_ppt.c472 dpm_table->clk_type = SMU_SOCCLK; in smu_v14_0_2_set_default_dpm_table()
487 dpm_table->clk_type = SMU_GFXCLK; in smu_v14_0_2_set_default_dpm_table()
518 dpm_table->clk_type = SMU_UCLK; in smu_v14_0_2_set_default_dpm_table()
533 dpm_table->clk_type = SMU_FCLK; in smu_v14_0_2_set_default_dpm_table()
548 dpm_table->clk_type = SMU_VCLK; in smu_v14_0_2_set_default_dpm_table()
563 dpm_table->clk_type = SMU_DCLK; in smu_v14_0_2_set_default_dpm_table()
578 dpm_table->clk_type = SMU_DCEFCLK; in smu_v14_0_2_set_default_dpm_table()
747 enum smu_clk_type clk_type, in smu_v14_0_2_get_dpm_ultimate_freq() argument
755 switch (clk_type) { in smu_v14_0_2_get_dpm_ultimate_freq()
882 enum smu_clk_type clk_type, in smu_v14_0_2_get_current_clk_freq_by_table() argument
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/linux/drivers/clk/imx/
H A Dclk-scu.h36 int num_parents, u32 rsrc_id, u8 clk_type);
40 u32 rsrc_id, u8 clk_type);
54 u8 clk_type) in imx_clk_scu() argument
56 return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type); in imx_clk_scu()
60 int num_parents, u32 rsrc_id, u8 clk_type) in imx_clk_scu2() argument
62 return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type); in imx_clk_scu2()
H A Dclk-scu.c33 u8 clk_type; member
52 u8 clk_type; member
253 msg.data.req.clk = clk->clk_type; in clk_scu_recalc_rate()
326 msg.clk = clk->clk_type; in clk_scu_set_rate()
344 msg.data.req.clk = clk->clk_type; in clk_scu_get_parent()
371 msg.clk = clk->clk_type; in clk_scu_set_parent()
416 clk->clk_type, true, false); in clk_scu_prepare()
431 clk->clk_type, false, false); in clk_scu_unprepare()
463 u32 rsrc_id, u8 clk_type) in __imx_clk_scu() argument
475 clk->clk_type = clk_type; in __imx_clk_scu()
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H A Dclk-imx95-blk-ctl.c49 u32 clk_type; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0.c902 int smu_v15_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v15_0_wait_for_event()
909 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v15_0_get_dpm_ultimate_freq()
910 switch (clk_type) { in smu_v15_0_get_dpm_ultimate_freq()
938 clk_type); in smu_v15_0_get_dpm_ultimate_freq()
971 enum smu_clk_type clk_type, in smu_v15_0_get_dpm_ultimate_freq()
979 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v15_0_set_soft_freq_limited_range()
984 clk_type); in smu_v15_0_set_soft_freq_limited_range()
1015 enum smu_clk_type clk_type, in smu_v15_0_set_soft_freq_limited_range()
1025 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v15_0_set_hard_freq_limited_range()
1030 clk_type); in smu_v15_0_set_hard_freq_limited_range()
907 smu_v15_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max) smu_v15_0_get_dpm_ultimate_freq() argument
976 smu_v15_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic) smu_v15_0_set_soft_freq_limited_range() argument
1020 smu_v15_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max) smu_v15_0_set_hard_freq_limited_range() argument
1248 smu_v15_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value) smu_v15_0_get_dpm_freq_by_index() argument
1282 smu_v15_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value) smu_v15_0_get_dpm_level_count() argument
1293 smu_v15_0_get_fine_grained_status(struct smu_context * smu,enum smu_clk_type clk_type,bool * is_fine_grained_dpm) smu_v15_0_get_fine_grained_status() argument
1331 smu_v15_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_dpm_table * single_dpm_table) smu_v15_0_set_single_dpm_table() argument
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c986 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu_v11_0_display_clock_voltage_request() local
993 switch (clk_type) { in smu_v11_0_display_clock_voltage_request()
1639 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v11_0_get_dpm_ultimate_freq() argument
1646 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v11_0_get_dpm_ultimate_freq()
1647 switch (clk_type) { in smu_v11_0_get_dpm_ultimate_freq()
1675 clk_type); in smu_v11_0_get_dpm_ultimate_freq()
1699 enum smu_clk_type clk_type, in smu_v11_0_set_soft_freq_limited_range() argument
1707 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v11_0_set_soft_freq_limited_range()
1712 clk_type); in smu_v11_0_set_soft_freq_limited_range()
1743 enum smu_clk_type clk_type, in smu_v11_0_set_hard_freq_limited_range() argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr.h115 unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);
/linux/drivers/input/
H A Devdev.c49 enum input_clock_type clk_type; member
146 struct timespec64 ts = ktime_to_timespec64(ev_time[client->clk_type]); in __evdev_queue_syn_dropped()
177 enum input_clock_type clk_type; in evdev_set_clk_type() local
182 clk_type = INPUT_CLK_REAL; in evdev_set_clk_type()
185 clk_type = INPUT_CLK_MONO; in evdev_set_clk_type()
188 clk_type = INPUT_CLK_BOOT; in evdev_set_clk_type()
194 if (client->clk_type != clk_type) { in evdev_set_clk_type()
195 client->clk_type = clk_type; in evdev_set_clk_type()
256 ts = ktime_to_timespec64(ev_time[client->clk_type]); in evdev_pass_values()
/linux/drivers/phy/
H A Dphy-xgene.c535 enum clk_type_t clk_type; /* Input clock selection */ member
706 enum clk_type_t clk_type) in xgene_phy_cfg_cmu_clk_type() argument
719 if (clk_type == CLK_EXT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
729 } else if (clk_type == CLK_INT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
739 } else if (clk_type == CLK_INT_SING) { in xgene_phy_cfg_cmu_clk_type()
760 enum clk_type_t clk_type) in xgene_phy_sata_cfg_cmu_core() argument
806 if (clk_type == CLK_EXT_DIFF) in xgene_phy_sata_cfg_cmu_core()
1137 enum clk_type_t clk_type) in xgene_phy_cal_rdy_chk() argument
1237 enum clk_type_t clk_type) in xgene_phy_pdwn_force_vco() argument
1254 enum clk_type_t clk_type, int ssc_enable) in xgene_phy_hw_init_sata() argument
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
H A Ddce120_clk_mgr.c86 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK; in dce12_update_clocks()
101 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK; in dce12_update_clocks()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_6_ppt.c253 enum smu_clk_type clk_type; member
990 enum smu_clk_type clk_type, in smu_v13_0_6_get_dpm_ultimate_freq()
1003 switch (clk_type) { in smu_v13_0_6_get_dpm_ultimate_freq()
1039 if (!(clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)) { in smu_v13_0_6_get_dpm_ultimate_freq()
1041 smu, CMN2ASIC_MAPPING_CLK, clk_type); in smu_v13_0_6_get_dpm_ultimate_freq()
1050 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK) in smu_v13_0_6_get_dpm_ultimate_freq()
1061 if (clk_type == SMU_GFXCLK || clk_type in smu_v13_0_6_get_dpm_ultimate_freq()
986 smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max) smu_v13_0_6_get_dpm_ultimate_freq() argument
1070 smu_v13_0_6_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * levels) smu_v13_0_6_get_dpm_level_count() argument
1346 smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value) smu_v13_0_6_get_current_clk_freq_by_table() argument
2053 smu_v13_0_6_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic) smu_v13_0_6_set_soft_freq_limited_range() argument
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H A Dsmu_v13_0_7_ppt.c600 dpm_table->clk_type = SMU_SOCCLK; in smu_v13_0_7_set_default_dpm_table()
615 dpm_table->clk_type = SMU_GFXCLK; in smu_v13_0_7_set_default_dpm_table()
637 dpm_table->clk_type = SMU_UCLK; in smu_v13_0_7_set_default_dpm_table()
652 dpm_table->clk_type = SMU_FCLK; in smu_v13_0_7_set_default_dpm_table()
667 dpm_table->clk_type = SMU_VCLK; in smu_v13_0_7_set_default_dpm_table()
682 dpm_table->clk_type = SMU_DCLK; in smu_v13_0_7_set_default_dpm_table()
697 dpm_table->clk_type = SMU_DCEFCLK; in smu_v13_0_7_set_default_dpm_table()
869 enum smu_clk_type clk_type, in smu_v13_0_7_get_dpm_ultimate_freq() argument
877 switch (clk_type) { in smu_v13_0_7_get_dpm_ultimate_freq()
1005 enum smu_clk_type clk_type, in smu_v13_0_7_get_current_clk_freq_by_table() argument
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H A Daldebaran_ppt.c342 enum smu_clk_type clk_type, in aldebaran_get_dpm_ultimate_freq() argument
350 switch (clk_type) { in aldebaran_get_dpm_ultimate_freq()
390 return smu_v13_0_get_dpm_ultimate_freq(smu, clk_type, min, max); in aldebaran_get_dpm_ultimate_freq()
405 dpm_table->clk_type = SMU_SOCCLK; in aldebaran_set_default_dpm_table()
420 dpm_table->clk_type = SMU_GFXCLK; in aldebaran_set_default_dpm_table()
437 dpm_table->clk_type = SMU_UCLK; in aldebaran_set_default_dpm_table()
452 dpm_table->clk_type = SMU_FCLK; in aldebaran_set_default_dpm_table()
726 enum smu_clk_type clk_type, in aldebaran_get_current_clk_freq_by_table() argument
737 clk_type); in aldebaran_get_current_clk_freq_by_table()
1234 enum smu_clk_type clk_type, in aldebaran_set_soft_freq_limited_range() argument
[all …]
H A Dsmu_v13_0_0_ppt.c572 dpm_table->clk_type = SMU_SOCCLK; in smu_v13_0_0_set_default_dpm_table()
587 dpm_table->clk_type = SMU_GFXCLK; in smu_v13_0_0_set_default_dpm_table()
618 dpm_table->clk_type = SMU_UCLK; in smu_v13_0_0_set_default_dpm_table()
633 dpm_table->clk_type = SMU_FCLK; in smu_v13_0_0_set_default_dpm_table()
648 dpm_table->clk_type = SMU_VCLK; in smu_v13_0_0_set_default_dpm_table()
663 dpm_table->clk_type = SMU_DCLK; in smu_v13_0_0_set_default_dpm_table()
678 dpm_table->clk_type = SMU_DCEFCLK; in smu_v13_0_0_set_default_dpm_table()
859 enum smu_clk_type clk_type, in smu_v13_0_0_get_dpm_ultimate_freq() argument
867 switch (clk_type) { in smu_v13_0_0_get_dpm_ultimate_freq()
995 enum smu_clk_type clk_type, in smu_v13_0_0_get_current_clk_freq_by_table() argument
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Dsmu_v12_0.c175 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v12_0_set_soft_freq_limited_range() argument
180 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v12_0_set_soft_freq_limited_range()
183 switch (clk_type) { in smu_v12_0_set_soft_freq_limited_range()
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Damdgpu_smu.h319 enum smu_clk_type clk_type; member
871 …int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset…
879 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
902 enum smu_clk_type clk_type,
1433 …int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, u…
1439 …int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t m…
1959 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1962 int smu_set_soft_freq_range(struct smu_context *smu, enum pp_clock_type clk_type,
/linux/drivers/gpu/drm/amd/amdgpu/
H A Datombios_crtc.h41 u32 freq, u8 clk_type, u8 clk_src);
H A Datombios_crtc.c526 u32 freq, u8 clk_type, u8 clk_src) in amdgpu_atombios_crtc_set_dce_clock() argument
545 args.v2_1.asParam.ucDCEClkType = clk_type; in amdgpu_atombios_crtc_set_dce_clock()
/linux/drivers/clk/zynqmp/
H A Dclkc.c43 enum clk_type { enum
74 enum clk_type type;
/linux/drivers/gpu/drm/amd/pm/swsmu/
H A Dsmu_cmn.h166 enum smu_clk_type clk_type);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/
H A Ddcn42_clk_mgr.c449 DC_LOG_SMU("clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n"); in dcn42_dump_clk_registers()
469 DC_LOG_SMU("reg_name,value,clk_type\n"); in dcn42_dump_clk_registers()
850 unsigned int dcn42_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type) in dcn42_get_max_clock_khz()
856 switch (clk_type) { in dcn42_get_max_clock_khz()
839 dcn42_get_max_clock_khz(struct clk_mgr * clk_mgr_base,enum clk_type clk_type) dcn42_get_max_clock_khz() argument
/linux/drivers/media/dvb-frontends/
H A Dmxl5xx.c1382 u32 clk_type = 0; in config_ts() local
1465 clk_type = 1; in config_ts()
1472 clk_type); in config_ts()
1474 update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type); in config_ts()
/linux/sound/soc/codecs/
H A Dwcd9335.c324 enum wcd_clock_type clk_type; member
4082 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) || in wcd9335_enable_mclk()
4083 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) { in wcd9335_enable_mclk()
4084 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n", in wcd9335_enable_mclk()
4085 wcd->clk_type); in wcd9335_enable_mclk()
4114 wcd->clk_type = WCD_CLK_MCLK;
4130 wcd->clk_type = WCD_CLK_RCO; in wcd9335_disable_mclk()
4135 wcd->clk_type = WCD_CLK_OFF; in wcd9335_disable_mclk()

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