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Searched refs:clk_type (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0_0_ppt.c795 enum smu_clk_type clk_type, in smu_v15_0_0_get_dpm_freq_by_index() argument
801 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v15_0_0_get_dpm_freq_by_index()
804 switch (clk_type) { in smu_v15_0_0_get_dpm_freq_by_index()
839 enum smu_clk_type clk_type, in smu_v15_0_5_get_dpm_freq_by_index() argument
845 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v15_0_5_get_dpm_freq_by_index()
848 switch (clk_type) { in smu_v15_0_5_get_dpm_freq_by_index()
873 enum smu_clk_type clk_type, in smu_v15_0_common_get_dpm_freq_by_index() argument
878 smu_v15_0_5_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq); in smu_v15_0_common_get_dpm_freq_by_index()
880 smu_v15_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq); in smu_v15_0_common_get_dpm_freq_by_index()
886 enum smu_clk_type clk_type) in smu_v15_0_0_clk_dpm_is_enabled() argument
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c601 enum smu_clk_type clk_type, in smu_v13_0_5_get_current_clk_freq() argument
606 switch (clk_type) { in smu_v13_0_5_get_current_clk_freq()
632 enum smu_clk_type clk_type, in smu_v13_0_5_get_dpm_level_count() argument
637 switch (clk_type) { in smu_v13_0_5_get_dpm_level_count()
661 enum smu_clk_type clk_type, in smu_v13_0_5_get_dpm_freq_by_index() argument
667 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_5_get_dpm_freq_by_index()
670 switch (clk_type) { in smu_v13_0_5_get_dpm_freq_by_index()
705 enum smu_clk_type clk_type) in smu_v13_0_5_clk_dpm_is_enabled() argument
709 switch (clk_type) { in smu_v13_0_5_clk_dpm_is_enabled()
734 enum smu_clk_type clk_type, in smu_v13_0_5_get_dpm_ultimate_freq() argument
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H A Dsmu_v13_0_4_ppt.c394 enum smu_clk_type clk_type, in smu_v13_0_4_get_current_clk_freq() argument
399 switch (clk_type) { in smu_v13_0_4_get_current_clk_freq()
430 enum smu_clk_type clk_type, in smu_v13_0_4_get_dpm_freq_by_index() argument
436 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_4_get_dpm_freq_by_index()
439 switch (clk_type) { in smu_v13_0_4_get_dpm_freq_by_index()
474 enum smu_clk_type clk_type, in smu_v13_0_4_get_dpm_level_count() argument
479 switch (clk_type) { in smu_v13_0_4_get_dpm_level_count()
503 enum smu_clk_type clk_type, char *buf, in smu_v13_0_4_emit_clk_levels() argument
510 switch (clk_type) { in smu_v13_0_4_emit_clk_levels()
529 ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value); in smu_v13_0_4_emit_clk_levels()
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H A Dyellow_carp_ppt.c732 enum smu_clk_type clk_type, in yellow_carp_get_current_clk_freq() argument
737 switch (clk_type) { in yellow_carp_get_current_clk_freq()
766 enum smu_clk_type clk_type, in yellow_carp_get_dpm_level_count() argument
771 switch (clk_type) { in yellow_carp_get_dpm_level_count()
795 enum smu_clk_type clk_type, in yellow_carp_get_dpm_freq_by_index() argument
801 if (!clk_table || clk_type >= SMU_CLK_COUNT) in yellow_carp_get_dpm_freq_by_index()
804 switch (clk_type) { in yellow_carp_get_dpm_freq_by_index()
839 enum smu_clk_type clk_type) in yellow_carp_clk_dpm_is_enabled() argument
843 switch (clk_type) { in yellow_carp_clk_dpm_is_enabled()
868 enum smu_clk_type clk_type, in yellow_carp_get_dpm_ultimate_freq() argument
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H A Dsmu_v13_0_7_ppt.c601 dpm_table->clk_type = SMU_SOCCLK; in smu_v13_0_7_set_default_dpm_table()
616 dpm_table->clk_type = SMU_GFXCLK; in smu_v13_0_7_set_default_dpm_table()
638 dpm_table->clk_type = SMU_UCLK; in smu_v13_0_7_set_default_dpm_table()
653 dpm_table->clk_type = SMU_FCLK; in smu_v13_0_7_set_default_dpm_table()
668 dpm_table->clk_type = SMU_VCLK; in smu_v13_0_7_set_default_dpm_table()
683 dpm_table->clk_type = SMU_DCLK; in smu_v13_0_7_set_default_dpm_table()
698 dpm_table->clk_type = SMU_DCEFCLK; in smu_v13_0_7_set_default_dpm_table()
870 enum smu_clk_type clk_type, in smu_v13_0_7_get_dpm_ultimate_freq() argument
878 switch (clk_type) { in smu_v13_0_7_get_dpm_ultimate_freq()
1006 enum smu_clk_type clk_type, in smu_v13_0_7_get_current_clk_freq_by_table() argument
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H A Dsmu_v13_0_0_ppt.c573 dpm_table->clk_type = SMU_SOCCLK; in smu_v13_0_0_set_default_dpm_table()
588 dpm_table->clk_type = SMU_GFXCLK; in smu_v13_0_0_set_default_dpm_table()
619 dpm_table->clk_type = SMU_UCLK; in smu_v13_0_0_set_default_dpm_table()
634 dpm_table->clk_type = SMU_FCLK; in smu_v13_0_0_set_default_dpm_table()
649 dpm_table->clk_type = SMU_VCLK; in smu_v13_0_0_set_default_dpm_table()
664 dpm_table->clk_type = SMU_DCLK; in smu_v13_0_0_set_default_dpm_table()
679 dpm_table->clk_type = SMU_DCEFCLK; in smu_v13_0_0_set_default_dpm_table()
860 enum smu_clk_type clk_type, in smu_v13_0_0_get_dpm_ultimate_freq() argument
868 switch (clk_type) { in smu_v13_0_0_get_dpm_ultimate_freq()
996 enum smu_clk_type clk_type, in smu_v13_0_0_get_current_clk_freq_by_table() argument
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/linux/drivers/clk/imx/
H A Dclk-scu.h36 int num_parents, u32 rsrc_id, u8 clk_type);
40 u32 rsrc_id, u8 clk_type);
54 u8 clk_type) in imx_clk_scu() argument
56 return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type); in imx_clk_scu()
60 int num_parents, u32 rsrc_id, u8 clk_type) in imx_clk_scu2() argument
62 return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type); in imx_clk_scu2()
H A Dclk-scu.c33 u8 clk_type; member
52 u8 clk_type; member
253 msg.data.req.clk = clk->clk_type; in clk_scu_recalc_rate()
309 msg.clk = clk->clk_type; in clk_scu_set_rate()
327 msg.data.req.clk = clk->clk_type; in clk_scu_get_parent()
354 msg.clk = clk->clk_type; in clk_scu_set_parent()
399 clk->clk_type, true, false); in clk_scu_prepare()
414 clk->clk_type, false, false); in clk_scu_unprepare()
446 u32 rsrc_id, u8 clk_type) in __imx_clk_scu() argument
458 clk->clk_type = clk_type; in __imx_clk_scu()
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H A Dclk-imx95-blk-ctl.c51 u32 clk_type; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dcyan_skillfish_ppt.c261 enum smu_clk_type clk_type, in cyan_skillfish_get_current_clk_freq() argument
266 switch (clk_type) { in cyan_skillfish_get_current_clk_freq()
292 enum smu_clk_type clk_type, char *buf, in cyan_skillfish_emit_clk_levels() argument
299 switch (clk_type) { in cyan_skillfish_emit_clk_levels()
326 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_emit_clk_levels()
333 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_emit_clk_levels()
540 enum smu_clk_type clk_type, in cyan_skillfish_get_dpm_ultimate_freq() argument
547 switch (clk_type) { in cyan_skillfish_get_dpm_ultimate_freq()
554 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &low); in cyan_skillfish_get_dpm_ultimate_freq()
/linux/drivers/input/
H A Devdev.c50 enum input_clock_type clk_type; member
149 struct timespec64 ts = ktime_to_timespec64(ev_time[client->clk_type]); in __evdev_queue_syn_dropped()
180 enum input_clock_type clk_type; in evdev_set_clk_type() local
185 clk_type = INPUT_CLK_REAL; in evdev_set_clk_type()
188 clk_type = INPUT_CLK_MONO; in evdev_set_clk_type()
191 clk_type = INPUT_CLK_BOOT; in evdev_set_clk_type()
197 if (client->clk_type != clk_type) { in evdev_set_clk_type()
198 client->clk_type = clk_type; in evdev_set_clk_type()
261 ts = ktime_to_timespec64(ev_time[client->clk_type]); in evdev_pass_values()
/linux/drivers/phy/
H A Dphy-xgene.c535 enum clk_type_t clk_type; /* Input clock selection */ member
706 enum clk_type_t clk_type) in xgene_phy_cfg_cmu_clk_type() argument
719 if (clk_type == CLK_EXT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
729 } else if (clk_type == CLK_INT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
739 } else if (clk_type == CLK_INT_SING) { in xgene_phy_cfg_cmu_clk_type()
760 enum clk_type_t clk_type) in xgene_phy_sata_cfg_cmu_core() argument
806 if (clk_type == CLK_EXT_DIFF) in xgene_phy_sata_cfg_cmu_core()
1137 enum clk_type_t clk_type) in xgene_phy_cal_rdy_chk() argument
1237 enum clk_type_t clk_type) in xgene_phy_pdwn_force_vco() argument
1254 enum clk_type_t clk_type, int ssc_enable) in xgene_phy_hw_init_sata() argument
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Dsmu_v12_0.c175 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v12_0_set_soft_freq_limited_range() argument
180 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v12_0_set_soft_freq_limited_range()
183 switch (clk_type) { in smu_v12_0_set_soft_freq_limited_range()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Datombios_crtc.h41 u32 freq, u8 clk_type, u8 clk_src);
H A Datombios_crtc.c526 u32 freq, u8 clk_type, u8 clk_src) in amdgpu_atombios_crtc_set_dce_clock() argument
545 args.v2_1.asParam.ucDCEClkType = clk_type; in amdgpu_atombios_crtc_set_dce_clock()
/linux/drivers/clk/zynqmp/
H A Dclkc.c43 enum clk_type { enum
74 enum clk_type type;
/linux/drivers/media/dvb-frontends/
H A Dmxl5xx.c1382 u32 clk_type = 0; in config_ts() local
1465 clk_type = 1; in config_ts()
1472 clk_type); in config_ts()
1474 update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type); in config_ts()
/linux/sound/soc/codecs/
H A Dwcd9335.c324 enum wcd_clock_type clk_type; member
4082 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) || in wcd9335_enable_mclk()
4083 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) { in wcd9335_enable_mclk()
4084 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n", in wcd9335_enable_mclk()
4085 wcd->clk_type); in wcd9335_enable_mclk()
4114 wcd->clk_type = WCD_CLK_MCLK;
4130 wcd->clk_type = WCD_CLK_RCO; in wcd9335_disable_mclk()
4135 wcd->clk_type = WCD_CLK_OFF; in wcd9335_disable_mclk()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c1319 static unsigned int dcn35_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type) in dcn35_get_max_clock_khz() argument
1325 switch (clk_type) { in dcn35_get_max_clock_khz()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c1578 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega12_display_clock_voltage_request() local
1584 switch (clk_type) { in vega12_display_clock_voltage_request()
H A Dvega20_hwmgr.c2304 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega20_display_clock_voltage_request() local
2310 switch (clk_type) { in vega20_display_clock_voltage_request()