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Searched refs:clk_regmap (Results 1 – 25 of 106) sorted by relevance

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/linux/drivers/clk/meson/
H A Da1-peripherals.c49 static struct clk_regmap a1_xtal_in = {
64 static struct clk_regmap a1_fixpll_in = {
79 static struct clk_regmap a1_usb_phy_in = {
94 static struct clk_regmap a1_usb_ctrl_in = {
109 static struct clk_regmap a1_hifipll_in = {
124 static struct clk_regmap a1_syspll_in = {
139 static struct clk_regmap a1_dds_in = {
154 static struct clk_regmap a1_rtc_32k_in = {
180 static struct clk_regmap a1_rtc_32k_div = {
219 static struct clk_regmap a1_rtc_32k_xtal = {
[all …]
H A Daxg.c111 static struct clk_regmap axg_fixed_pll_dco = {
154 static struct clk_regmap axg_fixed_pll = {
175 static struct clk_regmap axg_sys_pll_dco = {
213 static struct clk_regmap axg_sys_pll = {
272 static struct clk_regmap axg_gp0_pll_dco = {
318 static struct clk_regmap axg_gp0_pll = {
344 static struct clk_regmap axg_hifi_pll_dco = {
391 static struct clk_regmap axg_hifi_pll = {
420 static struct clk_regmap axg_fclk_div2 = {
447 static struct clk_regmap axg_fclk_div3 = {
[all …]
H A Dc3-pll.c37 static struct clk_regmap c3_fclk_50m_en = {
78 static struct clk_regmap c3_fclk_div2 = {
106 static struct clk_regmap c3_fclk_div2p5 = {
134 static struct clk_regmap c3_fclk_div3 = {
162 static struct clk_regmap c3_fclk_div4 = {
190 static struct clk_regmap c3_fclk_div5 = {
218 static struct clk_regmap c3_fclk_div7 = {
246 static struct clk_regmap c3_gp0_pll_dco = {
303 static struct clk_regmap c3_gp0_pll = {
329 static struct clk_regmap c3_hifi_pll_dco = {
[all …]
H A Dmeson8b.c122 static struct clk_regmap meson8b_fixed_pll_dco = {
167 static struct clk_regmap meson8b_fixed_pll = {
238 static struct clk_regmap meson8b_hdmi_pll_dco = {
285 static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
303 static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
321 static struct clk_regmap meson8b_sys_pll_dco = {
362 static struct clk_regmap meson8b_sys_pll = {
393 static struct clk_regmap meson8b_fclk_div2 = {
421 static struct clk_regmap meson8b_fclk_div3 = {
449 static struct clk_regmap meson8b_fclk_div4 = {
[all …]
H A Ds4-pll.c54 static struct clk_regmap s4_fixed_pll_dco = {
97 static struct clk_regmap s4_fixed_pll = {
129 static struct clk_regmap s4_fclk_div2 = {
155 static struct clk_regmap s4_fclk_div3 = {
181 static struct clk_regmap s4_fclk_div4 = {
207 static struct clk_regmap s4_fclk_div5 = {
233 static struct clk_regmap s4_fclk_div7 = {
261 static struct clk_regmap s4_fclk_div2p5 = {
293 static struct clk_regmap s4_gp0_pll_dco = {
334 static struct clk_regmap s4_gp0_pll = {
[all …]
H A Dg12a-aoclk.c71 static struct clk_regmap g12a_ao_cts_oscin = {
98 static struct clk_regmap g12a_ao_32k_by_oscin_pre = {
113 static struct clk_regmap g12a_ao_32k_by_oscin_div = {
152 static struct clk_regmap g12a_ao_32k_by_oscin_sel = {
171 static struct clk_regmap g12a_ao_32k_by_oscin = {
189 static struct clk_regmap g12a_ao_cec_pre = {
204 static struct clk_regmap g12a_ao_cec_div = {
243 static struct clk_regmap g12a_ao_cec_sel = {
262 static struct clk_regmap g12a_ao_cec = {
278 static struct clk_regmap g12a_ao_cts_rtc_oscin = {
[all …]
H A Dclk-regmap.h24 struct clk_regmap { struct
30 static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw) in to_clk_regmap() argument
32 return container_of(hw, struct clk_regmap, hw); in to_clk_regmap()
55 clk_get_regmap_gate_data(struct clk_regmap *clk) in clk_get_regmap_gate_data()
83 clk_get_regmap_div_data(struct clk_regmap *clk) in clk_get_regmap_div_data()
113 clk_get_regmap_mux_data(struct clk_regmap *clk) in clk_get_regmap_mux_data()
H A Daxg-aoclk.c51 static struct clk_regmap axg_ao_cts_oscin = {
66 static struct clk_regmap axg_ao_32k_pre = {
91 static struct clk_regmap axg_ao_32k_div = {
130 static struct clk_regmap axg_ao_32k_sel = {
149 static struct clk_regmap axg_ao_32k = {
165 static struct clk_regmap axg_ao_cts_rtc_oscin = {
184 static struct clk_regmap axg_ao_clk81 = {
209 static struct clk_regmap axg_ao_saradc_mux = {
226 static struct clk_regmap axg_ao_saradc_div = {
243 static struct clk_regmap axg_ao_saradc_gate = {
H A Dgxbb-aoclk.c39 static struct clk_regmap gxbb_ao_cts_oscin = {
54 static struct clk_regmap gxbb_ao_32k_pre = {
77 static struct clk_regmap gxbb_ao_32k_div = {
114 static struct clk_regmap gxbb_ao_32k_sel = {
133 static struct clk_regmap gxbb_ao_32k = {
147 static struct clk_regmap gxbb_ao_cts_rtc_oscin = {
169 static struct clk_regmap gxbb_ao_clk81 = {
188 static struct clk_regmap gxbb_ao_cts_cec = {
H A Da1-pll.c29 static struct clk_regmap a1_fixed_pll_dco = {
72 static struct clk_regmap a1_fixed_pll = {
100 static struct clk_regmap a1_hifi_pll = {
164 static struct clk_regmap a1_fclk_div2 = {
202 static struct clk_regmap a1_fclk_div3 = {
235 static struct clk_regmap a1_fclk_div5 = {
268 static struct clk_regmap a1_fclk_div7 = {
H A Dmeson-clkc-utils.h31 struct clk_regmap _name = { \
54 struct clk_regmap _prefix##_name##_sel = { \
73 struct clk_regmap _prefix##_name##_div = { \
92 struct clk_regmap _prefix##_name = { \
H A Dc3-peripherals.c60 static struct clk_regmap c3_rtc_xtal_clkin = {
80 static struct clk_regmap c3_rtc_32k_div = {
124 static struct clk_regmap c3_rtc_32k_sel = {
139 static struct clk_regmap c3_rtc_32k = {
161 static struct clk_regmap c3_rtc_clk = {
331 static struct clk_regmap c3_clk_12_24m_in = {
346 static struct clk_regmap c3_clk_12_24m = {
363 static struct clk_regmap c3_fclk_25m_div = {
379 static struct clk_regmap c3_fclk_25m = {
417 static struct clk_regmap c3_gen_sel = {
[all …]
H A Dmeson8-ddr.c26 static struct clk_regmap meson8_ddr_pll_dco = {
64 static struct clk_regmap meson8_ddr_pll = {
/linux/drivers/clk/qcom/
H A Dclk-regmap.h20 struct clk_regmap { struct
28 static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw) in to_clk_regmap() argument
30 return container_of(hw, struct clk_regmap, hw); in to_clk_regmap()
36 int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk);
H A Dclk-regmap-phy-mux.c18 static inline struct clk_regmap_phy_mux *to_clk_regmap_phy_mux(struct clk_regmap *clkr) in to_clk_regmap_phy_mux()
25 struct clk_regmap *clkr = to_clk_regmap(hw); in phy_mux_is_enabled()
39 struct clk_regmap *clkr = to_clk_regmap(hw); in phy_mux_enable()
49 struct clk_regmap *clkr = to_clk_regmap(hw); in phy_mux_disable()
H A Dclk-regmap.c24 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_is_enabled_regmap()
50 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_enable_regmap()
74 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_disable_regmap()
97 int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk) in devm_clk_register_regmap()
H A Dclk-cbf-8996.c95 struct clk_regmap clkr;
98 static struct clk_cbf_8996_mux *to_clk_cbf_8996_mux(struct clk_regmap *clkr) in to_clk_cbf_8996_mux()
108 struct clk_regmap *clkr = to_clk_regmap(hw); in clk_cbf_8996_mux_get_parent()
119 struct clk_regmap *clkr = to_clk_regmap(hw); in clk_cbf_8996_mux_set_parent()
205 static struct clk_regmap *cbf_msm8996_clks[] = {
H A Dclk-regmap-mux.c21 struct clk_regmap *clkr = to_clk_regmap(hw); in mux_get_parent()
39 struct clk_regmap *clkr = to_clk_regmap(hw); in mux_set_parent()
H A Dlpasscc-sc7280.c82 static struct clk_regmap *lpass_cc_top_sc7280_clocks[] = {
93 static struct clk_regmap *lpass_qdsp6ss_sc7280_clocks[] = {
H A Dtcsrcc-sm8550.c132 static struct clk_regmap *tcsr_cc_sar2130p_clocks[] = {
139 static struct clk_regmap *tcsr_cc_sm8550_clocks[] = {
H A Dq6sstop-qcs404.c121 static struct clk_regmap *q6sstop_qcs404_clocks[] = {
142 static struct clk_regmap *tcsr_qcs404_clocks[] = {
H A Dclk-cpu-8996.c260 struct clk_regmap clkr;
276 struct clk_regmap *clkr = to_clk_regmap(hw); in clk_cpu_8996_pmux_get_parent()
287 struct clk_regmap *clkr = to_clk_regmap(hw); in clk_cpu_8996_pmux_set_parent()
424 static struct clk_regmap *cpu_msm8996_clks[] = {
H A Dclk-regmap-phy-mux.h28 struct clk_regmap clkr;
H A Dclk-regmap-mux.h18 struct clk_regmap clkr;
/linux/drivers/memory/samsung/
H A Dexynos5422-dmc.c159 struct regmap *clk_regmap; member
319 ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, &reg); in exynos5_switch_timing_regs()
328 regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg); in exynos5_switch_timing_regs()
1307 regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, &tmp); in exynos5_dmc_init_clks()
1309 regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, tmp); in exynos5_dmc_init_clks()
1376 ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val); in exynos5_dmc_set_pause_on_switching()
1381 regmap_write(dmc->clk_regmap, CDREX_PAUSE, val); in exynos5_dmc_set_pause_on_switching()
1437 dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np, in exynos5_dmc_probe()
1439 if (IS_ERR(dmc->clk_regmap)) in exynos5_dmc_probe()
1440 return PTR_ERR(dmc->clk_regmap); in exynos5_dmc_probe()

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