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Searched refs:clk_rate (Results 1 – 25 of 95) sorted by relevance

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/linux/drivers/clocksource/
H A Dtimer-microchip-pit64b.c239 static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate, in mchp_pit64b_pres_compute() argument
245 tmp = clk_rate / (*pres + 1); in mchp_pit64b_pres_compute()
348 u32 clk_rate) in mchp_pit64b_init_clksrc() argument
374 ret = clocksource_register_hz(&cs->clksrc, clk_rate); in mchp_pit64b_init_clksrc()
385 sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate); in mchp_pit64b_init_clksrc()
388 mchp_pit64b_dt.freq = clk_rate; in mchp_pit64b_init_clksrc()
395 u32 clk_rate, u32 irq) in mchp_pit64b_init_clkevt() argument
404 mchp_pit64b_ce_cycles = DIV_ROUND_CLOSEST(clk_rate, HZ); in mchp_pit64b_init_clkevt()
428 clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX); in mchp_pit64b_init_clkevt()
437 unsigned long clk_rate; in mchp_pit64b_dt_init_timer() local
[all …]
/linux/drivers/pwm/
H A Dpwm-omap-dmtimer.c80 static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns) in pwm_omap_dmtimer_get_clock_cycles() argument
82 return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC); in pwm_omap_dmtimer_get_clock_cycles()
153 unsigned long clk_rate; in pwm_omap_dmtimer_config() local
169 clk_rate = clk_get_rate(fclk); in pwm_omap_dmtimer_config()
170 if (!clk_rate) { in pwm_omap_dmtimer_config()
175 dev_dbg(pwmchip_parent(chip), "clk rate: %luHz\n", clk_rate); in pwm_omap_dmtimer_config()
193 period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns); in pwm_omap_dmtimer_config()
194 duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns); in pwm_omap_dmtimer_config()
199 period_ns, clk_rate); in pwm_omap_dmtimer_config()
206 duty_ns, clk_rate); in pwm_omap_dmtimer_config()
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H A Dpwm-sunplus.c60 u64 clk_rate; in sunplus_pwm_apply() local
77 clk_rate = clk_get_rate(priv->clk); in sunplus_pwm_apply()
84 if (clk_rate > (u64)SP7021_PWM_FREQ_SCALER * NSEC_PER_SEC) in sunplus_pwm_apply()
91 dd_freq = mul_u64_u64_div_u64(clk_rate, state->period, (u64)SP7021_PWM_FREQ_SCALER in sunplus_pwm_apply()
116 duty = mul_u64_u64_div_u64(state->duty_cycle, clk_rate, in sunplus_pwm_apply()
132 u64 clk_rate; in sunplus_pwm_get_state() local
137 clk_rate = clk_get_rate(priv->clk); in sunplus_pwm_get_state()
146 * NSEC_PER_SEC, clk_rate); in sunplus_pwm_get_state()
151 clk_rate); in sunplus_pwm_get_state()
H A Dpwm-keembay.c96 unsigned long clk_rate; in keembay_pwm_get_state() local
99 clk_rate = clk_get_rate(priv->clk); in keembay_pwm_get_state()
112 state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate); in keembay_pwm_get_state()
113 state->period = DIV_ROUND_UP_ULL(high + low, clk_rate); in keembay_pwm_get_state()
125 unsigned long clk_rate; in keembay_pwm_apply() local
153 clk_rate = clk_get_rate(priv->clk); in keembay_pwm_apply()
154 div = clk_rate * state->duty_cycle; in keembay_pwm_apply()
160 div = clk_rate * state->period; in keembay_pwm_apply()
H A Dpwm-sun4i.c112 u64 clk_rate, tmp; in sun4i_pwm_get_state() local
116 clk_rate = clk_get_rate(sun4ichip->clk); in sun4i_pwm_get_state()
117 if (!clk_rate) in sun4i_pwm_get_state()
129 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); in sun4i_pwm_get_state()
159 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in sun4i_pwm_get_state()
162 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in sun4i_pwm_get_state()
172 u64 clk_rate, div = 0; in sun4i_pwm_calculate() local
175 clk_rate = clk_get_rate(sun4ichip->clk); in sun4i_pwm_calculate()
179 (state->period * clk_rate >= NSEC_PER_SEC) && in sun4i_pwm_calculate()
180 (state->period * clk_rate < 2 * NSEC_PER_SEC) && in sun4i_pwm_calculate()
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H A Dpwm-microchip-core.c131 static u64 mchp_core_pwm_calc_duty(const struct pwm_state *state, u64 clk_rate, in mchp_core_pwm_calc_duty() argument
143 duty_steps = mul_u64_u64_div_u64(state->duty_cycle, clk_rate, tmp); in mchp_core_pwm_calc_duty()
182 static int mchp_core_pwm_calc_period(const struct pwm_state *state, unsigned long clk_rate, in mchp_core_pwm_calc_period() argument
209 tmp = mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC); in mchp_core_pwm_calc_period()
276 unsigned long clk_rate; in mchp_core_pwm_apply_locked() local
291 clk_rate = clk_get_rate(mchp_core_pwm->clk); in mchp_core_pwm_apply_locked()
292 if (clk_rate >= NSEC_PER_SEC) in mchp_core_pwm_apply_locked()
295 ret = mchp_core_pwm_calc_period(state, clk_rate, &prescale, &period_steps); in mchp_core_pwm_apply_locked()
335 duty_steps = mchp_core_pwm_calc_duty(state, clk_rate, prescale, period_steps); in mchp_core_pwm_apply_locked()
H A Dpwm-rcar.c75 unsigned long clk_rate = clk_get_rate(rp->clk); in rcar_pwm_get_clock_division() local
78 if (clk_rate == 0) in rcar_pwm_get_clock_division()
82 tmp = (u64)period_ns * clk_rate + div - 1; in rcar_pwm_get_clock_division()
110 unsigned long clk_rate = clk_get_rate(rp->clk); in rcar_pwm_set_counter() local
114 tmp = mul_u64_u64_div_u64(period_ns, clk_rate, (u64)NSEC_PER_SEC << div); in rcar_pwm_set_counter()
120 tmp = mul_u64_u64_div_u64(duty_ns, clk_rate, (u64)NSEC_PER_SEC << div); in rcar_pwm_set_counter()
H A Dpwm-rockchip.c68 unsigned long clk_rate; in rockchip_pwm_get_state() local
81 clk_rate = clk_get_rate(pc->clk); in rockchip_pwm_get_state()
85 state->period = DIV_U64_ROUND_UP(tmp, clk_rate); in rockchip_pwm_get_state()
89 state->duty_cycle = DIV_U64_ROUND_UP(tmp, clk_rate); in rockchip_pwm_get_state()
110 u64 clk_rate, tmp; in rockchip_pwm_config() local
114 clk_rate = clk_get_rate(pc->clk); in rockchip_pwm_config()
121 tmp = mul_u64_u64_div_u64(clk_rate, state->period, prescaled_ns); in rockchip_pwm_config()
126 tmp = mul_u64_u64_div_u64(clk_rate, state->duty_cycle, prescaled_ns); in rockchip_pwm_config()
H A Dpwm-lpc18xx-sct.c97 unsigned long clk_rate; member
152 val = mul_u64_u64_div_u64(period_ns, lpc18xx_pwm->clk_rate, NSEC_PER_SEC); in lpc18xx_pwm_config_period()
174 val = mul_u64_u64_div_u64(duty_ns, lpc18xx_pwm->clk_rate, NSEC_PER_SEC); in lpc18xx_pwm_config_duty()
358 lpc18xx_pwm->clk_rate = clk_get_rate(lpc18xx_pwm->pwm_clk); in lpc18xx_pwm_probe()
359 if (!lpc18xx_pwm->clk_rate) in lpc18xx_pwm_probe()
366 if (lpc18xx_pwm->clk_rate > NSEC_PER_SEC) in lpc18xx_pwm_probe()
370 mul_u64_u64_div_u64(NSEC_PER_SEC, LPC18XX_PWM_TIMER_MAX, lpc18xx_pwm->clk_rate); in lpc18xx_pwm_probe()
373 lpc18xx_pwm->clk_rate); in lpc18xx_pwm_probe()
/linux/drivers/mfd/
H A Dintel-lpss-acpi.c37 .clk_rate = 120000000,
51 .clk_rate = 120000000,
67 .clk_rate = 120000000,
82 .clk_rate = 100000000,
98 .clk_rate = 133000000,
114 .clk_rate = 133000000,
128 .clk_rate = 120000000,
133 .clk_rate = 216000000,
/linux/drivers/watchdog/
H A Dloongson1_wdt.c50 unsigned long clk_rate; member
73 counts = drvdata->clk_rate * min(timeout, max_hw_heartbeat); in ls1x_wdt_set_timeout()
130 unsigned long clk_rate; in ls1x_wdt_probe() local
147 clk_rate = clk_get_rate(drvdata->clk); in ls1x_wdt_probe()
148 if (!clk_rate) in ls1x_wdt_probe()
150 drvdata->clk_rate = clk_rate; in ls1x_wdt_probe()
157 ls1x_wdt->max_hw_heartbeat_ms = U32_MAX / clk_rate * 1000; in ls1x_wdt_probe()
H A Dimgpdc_wdt.c116 unsigned long clk_rate = clk_get_rate(wdt->wdt_clk); in __pdc_wdt_set_timeout() local
120 val |= order_base_2(wdt->wdt_dev.timeout * clk_rate) - 1; in __pdc_wdt_set_timeout()
183 unsigned long clk_rate; in pdc_wdt_probe() local
207 clk_rate = clk_get_rate(pdc_wdt->wdt_clk); in pdc_wdt_probe()
208 if (clk_rate == 0) { in pdc_wdt_probe()
213 if (order_base_2(clk_rate) > PDC_WDT_CONFIG_DELAY_MASK + 1) { in pdc_wdt_probe()
218 if (order_base_2(clk_rate) == 0) in pdc_wdt_probe()
227 do_div(div, clk_rate); in pdc_wdt_probe()
H A Drenesas_wdt.c37 DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
40 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
52 unsigned long clk_rate; member
80 delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate); in rwdt_wait_cycles()
143 udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate)); in rwdt_restart()
155 udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate)); in rwdt_restart()
237 priv->clk_rate = clk_get_rate(priv->clk); in rwdt_probe()
242 if (!priv->clk_rate) { in rwdt_probe()
248 clks_per_sec = priv->clk_rate / clk_divs[i]; in rwdt_probe()
H A Dlantiq_wdt.c65 unsigned long clk_rate; member
104 timeout = wdt->timeout * priv->clk_rate; in ltq_wdt_start()
132 timeout = wdt->timeout * priv->clk_rate; in ltq_wdt_ping()
148 return do_div(timeout, priv->clk_rate); in ltq_wdt_get_timeleft()
220 priv->clk_rate = clk_get_rate(clk) / LTQ_WDT_DIVIDER; in ltq_wdt_probe()
221 if (!priv->clk_rate) { in ltq_wdt_probe()
231 wdt->max_timeout = LTQ_WDT_CR_MAX_TIMEOUT / priv->clk_rate; in ltq_wdt_probe()
H A Dorion_wdt.c74 unsigned long clk_rate; member
93 dev->clk_rate = clk_get_rate(dev->clk); in orion_wdt_clock_init()
116 dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO; in armada370_wdt_clock_init()
136 dev->clk_rate = clk_get_rate(dev->clk); in armada375_wdt_clock_init()
155 dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO; in armada375_wdt_clock_init()
179 dev->clk_rate = clk_get_rate(dev->clk); in armadaxp_wdt_clock_init()
187 writel(dev->clk_rate * wdt_dev->timeout, in orion_wdt_ping()
190 writel(dev->clk_rate * (wdt_dev->timeout - wdt_dev->pretimeout), in orion_wdt_ping()
202 writel(dev->clk_rate * wdt_dev->timeout, in armada375_start()
205 writel(dev->clk_rate * (wdt_dev->timeout - wdt_dev->pretimeout), in armada375_start()
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H A Dapple_wdt.c59 unsigned long clk_rate; member
103 writel_relaxed(wdt->clk_rate * actual, wdt->regs + APPLE_WDT_WD1_BITE_TIME); in apple_wdt_set_timeout()
118 return (reset_time - cur_time) / wdt->clk_rate; in apple_wdt_get_timeleft()
175 wdt->clk_rate = clk_get_rate(clk); in apple_wdt_probe()
176 if (!wdt->clk_rate) in apple_wdt_probe()
183 wdt->wdd.max_hw_heartbeat_ms = U32_MAX / wdt->clk_rate * 1000; in apple_wdt_probe()
H A Dlpc18xx_wdt.c55 unsigned long clk_rate; member
108 val = DIV_ROUND_UP(lpc18xx_wdt->wdt_dev.timeout * lpc18xx_wdt->clk_rate, in __lpc18xx_wdt_set_timeout()
130 return (val * LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate; in lpc18xx_wdt_get_timeleft()
227 lpc18xx_wdt->clk_rate = clk_get_rate(lpc18xx_wdt->wdt_clk); in lpc18xx_wdt_probe()
228 if (lpc18xx_wdt->clk_rate == 0) { in lpc18xx_wdt_probe()
237 LPC18XX_WDT_CLK_DIV, lpc18xx_wdt->clk_rate); in lpc18xx_wdt_probe()
240 LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate; in lpc18xx_wdt_probe()
H A Drzn1_wdt.c107 unsigned long clk_rate; in rzn1_wdt_probe() local
136 clk_rate = clk_get_rate(clk); in rzn1_wdt_probe()
137 if (!clk_rate) { in rzn1_wdt_probe()
142 wdt->clk_rate_khz = clk_rate / 1000; in rzn1_wdt_probe()
/linux/arch/m68k/include/asm/
H A Dmcfclk.h32 #define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \ argument
35 .rate = clk_rate, \
42 #define DEFINE_CLK(clk_ref, clk_name, clk_rate) \ argument
44 .rate = clk_rate, \
/linux/drivers/spi/
H A Dspi-rzv2h-rspi.c83 unsigned long clk_rate; member
418 long clk_rate, clk_min_rate, clk_max_rate; in rzv2h_rspi_find_rate_variable() local
486 clk_rate = (spr + 1) * rate_div; in rzv2h_rspi_find_rate_variable()
488 clk_rate = clk_round_rate(clk, clk_rate); in rzv2h_rspi_find_rate_variable()
489 if (clk_rate <= 0) in rzv2h_rspi_find_rate_variable()
492 actual_hz = rzv2h_rspi_calc_bitrate(clk_rate, spr, brdv); in rzv2h_rspi_find_rate_variable()
500 .clk_rate = clk_rate, in rzv2h_rspi_find_rate_variable()
516 unsigned long clk_rate; in rzv2h_rspi_find_rate_fixed() local
531 clk_rate = clk_get_rate(clk); in rzv2h_rspi_find_rate_fixed()
533 spr = DIV_ROUND_UP(clk_rate, hz * (1 << (brdv + 1))); in rzv2h_rspi_find_rate_fixed()
[all …]
/linux/sound/soc/loongson/
H A Dloongson_i2s.c65 u32 clk_rate = i2s->clk_rate; in loongson_i2s_hw_params() local
76 bclk_ratio = DIV_ROUND_CLOSEST(clk_rate, in loongson_i2s_hw_params()
78 mclk_ratio = DIV_ROUND_CLOSEST(clk_rate, (sysclk * 2)) - 1; in loongson_i2s_hw_params()
91 mclk_ratio = clk_rate / sysclk; in loongson_i2s_hw_params()
92 mclk_ratio_frac = DIV_ROUND_CLOSEST_ULL(((u64)clk_rate << 16), in loongson_i2s_hw_params()
/linux/drivers/nvmem/
H A Dvf610-ocotp.c116 u32 clk_rate; in vf610_ocotp_calculate_timing() local
120 clk_rate = clk_get_rate(ocotp_dev->clk); in vf610_ocotp_calculate_timing()
123 relax = clk_rate / (1000000000 / DEF_RELAX) - 1; in vf610_ocotp_calculate_timing()
124 strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1; in vf610_ocotp_calculate_timing()
125 strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1; in vf610_ocotp_calculate_timing()
H A Dimx-ocotp.c242 unsigned long clk_rate; in imx_ocotp_set_imx6_timing() local
274 clk_rate = clk_get_rate(priv->clk); in imx_ocotp_set_imx6_timing()
276 relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1; in imx_ocotp_set_imx6_timing()
277 strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS, in imx_ocotp_set_imx6_timing()
280 strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US, in imx_ocotp_set_imx6_timing()
294 unsigned long clk_rate; in imx_ocotp_set_imx7_timing() local
301 clk_rate = clk_get_rate(priv->clk); in imx_ocotp_set_imx7_timing()
302 fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE, in imx_ocotp_set_imx7_timing()
304 strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG, in imx_ocotp_set_imx7_timing()
/linux/drivers/media/rc/
H A Dmeson-ir-tx.c76 unsigned long clk_rate; member
81 unsigned int cnt = DIV_ROUND_CLOSEST(ir->clk_rate, ir->carrier); in meson_irtx_set_mod()
86 ir->carrier, NSEC_PER_SEC / ir->clk_rate * cnt, in meson_irtx_set_mod()
296 ir->clk_rate = clk_get_rate(clock) / 3; in meson_irtx_mod_clock_probe()
298 if (ir->clk_rate < IRB_MOD_1US_CLK_RATE) { in meson_irtx_mod_clock_probe()
300 ir->clk_rate = IRB_MOD_1US_CLK_RATE; in meson_irtx_mod_clock_probe()
303 dev_info(ir->dev, "F_clk = %luHz\n", ir->clk_rate); in meson_irtx_mod_clock_probe()
/linux/drivers/phy/ralink/
H A Dphy-mt7621-pci.c120 unsigned long clk_rate; in mt7621_set_phy_for_ssc() local
122 clk_rate = clk_get_rate(phy->sys_clk); in mt7621_set_phy_for_ssc()
123 if (!clk_rate) in mt7621_set_phy_for_ssc()
142 if (clk_rate == 40000000) { /* 40MHz Xtal */ in mt7621_set_phy_for_ssc()
148 } else if (clk_rate == 25000000) { /* 25MHz Xal */ in mt7621_set_phy_for_ssc()
199 if (clk_rate == 40000000) { /* 40MHz Xtal */ in mt7621_set_phy_for_ssc()

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