Searched refs:clk_div_mask (Results 1 – 15 of 15) sorted by relevance
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()55 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate()91 val &= ~(clk_div_mask(div->width) << div->shift); in clk_divider_gate_set_rate()137 val &= clk_div_mask(div->width); in clk_divider_disable()150 val &= clk_div_mask(div->width); in clk_divider_is_enabled()210 val &= clk_div_mask(width); in imx_clk_hw_divider_gate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()44 div_value &= clk_div_mask(PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()95 val = orig & ~((clk_div_mask(divider->width) << divider->shift) | in imx8m_clk_composite_divider_set_rate()96 (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); in imx8m_clk_composite_divider_set_rate()122 prediv_value &= clk_div_mask(divider->width); in imx8m_divider_determine_rate()126 div_value &= clk_div_mask(PCG_DIV_WIDTH); in imx8m_divider_determine_rate()
124 val &= ~(clk_div_mask(divider->width) << divider->shift); in imx93_clk_composite_divider_set_rate()
49 unsigned int maxdiv = 0, mask = clk_div_mask(width); in _get_table_maxdiv()73 return clk_div_mask(width); in _get_maxdiv()75 return 1 << clk_div_mask(width); in _get_maxdiv()77 return 2 * (clk_div_mask(width) + 1); in _get_maxdiv()80 return clk_div_mask(width) + 1; in _get_maxdiv()102 return val ? val : clk_div_mask(width) + 1; in _get_div()129 return (div == clk_div_mask(width) + 1) ? 0 : div; in _get_val()163 val &= clk_div_mask(divider->width); in clk_divider_recalc_rate()409 val &= clk_div_mask(divider->width); in clk_divider_determine_rate()433 return min_t(unsigned int, value, clk_div_mask(width)); in divider_get_val()[all …]
383 val &= clk_div_mask(divider->width); in m10v_clk_divider_recalc_rate()399 val &= clk_div_mask(divider->width); in m10v_clk_divider_determine_rate()429 val &= ~(clk_div_mask(divider->width) << divider->shift); in m10v_clk_divider_set_rate()
601 val &= clk_div_mask(div->width); in bm1880_clk_div_recalc_rate()621 val &= clk_div_mask(div->width); in bm1880_clk_div_determine_rate()651 val &= ~(clk_div_mask(div->width) << div_hw->div.shift); in bm1880_clk_div_set_rate()
155 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()157 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()260 val &= clk_div_mask(cfg->width); in mpfs_cfg_clk_recalc_rate()286 mask = clk_div_mask(cfg->width) << cfg->shift; in mpfs_cfg_clk_set_rate()
82 mult &= clk_div_mask(MPFS_CCC_FBDIV_WIDTH); in mpfs_ccc_pll_recalc_rate()84 ref_div &= clk_div_mask(MPFS_CCC_REFDIV_WIDTH); in mpfs_ccc_pll_recalc_rate()
657 val &= clk_div_mask(divider->width); in sky1_audss_clk_divider_recalc_rate()675 val &= clk_div_mask(divider->width); in sky1_audss_clk_divider_determine_rate()707 val = clk_div_mask(divider->width) << (divider->shift + 16); in sky1_audss_clk_divider_set_rate()710 val &= ~(clk_div_mask(divider->width) << divider->shift); in sky1_audss_clk_divider_set_rate()
310 maxdiv = clk_div_mask(width); in _eswin_get_val()349 val &= ~(clk_div_mask(dclk->width) << dclk->shift); in clk_div_set_rate()365 val &= clk_div_mask(dclk->width); in clk_div_recalc_rate()
85 val &= clk_div_mask(divider->width); in ultrarisc_divider_recalc_rate()115 val &= ~(clk_div_mask(divider->width) << divider->shift); in ultrarisc_divider_set_rate()
246 div &= clk_div_mask(ddiv.width); in rzv2h_cpg_plldsi_div_recalc_rate()322 val &= ~(clk_div_mask(ddiv.width) << shift); in rzv2h_cpg_plldsi_div_set_rate()612 clk_hw_data->mux.mask = clk_div_mask(smux.width); in rzv2h_cpg_plldsi_smux_clk_register()757 val &= clk_div_mask(divider->width); in rzv2h_ddiv_recalc_rate()806 val &= ~(clk_div_mask(divider->width) << divider->shift); in rzv2h_ddiv_set_rate()
780 val &= ~(clk_div_mask(GET_WIDTH(dsi_div->conf)) << shift); in r9a09g077_cpg_lcdc_div_set_rate()796 div &= clk_div_mask(GET_WIDTH(dsi_div->conf)); in r9a09g077_cpg_lcdc_div_recalc_rate()
103 return (reg >> div->shift) & clk_div_mask(div->width); in sg2044_div_get_reg_div()168 reg &= ~(clk_div_mask(div->width) << div->shift); in sg2044_div_set_reg_div()
758 #define clk_div_mask(width) ((1 << (width)) - 1) macro