| /linux/drivers/sh/clk/ |
| H A D | cpg.c | 19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
29 static unsigned int sh_clk_read_status(struct clk *clk) in sh_clk_read_status() argument
31 void __iomem *mapped_status = (phys_addr_t)clk->status_reg - in sh_clk_read_status()
32 (phys_addr_t)clk->enable_reg + clk->mapped_reg; in sh_clk_read_status()
34 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read_status()
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| H A D | core.c | 39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
137 long clk_rate_table_round(struct clk *clk, in clk_rate_table_round() argument
143 .max = clk->nr_freqs - 1, in clk_rate_table_round()
149 if (clk->nr_freqs < 1) in clk_rate_table_round()
161 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, in clk_rate_div_range_round() argument
168 .arg = clk_get_parent(clk), in clk_rate_div_range_round()
181 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, in clk_rate_mult_range_round() argument
188 .arg = clk_get_parent(clk), in clk_rate_mult_range_round()
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| /linux/drivers/clk/mediatek/ |
| H A D | Makefile | 2 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…
3 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
5 obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg…
6 obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) += clk-mt6735-imgsys.o
7 obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) += clk-mt6735-mfgcfg.o
8 obj-$(CONFIG_COMMON_CLK_MT6735_VDECSYS) += clk-mt6735-vdecsys.o
9 obj-$(CONFIG_COMMON_CLK_MT6735_VENCSYS) += clk-mt6735-vencsys.o
10 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
11 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
12 obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o
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| /linux/drivers/clk/imx/ |
| H A D | clk-vf610.c | 113 static struct clk *clk[VF610_CLK_END]; variable
131 static struct clk * __init vf610_get_fixed_clock( in vf610_get_fixed_clock()
134 struct clk *clk = of_clk_get_by_name(ccm_node, name); in vf610_get_fixed_clock() local
137 if (IS_ERR(clk)) in vf610_get_fixed_clock()
138 clk = imx_obtain_fixed_clock(name, 0); in vf610_get_fixed_clock()
139 return clk; in vf610_get_fixed_clock()
188 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in vf610_clocks_init()
189 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); in vf610_clocks_init()
190 clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000); in vf610_clocks_init()
191 clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000); in vf610_clocks_init()
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| H A D | Makefile | 3 mxc-clk-objs += clk.o
4 mxc-clk-objs += clk-busy.o
5 mxc-clk-objs += clk-composite-7ulp.o
6 mxc-clk-objs += clk-composite-8m.o
7 mxc-clk-objs += clk-composite-93.o
8 mxc-clk-objs += clk-fracn-gppll.o
9 mxc-clk-objs += clk-cpu.o
10 mxc-clk-objs += clk-divider-gate.o
11 mxc-clk-objs += clk-fixup-div.o
12 mxc-clk-objs += clk-fixup-mux.o
[all …]
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| H A D | clk-imx27.c | 48 static struct clk *clk[IMX27_CLK_MAX]; variable
55 clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx27_clocks_init()
56 clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); in _mx27_clocks_init()
57 clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768); in _mx27_clocks_init()
58 clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); in _mx27_clocks_init()
59 clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); in _mx27_clocks_init()
60 clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); in _mx27_clocks_init()
61 …clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY… in _mx27_clocks_init()
62 …clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_… in _mx27_clocks_init()
63 clk[IMX27_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "mpll", "mpll_sel", CCM_MPCTL0); in _mx27_clocks_init()
[all …]
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| H A D | clk-imx25.c | 75 static struct clk *clk[clk_max]; variable
81 clk[dummy] = imx_clk_fixed("dummy", 0); in __mx25_clocks_init()
82 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); in __mx25_clocks_init()
83 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL)); in __mx25_clocks_init()
84 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); in __mx25_clocks_init()
85 …clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)… in __mx25_clocks_init()
86 clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2); in __mx25_clocks_init()
87 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
88 clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6); in __mx25_clocks_init()
89 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in __mx25_clocks_init()
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| H A D | clk-imx35.c | 82 static struct clk *clk[clk_max]; variable
106 clk[ckih] = imx_clk_fixed("ckih", 24000000); in _mx35_clocks_init()
107 clk[ckil] = imx_clk_fixed("ckil", 32768); in _mx35_clocks_init()
108 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); in _mx35_clocks_init()
109 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
111 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); in _mx35_clocks_init()
114 clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm); in _mx35_clocks_init()
116 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); in _mx35_clocks_init()
118 if (clk_get_rate(clk[arm]) > 400000000) in _mx35_clocks_init()
129 clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]); in _mx35_clocks_init()
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| H A D | clk-imx31.c | 50 static struct clk *clk[clk_max]; variable
55 clk[dummy] = imx_clk_fixed("dummy", 0); in _mx31_clocks_init()
56 clk[ckih] = imx_clk_fixed("ckih", fref); in _mx31_clocks_init()
57 clk[ckil] = imx_clk_fixed("ckil", 32768); in _mx31_clocks_init()
58 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); in _mx31_clocks_init()
59 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); in _mx31_clocks_init()
60 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL); in _mx31_clocks_init()
61 …clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_… in _mx31_clocks_init()
62 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3); in _mx31_clocks_init()
63 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); in _mx31_clocks_init()
[all …]
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| /linux/drivers/clk/spear/ |
| H A D | spear3xx_clock.c | 141 struct clk *clk; in spear300_clk_init() local
143 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, in spear300_clk_init()
145 clk_register_clkdev(clk, NULL, "60000000.clcd"); in spear300_clk_init()
147 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
149 clk_register_clkdev(clk, NULL, "94000000.flash"); in spear300_clk_init()
151 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
153 clk_register_clkdev(clk, NULL, "70000000.sdhci"); in spear300_clk_init()
155 clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1, in spear300_clk_init()
157 clk_register_clkdev(clk, NULL, "a9000000.gpio"); in spear300_clk_init()
159 clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1, in spear300_clk_init()
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| H A D | spear1310_clock.c | 384 struct clk *clk, *clk1; in spear1310_clk_init() local
386 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear1310_clk_init()
387 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear1310_clk_init()
389 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000); in spear1310_clk_init()
390 clk_register_clkdev(clk, "osc_24m_clk", NULL); in spear1310_clk_init()
392 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000); in spear1310_clk_init()
393 clk_register_clkdev(clk, "osc_25m_clk", NULL); in spear1310_clk_init()
395 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000); in spear1310_clk_init()
396 clk_register_clkdev(clk, "gmii_pad_clk", NULL); in spear1310_clk_init()
398 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0, in spear1310_clk_init()
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| H A D | spear6xx_clock.c | 116 struct clk *clk, *clk1; in spear6xx_clk_init() local
118 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear6xx_clk_init()
119 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear6xx_clk_init()
121 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000); in spear6xx_clk_init()
122 clk_register_clkdev(clk, "osc_30m_clk", NULL); in spear6xx_clk_init()
125 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0, in spear6xx_clk_init()
127 clk_register_clkdev(clk, NULL, "rtc-spear"); in spear6xx_clk_init()
130 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, in spear6xx_clk_init()
132 clk_register_clkdev(clk, "pll3_clk", NULL); in spear6xx_clk_init()
134 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", in spear6xx_clk_init()
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| /linux/arch/mips/lantiq/ |
| H A D | clk.c | 27 static struct clk cpu_clk_generic[4];
38 struct clk *clk_get_cpu(void) in clk_get_cpu()
43 struct clk *clk_get_fpi(void) in clk_get_fpi()
49 struct clk *clk_get_io(void) in clk_get_io()
55 struct clk *clk_get_ppe(void) in clk_get_ppe()
61 static inline int clk_good(struct clk *clk) in clk_good() argument
63 return clk && !IS_ERR(clk); in clk_good()
66 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
68 if (unlikely(!clk_good(clk))) in clk_get_rate()
71 if (clk->rate != 0) in clk_get_rate()
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| /linux/arch/m68k/coldfire/ |
| H A D | clk.c | 31 void __clk_init_enabled(struct clk *clk) in __clk_init_enabled() argument
33 clk->enabled = 1; in __clk_init_enabled()
34 clk->clk_ops->enable(clk); in __clk_init_enabled()
37 void __clk_init_disabled(struct clk *clk) in __clk_init_disabled() argument
39 clk->enabled = 0; in __clk_init_disabled()
40 clk->clk_ops->disable(clk); in __clk_init_disabled()
43 static void __clk_enable0(struct clk *clk) in __clk_enable0() argument
45 __raw_writeb(clk->slot, MCFPM_PPMCR0); in __clk_enable0()
48 static void __clk_disable0(struct clk *clk) in __clk_disable0() argument
50 __raw_writeb(clk->slot, MCFPM_PPMSR0); in __clk_disable0()
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| /linux/drivers/clk/ux500/ |
| H A D | u8500_of_clk.c | 18 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
19 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22 #define PRCC_SHOW(clk, base, bit) \ argument
23 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
24 #define PRCC_PCLK_STORE(clk, base, bit) \ argument
25 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
26 #define PRCC_KCLK_STORE(clk, base, bit) \ argument
27 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
29 static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, in ux500_twocell_get()
32 struct clk **clk_data = data; in ux500_twocell_get()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | base.c | 41 nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, in nvkm_clk_adjust() argument
44 struct nvkm_bios *bios = clk->subdev.device->bios; in nvkm_clk_adjust()
79 nvkm_cstate_valid(struct nvkm_clk *clk, struct nvkm_cstate *cstate, in nvkm_cstate_valid() argument
82 const struct nvkm_domain *domain = clk->domains; in nvkm_cstate_valid()
83 struct nvkm_volt *volt = clk->subdev.device->volt; in nvkm_cstate_valid()
89 switch (clk->boost_mode) { in nvkm_cstate_valid()
91 if (clk->base_khz && freq > clk->base_khz) in nvkm_cstate_valid()
95 if (clk->boost_khz && freq > clk->boost_khz) in nvkm_cstate_valid()
112 nvkm_cstate_find_best(struct nvkm_clk *clk, struct nvkm_pstate *pstate, in nvkm_cstate_find_best() argument
115 struct nvkm_device *device = clk->subdev.device; in nvkm_cstate_find_best()
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| H A D | mcp77.c | 42 read_div(struct mcp77_clk *clk) in read_div() argument
44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
49 read_pll(struct mcp77_clk *clk, u32 base) in read_pll() argument
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll()
83 struct mcp77_clk *clk = mcp77_clk(base); in mcp77_clk_read() local
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
95 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4; in mcp77_clk_read()
97 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 2 / 3; in mcp77_clk_read()
100 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3); in mcp77_clk_read()
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mp-nominal.dtsi | 6 &clk {
7 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
8 <&clk IMX8MP_CLK_A53_CORE>,
9 <&clk IMX8MP_SYS_PLL3>,
10 <&clk IMX8MP_CLK_NOC>,
11 <&clk IMX8MP_CLK_NOC_IO>,
12 <&clk IMX8MP_CLK_GIC>;
13 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
14 <&clk IMX8MP_ARM_PLL_OUT>,
16 <&clk IMX8MP_SYS_PLL1_800M>,
[all …]
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| /linux/drivers/clk/ |
| H A D | Makefile | 3 obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o clkdev.o
4 obj-$(CONFIG_COMMON_CLK) += clk.o
5 obj-$(CONFIG_CLK_KUNIT_TEST) += clk-test.o
6 clk-test-y := clk_test.o \
23 obj-$(CONFIG_COMMON_CLK) += clk-divider.o
24 obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
25 obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
26 obj-$(CONFIG_CLK_FIXED_RATE_KUNIT_TEST) += clk-fixed-rate-test.o
27 clk-fixed-rate-test-y := clk-fixed-rate_test.o kunit_clk_fixed_rate_test.dtbo.o
28 obj-$(CONFIG_COMMON_CLK) += clk-gate.o
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| /linux/drivers/clk/rockchip/ |
| H A D | Makefile | 6 obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
8 clk-rockchip-y += clk.o
9 clk-rockchip-y += clk-pll.o
10 clk-rockchip-y += clk-cpu.o
11 clk-rockchip-y += clk-gate-grf.o
12 clk-rockchip-y += clk-half-divider.o
13 clk-rockchip-y += clk-inverter.o
14 clk-rockchip-y += clk-mmc-phase.o
15 clk-rockchip-y += clk-muxgrf.o
16 clk-rockchip-y += clk-ddr.o
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| /linux/rust/helpers/ |
| H A D | clk.c | 10 struct clk *rust_helper_clk_get(struct device *dev, const char *id) in rust_helper_clk_get()
15 void rust_helper_clk_put(struct clk *clk) in rust_helper_clk_put() argument
17 clk_put(clk); in rust_helper_clk_put()
20 int rust_helper_clk_enable(struct clk *clk) in rust_helper_clk_enable() argument
22 return clk_enable(clk); in rust_helper_clk_enable()
25 void rust_helper_clk_disable(struct clk *clk) in rust_helper_clk_disable() argument
27 clk_disable(clk); in rust_helper_clk_disable()
30 unsigned long rust_helper_clk_get_rate(struct clk *clk) in rust_helper_clk_get_rate() argument
32 return clk_get_rate(clk); in rust_helper_clk_get_rate()
35 int rust_helper_clk_set_rate(struct clk *clk, unsigned long rate) in rust_helper_clk_set_rate() argument
[all …]
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| /linux/kernel/time/ |
| H A D | posix-clock.c | 23 struct posix_clock *clk = pccontext->clk; in get_posix_clock() local
25 down_read(&clk->rwsem); in get_posix_clock()
27 if (!clk->zombie) in get_posix_clock()
28 return clk; in get_posix_clock()
30 up_read(&clk->rwsem); in get_posix_clock()
35 static void put_posix_clock(struct posix_clock *clk) in put_posix_clock() argument
37 up_read(&clk->rwsem); in put_posix_clock()
44 struct posix_clock *clk = get_posix_clock(fp); in posix_clock_read() local
47 if (!clk) in posix_clock_read()
50 if (clk->ops.read) in posix_clock_read()
[all …]
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| /linux/arch/mips/lantiq/xway/ |
| H A D | sysctrl.c | 189 static int cgu_enable(struct clk *clk) in cgu_enable() argument
191 ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr); in cgu_enable()
196 static void cgu_disable(struct clk *clk) in cgu_disable() argument
198 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr); in cgu_disable()
202 static int pmu_enable(struct clk *clk) in pmu_enable() argument
208 pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module)); in pmu_enable()
210 (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits))); in pmu_enable()
214 pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits, in pmu_enable()
215 PWDCR(clk->module)); in pmu_enable()
217 (pmu_r32(PWDSR(clk->module)) & clk->bits)); in pmu_enable()
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| /linux/arch/mips/bcm63xx/ |
| H A D | clk.c | 21 struct clk { struct
22 void (*set)(struct clk *, int); argument
31 static void clk_enable_unlocked(struct clk *clk) in clk_enable_unlocked() argument
33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
37 static void clk_disable_unlocked(struct clk *clk) in clk_disable_unlocked() argument
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
58 static void enet_misc_set(struct clk *clk, int enable) in enet_misc_set() argument
74 static struct clk clk_enet_misc = {
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| /linux/drivers/clk/ti/ |
| H A D | clkt_dflt.c | 50 static int _wait_idlest_generic(struct clk_hw_omap *clk, in _wait_idlest_generic() argument
85 static void _omap2_module_wait_ready(struct clk_hw_omap *clk) in _omap2_module_wait_ready() argument
93 if (clk->ops->find_companion) { in _omap2_module_wait_ready()
94 clk->ops->find_companion(clk, &companion_reg, &other_bit); in _omap2_module_wait_ready()
100 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); in _omap2_module_wait_ready()
105 _wait_idlest_generic(clk, &idlest_reg, (1 << idlest_bit), in _omap2_module_wait_ready()
106 idlest_val, clk_hw_get_name(&clk->hw)); in _omap2_module_wait_ready()
134 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, in omap2_clk_dflt_find_companion() argument
138 memcpy(other_reg, &clk->enable_reg, sizeof(*other_reg)); in omap2_clk_dflt_find_companion()
146 *other_bit = clk->enable_bit; in omap2_clk_dflt_find_companion()
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