1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2287e3f3fSJohn Crispin /*
3287e3f3fSJohn Crispin *
497b92108SJohn Crispin * Copyright (C) 2011-2012 John Crispin <john@phrozen.org>
5cab7b836SHauke Mehrtens * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
6287e3f3fSJohn Crispin */
7287e3f3fSJohn Crispin
8287e3f3fSJohn Crispin #include <linux/ioport.h>
9287e3f3fSJohn Crispin #include <linux/export.h>
10287e3f3fSJohn Crispin #include <linux/clkdev.h>
11758d2443SHauke Mehrtens #include <linux/spinlock.h>
12287e3f3fSJohn Crispin #include <linux/of.h>
13287e3f3fSJohn Crispin #include <linux/of_address.h>
14287e3f3fSJohn Crispin
15287e3f3fSJohn Crispin #include <lantiq_soc.h>
16287e3f3fSJohn Crispin
17287e3f3fSJohn Crispin #include "../clk.h"
18287e3f3fSJohn Crispin #include "../prom.h"
19287e3f3fSJohn Crispin
20758d2443SHauke Mehrtens /* clock control register for legacy */
21287e3f3fSJohn Crispin #define CGU_IFCCR 0x0018
22e29b72f5SJohn Crispin #define CGU_IFCCR_VR9 0x0024
23758d2443SHauke Mehrtens /* system clock register for legacy */
24287e3f3fSJohn Crispin #define CGU_SYS 0x0010
25287e3f3fSJohn Crispin /* pci control register */
26287e3f3fSJohn Crispin #define CGU_PCICR 0x0034
27e29b72f5SJohn Crispin #define CGU_PCICR_VR9 0x0038
28287e3f3fSJohn Crispin /* ephy configuration register */
29287e3f3fSJohn Crispin #define CGU_EPHY 0x10
30758d2443SHauke Mehrtens
31758d2443SHauke Mehrtens /* Legacy PMU register for ar9, ase, danube */
32287e3f3fSJohn Crispin /* power control register */
33287e3f3fSJohn Crispin #define PMU_PWDCR 0x1C
34287e3f3fSJohn Crispin /* power status register */
35287e3f3fSJohn Crispin #define PMU_PWDSR 0x20
36287e3f3fSJohn Crispin /* power control register */
37287e3f3fSJohn Crispin #define PMU_PWDCR1 0x24
38287e3f3fSJohn Crispin /* power status register */
39287e3f3fSJohn Crispin #define PMU_PWDSR1 0x28
40287e3f3fSJohn Crispin /* power control register */
41287e3f3fSJohn Crispin #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
42287e3f3fSJohn Crispin /* power status register */
43287e3f3fSJohn Crispin #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
44287e3f3fSJohn Crispin
45758d2443SHauke Mehrtens
46758d2443SHauke Mehrtens /* PMU register for ar10 and grx390 */
47758d2443SHauke Mehrtens
48758d2443SHauke Mehrtens /* First register set */
49758d2443SHauke Mehrtens #define PMU_CLK_SR 0x20 /* status */
50758d2443SHauke Mehrtens #define PMU_CLK_CR_A 0x24 /* Enable */
51758d2443SHauke Mehrtens #define PMU_CLK_CR_B 0x28 /* Disable */
52758d2443SHauke Mehrtens /* Second register set */
53758d2443SHauke Mehrtens #define PMU_CLK_SR1 0x30 /* status */
54758d2443SHauke Mehrtens #define PMU_CLK_CR1_A 0x34 /* Enable */
55758d2443SHauke Mehrtens #define PMU_CLK_CR1_B 0x38 /* Disable */
56758d2443SHauke Mehrtens /* Third register set */
57758d2443SHauke Mehrtens #define PMU_ANA_SR 0x40 /* status */
58758d2443SHauke Mehrtens #define PMU_ANA_CR_A 0x44 /* Enable */
59758d2443SHauke Mehrtens #define PMU_ANA_CR_B 0x48 /* Disable */
60758d2443SHauke Mehrtens
61758d2443SHauke Mehrtens /* Status */
62758d2443SHauke Mehrtens static u32 pmu_clk_sr[] = {
63758d2443SHauke Mehrtens PMU_CLK_SR,
64758d2443SHauke Mehrtens PMU_CLK_SR1,
65758d2443SHauke Mehrtens PMU_ANA_SR,
66758d2443SHauke Mehrtens };
67758d2443SHauke Mehrtens
68758d2443SHauke Mehrtens /* Enable */
69758d2443SHauke Mehrtens static u32 pmu_clk_cr_a[] = {
70758d2443SHauke Mehrtens PMU_CLK_CR_A,
71758d2443SHauke Mehrtens PMU_CLK_CR1_A,
72758d2443SHauke Mehrtens PMU_ANA_CR_A,
73758d2443SHauke Mehrtens };
74758d2443SHauke Mehrtens
75758d2443SHauke Mehrtens /* Disable */
76758d2443SHauke Mehrtens static u32 pmu_clk_cr_b[] = {
77758d2443SHauke Mehrtens PMU_CLK_CR_B,
78758d2443SHauke Mehrtens PMU_CLK_CR1_B,
79758d2443SHauke Mehrtens PMU_ANA_CR_B,
80758d2443SHauke Mehrtens };
81758d2443SHauke Mehrtens
82758d2443SHauke Mehrtens #define PWDCR_EN_XRX(x) (pmu_clk_cr_a[(x)])
83758d2443SHauke Mehrtens #define PWDCR_DIS_XRX(x) (pmu_clk_cr_b[(x)])
84758d2443SHauke Mehrtens #define PWDSR_XRX(x) (pmu_clk_sr[(x)])
85758d2443SHauke Mehrtens
86287e3f3fSJohn Crispin /* clock gates that we can en/disable */
87287e3f3fSJohn Crispin #define PMU_USB0_P BIT(0)
88e182c98aSHauke Mehrtens #define PMU_ASE_SDIO BIT(2) /* ASE special */
89287e3f3fSJohn Crispin #define PMU_PCI BIT(4)
90009d6914SJohn Crispin #define PMU_DMA BIT(5)
91287e3f3fSJohn Crispin #define PMU_USB0 BIT(6)
92287e3f3fSJohn Crispin #define PMU_ASC0 BIT(7)
93287e3f3fSJohn Crispin #define PMU_EPHY BIT(7) /* ase */
94e182c98aSHauke Mehrtens #define PMU_USIF BIT(7) /* from vr9 until grx390 */
95287e3f3fSJohn Crispin #define PMU_SPI BIT(8)
96287e3f3fSJohn Crispin #define PMU_DFE BIT(9)
97287e3f3fSJohn Crispin #define PMU_EBU BIT(10)
98287e3f3fSJohn Crispin #define PMU_STP BIT(11)
99009d6914SJohn Crispin #define PMU_GPT BIT(12)
100287e3f3fSJohn Crispin #define PMU_AHBS BIT(13) /* vr9 */
101009d6914SJohn Crispin #define PMU_FPI BIT(14)
102287e3f3fSJohn Crispin #define PMU_AHBM BIT(15)
103e182c98aSHauke Mehrtens #define PMU_SDIO BIT(16) /* danube, ar9, vr9 */
104287e3f3fSJohn Crispin #define PMU_ASC1 BIT(17)
105287e3f3fSJohn Crispin #define PMU_PPE_QSB BIT(18)
106287e3f3fSJohn Crispin #define PMU_PPE_SLL01 BIT(19)
107e71f6d35SHauke Mehrtens #define PMU_DEU BIT(20)
108287e3f3fSJohn Crispin #define PMU_PPE_TC BIT(21)
109287e3f3fSJohn Crispin #define PMU_PPE_EMA BIT(22)
110287e3f3fSJohn Crispin #define PMU_PPE_DPLUM BIT(23)
111d0b991e3SHauke Mehrtens #define PMU_PPE_DP BIT(23)
112287e3f3fSJohn Crispin #define PMU_PPE_DPLUS BIT(24)
113287e3f3fSJohn Crispin #define PMU_USB1_P BIT(26)
11458c9e247SAleksander Jan Bajkowski #define PMU_GPHY3 BIT(26) /* grx390 */
115287e3f3fSJohn Crispin #define PMU_USB1 BIT(27)
116009d6914SJohn Crispin #define PMU_SWITCH BIT(28)
117287e3f3fSJohn Crispin #define PMU_PPE_TOP BIT(29)
11858c9e247SAleksander Jan Bajkowski #define PMU_GPHY0 BIT(29) /* ar10, xrx390 */
119287e3f3fSJohn Crispin #define PMU_GPHY BIT(30)
12058c9e247SAleksander Jan Bajkowski #define PMU_GPHY1 BIT(30) /* ar10, xrx390 */
121287e3f3fSJohn Crispin #define PMU_PCIE_CLK BIT(31)
12258c9e247SAleksander Jan Bajkowski #define PMU_GPHY2 BIT(31) /* ar10, xrx390 */
123287e3f3fSJohn Crispin
124d0b991e3SHauke Mehrtens #define PMU1_PCIE_PHY BIT(0) /* vr9-specific,moved in ar10/grx390 */
125287e3f3fSJohn Crispin #define PMU1_PCIE_CTL BIT(1)
126287e3f3fSJohn Crispin #define PMU1_PCIE_PDI BIT(4)
127287e3f3fSJohn Crispin #define PMU1_PCIE_MSI BIT(5)
128d0b991e3SHauke Mehrtens #define PMU1_CKE BIT(6)
129d0b991e3SHauke Mehrtens #define PMU1_PCIE1_CTL BIT(17)
130d0b991e3SHauke Mehrtens #define PMU1_PCIE1_PDI BIT(20)
131d0b991e3SHauke Mehrtens #define PMU1_PCIE1_MSI BIT(21)
132d0b991e3SHauke Mehrtens #define PMU1_PCIE2_CTL BIT(25)
133d0b991e3SHauke Mehrtens #define PMU1_PCIE2_PDI BIT(26)
134d0b991e3SHauke Mehrtens #define PMU1_PCIE2_MSI BIT(27)
135d0b991e3SHauke Mehrtens
136d0b991e3SHauke Mehrtens #define PMU_ANALOG_USB0_P BIT(0)
137d0b991e3SHauke Mehrtens #define PMU_ANALOG_USB1_P BIT(1)
138d0b991e3SHauke Mehrtens #define PMU_ANALOG_PCIE0_P BIT(8)
139d0b991e3SHauke Mehrtens #define PMU_ANALOG_PCIE1_P BIT(9)
140d0b991e3SHauke Mehrtens #define PMU_ANALOG_PCIE2_P BIT(10)
141d0b991e3SHauke Mehrtens #define PMU_ANALOG_DSL_AFE BIT(16)
142d0b991e3SHauke Mehrtens #define PMU_ANALOG_DCDC_2V5 BIT(17)
143d0b991e3SHauke Mehrtens #define PMU_ANALOG_DCDC_1VX BIT(18)
144d0b991e3SHauke Mehrtens #define PMU_ANALOG_DCDC_1V0 BIT(19)
145287e3f3fSJohn Crispin
146287e3f3fSJohn Crispin #define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y))
147287e3f3fSJohn Crispin #define pmu_r32(x) ltq_r32(pmu_membase + (x))
148287e3f3fSJohn Crispin
149287e3f3fSJohn Crispin static void __iomem *pmu_membase;
150287e3f3fSJohn Crispin void __iomem *ltq_cgu_membase;
151287e3f3fSJohn Crispin void __iomem *ltq_ebu_membase;
152287e3f3fSJohn Crispin
153e29b72f5SJohn Crispin static u32 ifccr = CGU_IFCCR;
154e29b72f5SJohn Crispin static u32 pcicr = CGU_PCICR;
155e29b72f5SJohn Crispin
156cab7b836SHauke Mehrtens static DEFINE_SPINLOCK(g_pmu_lock);
157cab7b836SHauke Mehrtens
158287e3f3fSJohn Crispin /* legacy function kept alive to ease clkdev transition */
ltq_pmu_enable(unsigned int module)159287e3f3fSJohn Crispin void ltq_pmu_enable(unsigned int module)
160287e3f3fSJohn Crispin {
161cab7b836SHauke Mehrtens int retry = 1000000;
162287e3f3fSJohn Crispin
163cab7b836SHauke Mehrtens spin_lock(&g_pmu_lock);
164287e3f3fSJohn Crispin pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR);
165cab7b836SHauke Mehrtens do {} while (--retry && (pmu_r32(PMU_PWDSR) & module));
166cab7b836SHauke Mehrtens spin_unlock(&g_pmu_lock);
167287e3f3fSJohn Crispin
168cab7b836SHauke Mehrtens if (!retry)
169287e3f3fSJohn Crispin panic("activating PMU module failed!");
170287e3f3fSJohn Crispin }
171287e3f3fSJohn Crispin EXPORT_SYMBOL(ltq_pmu_enable);
172287e3f3fSJohn Crispin
173287e3f3fSJohn Crispin /* legacy function kept alive to ease clkdev transition */
ltq_pmu_disable(unsigned int module)174287e3f3fSJohn Crispin void ltq_pmu_disable(unsigned int module)
175287e3f3fSJohn Crispin {
176cab7b836SHauke Mehrtens int retry = 1000000;
177cab7b836SHauke Mehrtens
178cab7b836SHauke Mehrtens spin_lock(&g_pmu_lock);
179287e3f3fSJohn Crispin pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR);
180cab7b836SHauke Mehrtens do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module)));
181cab7b836SHauke Mehrtens spin_unlock(&g_pmu_lock);
182cab7b836SHauke Mehrtens
183cab7b836SHauke Mehrtens if (!retry)
184cab7b836SHauke Mehrtens pr_warn("deactivating PMU module failed!");
185287e3f3fSJohn Crispin }
186287e3f3fSJohn Crispin EXPORT_SYMBOL(ltq_pmu_disable);
187287e3f3fSJohn Crispin
188287e3f3fSJohn Crispin /* enable a hw clock */
cgu_enable(struct clk * clk)189287e3f3fSJohn Crispin static int cgu_enable(struct clk *clk)
190287e3f3fSJohn Crispin {
191e29b72f5SJohn Crispin ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
192287e3f3fSJohn Crispin return 0;
193287e3f3fSJohn Crispin }
194287e3f3fSJohn Crispin
195287e3f3fSJohn Crispin /* disable a hw clock */
cgu_disable(struct clk * clk)196287e3f3fSJohn Crispin static void cgu_disable(struct clk *clk)
197287e3f3fSJohn Crispin {
198e29b72f5SJohn Crispin ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
199287e3f3fSJohn Crispin }
200287e3f3fSJohn Crispin
201287e3f3fSJohn Crispin /* enable a clock gate */
pmu_enable(struct clk * clk)202287e3f3fSJohn Crispin static int pmu_enable(struct clk *clk)
203287e3f3fSJohn Crispin {
204287e3f3fSJohn Crispin int retry = 1000000;
205287e3f3fSJohn Crispin
206758d2443SHauke Mehrtens if (of_machine_is_compatible("lantiq,ar10")
207758d2443SHauke Mehrtens || of_machine_is_compatible("lantiq,grx390")) {
208758d2443SHauke Mehrtens pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module));
209758d2443SHauke Mehrtens do {} while (--retry &&
210758d2443SHauke Mehrtens (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)));
211758d2443SHauke Mehrtens
212758d2443SHauke Mehrtens } else {
213cab7b836SHauke Mehrtens spin_lock(&g_pmu_lock);
214287e3f3fSJohn Crispin pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
215287e3f3fSJohn Crispin PWDCR(clk->module));
216758d2443SHauke Mehrtens do {} while (--retry &&
217758d2443SHauke Mehrtens (pmu_r32(PWDSR(clk->module)) & clk->bits));
218cab7b836SHauke Mehrtens spin_unlock(&g_pmu_lock);
219758d2443SHauke Mehrtens }
220287e3f3fSJohn Crispin
221287e3f3fSJohn Crispin if (!retry)
222f7777dccSRalf Baechle panic("activating PMU module failed!");
223287e3f3fSJohn Crispin
224287e3f3fSJohn Crispin return 0;
225287e3f3fSJohn Crispin }
226287e3f3fSJohn Crispin
227287e3f3fSJohn Crispin /* disable a clock gate */
pmu_disable(struct clk * clk)228287e3f3fSJohn Crispin static void pmu_disable(struct clk *clk)
229287e3f3fSJohn Crispin {
230cab7b836SHauke Mehrtens int retry = 1000000;
231cab7b836SHauke Mehrtens
232758d2443SHauke Mehrtens if (of_machine_is_compatible("lantiq,ar10")
233758d2443SHauke Mehrtens || of_machine_is_compatible("lantiq,grx390")) {
234758d2443SHauke Mehrtens pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module));
235758d2443SHauke Mehrtens do {} while (--retry &&
236758d2443SHauke Mehrtens (pmu_r32(PWDSR_XRX(clk->module)) & clk->bits));
237758d2443SHauke Mehrtens } else {
238cab7b836SHauke Mehrtens spin_lock(&g_pmu_lock);
239758d2443SHauke Mehrtens pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
240758d2443SHauke Mehrtens PWDCR(clk->module));
241758d2443SHauke Mehrtens do {} while (--retry &&
242758d2443SHauke Mehrtens (!(pmu_r32(PWDSR(clk->module)) & clk->bits)));
243cab7b836SHauke Mehrtens spin_unlock(&g_pmu_lock);
244758d2443SHauke Mehrtens }
245cab7b836SHauke Mehrtens
246cab7b836SHauke Mehrtens if (!retry)
247cab7b836SHauke Mehrtens pr_warn("deactivating PMU module failed!");
248287e3f3fSJohn Crispin }
249287e3f3fSJohn Crispin
usb_set_clock(void)250*9c7a86c9SHauke Mehrtens static void usb_set_clock(void)
251*9c7a86c9SHauke Mehrtens {
252*9c7a86c9SHauke Mehrtens unsigned int val = ltq_cgu_r32(ifccr);
253*9c7a86c9SHauke Mehrtens
254*9c7a86c9SHauke Mehrtens if (of_machine_is_compatible("lantiq,ar10") ||
255*9c7a86c9SHauke Mehrtens of_machine_is_compatible("lantiq,grx390")) {
256*9c7a86c9SHauke Mehrtens val &= ~0x03; /* XTAL divided by 3 */
257*9c7a86c9SHauke Mehrtens } else if (of_machine_is_compatible("lantiq,ar9") ||
258*9c7a86c9SHauke Mehrtens of_machine_is_compatible("lantiq,vr9")) {
259*9c7a86c9SHauke Mehrtens /* TODO: this depends on the XTAL frequency */
260*9c7a86c9SHauke Mehrtens val |= 0x03; /* XTAL divided by 3 */
261*9c7a86c9SHauke Mehrtens } else if (of_machine_is_compatible("lantiq,ase")) {
262*9c7a86c9SHauke Mehrtens val |= 0x20; /* from XTAL */
263*9c7a86c9SHauke Mehrtens } else if (of_machine_is_compatible("lantiq,danube")) {
264*9c7a86c9SHauke Mehrtens val |= 0x30; /* 12 MHz, generated from 36 MHz */
265*9c7a86c9SHauke Mehrtens }
266*9c7a86c9SHauke Mehrtens ltq_cgu_w32(val, ifccr);
267*9c7a86c9SHauke Mehrtens }
268*9c7a86c9SHauke Mehrtens
269287e3f3fSJohn Crispin /* the pci enable helper */
pci_enable(struct clk * clk)270287e3f3fSJohn Crispin static int pci_enable(struct clk *clk)
271287e3f3fSJohn Crispin {
272e29b72f5SJohn Crispin unsigned int val = ltq_cgu_r32(ifccr);
273287e3f3fSJohn Crispin /* set bus clock speed */
274f40e1f9dSJohn Crispin if (of_machine_is_compatible("lantiq,ar9") ||
275f40e1f9dSJohn Crispin of_machine_is_compatible("lantiq,vr9")) {
276e29b72f5SJohn Crispin val &= ~0x1f00000;
277287e3f3fSJohn Crispin if (clk->rate == CLOCK_33M)
278e29b72f5SJohn Crispin val |= 0xe00000;
279287e3f3fSJohn Crispin else
280e29b72f5SJohn Crispin val |= 0x700000; /* 62.5M */
281287e3f3fSJohn Crispin } else {
282e29b72f5SJohn Crispin val &= ~0xf00000;
283287e3f3fSJohn Crispin if (clk->rate == CLOCK_33M)
284e29b72f5SJohn Crispin val |= 0x800000;
285287e3f3fSJohn Crispin else
286e29b72f5SJohn Crispin val |= 0x400000; /* 62.5M */
287287e3f3fSJohn Crispin }
288e29b72f5SJohn Crispin ltq_cgu_w32(val, ifccr);
289287e3f3fSJohn Crispin pmu_enable(clk);
290287e3f3fSJohn Crispin return 0;
291287e3f3fSJohn Crispin }
292287e3f3fSJohn Crispin
293287e3f3fSJohn Crispin /* enable the external clock as a source */
pci_ext_enable(struct clk * clk)294287e3f3fSJohn Crispin static int pci_ext_enable(struct clk *clk)
295287e3f3fSJohn Crispin {
296e29b72f5SJohn Crispin ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
297e29b72f5SJohn Crispin ltq_cgu_w32((1 << 30), pcicr);
298287e3f3fSJohn Crispin return 0;
299287e3f3fSJohn Crispin }
300287e3f3fSJohn Crispin
301287e3f3fSJohn Crispin /* disable the external clock as a source */
pci_ext_disable(struct clk * clk)302287e3f3fSJohn Crispin static void pci_ext_disable(struct clk *clk)
303287e3f3fSJohn Crispin {
304e29b72f5SJohn Crispin ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
305e29b72f5SJohn Crispin ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
306287e3f3fSJohn Crispin }
307287e3f3fSJohn Crispin
308287e3f3fSJohn Crispin /* enable a clockout source */
clkout_enable(struct clk * clk)309287e3f3fSJohn Crispin static int clkout_enable(struct clk *clk)
310287e3f3fSJohn Crispin {
311287e3f3fSJohn Crispin int i;
312287e3f3fSJohn Crispin
313287e3f3fSJohn Crispin /* get the correct rate */
314287e3f3fSJohn Crispin for (i = 0; i < 4; i++) {
315287e3f3fSJohn Crispin if (clk->rates[i] == clk->rate) {
316287e3f3fSJohn Crispin int shift = 14 - (2 * clk->module);
31798dbc576SJohn Crispin int enable = 7 - clk->module;
318e29b72f5SJohn Crispin unsigned int val = ltq_cgu_r32(ifccr);
319287e3f3fSJohn Crispin
320e29b72f5SJohn Crispin val &= ~(3 << shift);
321e29b72f5SJohn Crispin val |= i << shift;
32298dbc576SJohn Crispin val |= enable;
323e29b72f5SJohn Crispin ltq_cgu_w32(val, ifccr);
324287e3f3fSJohn Crispin return 0;
325287e3f3fSJohn Crispin }
326287e3f3fSJohn Crispin }
327287e3f3fSJohn Crispin return -1;
328287e3f3fSJohn Crispin }
329287e3f3fSJohn Crispin
330287e3f3fSJohn Crispin /* manage the clock gates via PMU */
clkdev_add_pmu(const char * dev,const char * con,bool deactivate,unsigned int module,unsigned int bits)33195135bfaSHauke Mehrtens static void clkdev_add_pmu(const char *dev, const char *con, bool deactivate,
332287e3f3fSJohn Crispin unsigned int module, unsigned int bits)
333287e3f3fSJohn Crispin {
334287e3f3fSJohn Crispin struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
335287e3f3fSJohn Crispin
33634123208SXiaoke Wang if (!clk)
33734123208SXiaoke Wang return;
338287e3f3fSJohn Crispin clk->cl.dev_id = dev;
339287e3f3fSJohn Crispin clk->cl.con_id = con;
340287e3f3fSJohn Crispin clk->cl.clk = clk;
341287e3f3fSJohn Crispin clk->enable = pmu_enable;
342287e3f3fSJohn Crispin clk->disable = pmu_disable;
343287e3f3fSJohn Crispin clk->module = module;
344287e3f3fSJohn Crispin clk->bits = bits;
34595135bfaSHauke Mehrtens if (deactivate) {
34695135bfaSHauke Mehrtens /*
34795135bfaSHauke Mehrtens * Disable it during the initialization. Module should enable
34895135bfaSHauke Mehrtens * when used
34995135bfaSHauke Mehrtens */
35095135bfaSHauke Mehrtens pmu_disable(clk);
35195135bfaSHauke Mehrtens }
352287e3f3fSJohn Crispin clkdev_add(&clk->cl);
353287e3f3fSJohn Crispin }
354287e3f3fSJohn Crispin
355287e3f3fSJohn Crispin /* manage the clock generator */
clkdev_add_cgu(const char * dev,const char * con,unsigned int bits)356287e3f3fSJohn Crispin static void clkdev_add_cgu(const char *dev, const char *con,
357287e3f3fSJohn Crispin unsigned int bits)
358287e3f3fSJohn Crispin {
359287e3f3fSJohn Crispin struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
360287e3f3fSJohn Crispin
36134123208SXiaoke Wang if (!clk)
36234123208SXiaoke Wang return;
363287e3f3fSJohn Crispin clk->cl.dev_id = dev;
364287e3f3fSJohn Crispin clk->cl.con_id = con;
365287e3f3fSJohn Crispin clk->cl.clk = clk;
366287e3f3fSJohn Crispin clk->enable = cgu_enable;
367287e3f3fSJohn Crispin clk->disable = cgu_disable;
368287e3f3fSJohn Crispin clk->bits = bits;
369287e3f3fSJohn Crispin clkdev_add(&clk->cl);
370287e3f3fSJohn Crispin }
371287e3f3fSJohn Crispin
372287e3f3fSJohn Crispin /* pci needs its own enable function as the setup is a bit more complex */
373287e3f3fSJohn Crispin static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0};
374287e3f3fSJohn Crispin
clkdev_add_pci(void)375287e3f3fSJohn Crispin static void clkdev_add_pci(void)
376287e3f3fSJohn Crispin {
377287e3f3fSJohn Crispin struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
378287e3f3fSJohn Crispin struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
379287e3f3fSJohn Crispin
380287e3f3fSJohn Crispin /* main pci clock */
38134123208SXiaoke Wang if (clk) {
382287e3f3fSJohn Crispin clk->cl.dev_id = "17000000.pci";
383287e3f3fSJohn Crispin clk->cl.con_id = NULL;
384287e3f3fSJohn Crispin clk->cl.clk = clk;
385287e3f3fSJohn Crispin clk->rate = CLOCK_33M;
386287e3f3fSJohn Crispin clk->rates = valid_pci_rates;
387287e3f3fSJohn Crispin clk->enable = pci_enable;
388287e3f3fSJohn Crispin clk->disable = pmu_disable;
389287e3f3fSJohn Crispin clk->module = 0;
390287e3f3fSJohn Crispin clk->bits = PMU_PCI;
391287e3f3fSJohn Crispin clkdev_add(&clk->cl);
39234123208SXiaoke Wang }
393287e3f3fSJohn Crispin
394287e3f3fSJohn Crispin /* use internal/external bus clock */
39534123208SXiaoke Wang if (clk_ext) {
396287e3f3fSJohn Crispin clk_ext->cl.dev_id = "17000000.pci";
397287e3f3fSJohn Crispin clk_ext->cl.con_id = "external";
398287e3f3fSJohn Crispin clk_ext->cl.clk = clk_ext;
399287e3f3fSJohn Crispin clk_ext->enable = pci_ext_enable;
400287e3f3fSJohn Crispin clk_ext->disable = pci_ext_disable;
401287e3f3fSJohn Crispin clkdev_add(&clk_ext->cl);
402287e3f3fSJohn Crispin }
40334123208SXiaoke Wang }
404287e3f3fSJohn Crispin
405287e3f3fSJohn Crispin /* xway socs can generate clocks on gpio pins */
406287e3f3fSJohn Crispin static unsigned long valid_clkout_rates[4][5] = {
407287e3f3fSJohn Crispin {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
408287e3f3fSJohn Crispin {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0},
409287e3f3fSJohn Crispin {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0},
410287e3f3fSJohn Crispin {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0},
411287e3f3fSJohn Crispin };
412287e3f3fSJohn Crispin
clkdev_add_clkout(void)413287e3f3fSJohn Crispin static void clkdev_add_clkout(void)
414287e3f3fSJohn Crispin {
415287e3f3fSJohn Crispin int i;
416287e3f3fSJohn Crispin
417287e3f3fSJohn Crispin for (i = 0; i < 4; i++) {
418287e3f3fSJohn Crispin struct clk *clk;
419287e3f3fSJohn Crispin char *name;
420287e3f3fSJohn Crispin
421287e3f3fSJohn Crispin name = kzalloc(sizeof("clkout0"), GFP_KERNEL);
42234123208SXiaoke Wang if (!name)
42334123208SXiaoke Wang continue;
424287e3f3fSJohn Crispin sprintf(name, "clkout%d", i);
425287e3f3fSJohn Crispin
426287e3f3fSJohn Crispin clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
42734123208SXiaoke Wang if (!clk) {
42834123208SXiaoke Wang kfree(name);
42934123208SXiaoke Wang continue;
43034123208SXiaoke Wang }
431287e3f3fSJohn Crispin clk->cl.dev_id = "1f103000.cgu";
432287e3f3fSJohn Crispin clk->cl.con_id = name;
433287e3f3fSJohn Crispin clk->cl.clk = clk;
434287e3f3fSJohn Crispin clk->rate = 0;
435287e3f3fSJohn Crispin clk->rates = valid_clkout_rates[i];
436287e3f3fSJohn Crispin clk->enable = clkout_enable;
437287e3f3fSJohn Crispin clk->module = i;
438287e3f3fSJohn Crispin clkdev_add(&clk->cl);
439287e3f3fSJohn Crispin }
440287e3f3fSJohn Crispin }
441287e3f3fSJohn Crispin
442287e3f3fSJohn Crispin /* bring up all register ranges that we need for basic system control */
ltq_soc_init(void)443287e3f3fSJohn Crispin void __init ltq_soc_init(void)
444287e3f3fSJohn Crispin {
445287e3f3fSJohn Crispin struct resource res_pmu, res_cgu, res_ebu;
446287e3f3fSJohn Crispin struct device_node *np_pmu =
447287e3f3fSJohn Crispin of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");
448287e3f3fSJohn Crispin struct device_node *np_cgu =
449287e3f3fSJohn Crispin of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");
450287e3f3fSJohn Crispin struct device_node *np_ebu =
451287e3f3fSJohn Crispin of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");
452287e3f3fSJohn Crispin
453287e3f3fSJohn Crispin /* check if all the core register ranges are available */
454287e3f3fSJohn Crispin if (!np_pmu || !np_cgu || !np_ebu)
4553d18c17eSJohn Crispin panic("Failed to load core nodes from devicetree");
456287e3f3fSJohn Crispin
457287e3f3fSJohn Crispin if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
458287e3f3fSJohn Crispin of_address_to_resource(np_cgu, 0, &res_cgu) ||
459287e3f3fSJohn Crispin of_address_to_resource(np_ebu, 0, &res_ebu))
460287e3f3fSJohn Crispin panic("Failed to get core resources");
461287e3f3fSJohn Crispin
46276695592SLiang He of_node_put(np_pmu);
46376695592SLiang He of_node_put(np_cgu);
46476695592SLiang He of_node_put(np_ebu);
46576695592SLiang He
4666e807852SHauke Mehrtens if (!request_mem_region(res_pmu.start, resource_size(&res_pmu),
4676e807852SHauke Mehrtens res_pmu.name) ||
4686e807852SHauke Mehrtens !request_mem_region(res_cgu.start, resource_size(&res_cgu),
4696e807852SHauke Mehrtens res_cgu.name) ||
4706e807852SHauke Mehrtens !request_mem_region(res_ebu.start, resource_size(&res_ebu),
4716e807852SHauke Mehrtens res_ebu.name))
4721a84db56SMasanari Iida pr_err("Failed to request core resources");
473287e3f3fSJohn Crispin
4744bdc0d67SChristoph Hellwig pmu_membase = ioremap(res_pmu.start, resource_size(&res_pmu));
4754bdc0d67SChristoph Hellwig ltq_cgu_membase = ioremap(res_cgu.start,
476287e3f3fSJohn Crispin resource_size(&res_cgu));
4774bdc0d67SChristoph Hellwig ltq_ebu_membase = ioremap(res_ebu.start,
478287e3f3fSJohn Crispin resource_size(&res_ebu));
479287e3f3fSJohn Crispin if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
480287e3f3fSJohn Crispin panic("Failed to remap core resources");
481287e3f3fSJohn Crispin
482287e3f3fSJohn Crispin /* make sure to unprotect the memory region where flash is located */
483287e3f3fSJohn Crispin ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
484287e3f3fSJohn Crispin
485287e3f3fSJohn Crispin /* add our generic xway clocks */
48695135bfaSHauke Mehrtens clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
48795135bfaSHauke Mehrtens clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
48895135bfaSHauke Mehrtens clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
48944a374c0SMartin Schiller clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
49095135bfaSHauke Mehrtens clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
49195135bfaSHauke Mehrtens clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
49295135bfaSHauke Mehrtens clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
493287e3f3fSJohn Crispin clkdev_add_clkout();
494287e3f3fSJohn Crispin
495287e3f3fSJohn Crispin /* add the soc dependent clocks */
496e29b72f5SJohn Crispin if (of_machine_is_compatible("lantiq,vr9")) {
497e29b72f5SJohn Crispin ifccr = CGU_IFCCR_VR9;
498e29b72f5SJohn Crispin pcicr = CGU_PCICR_VR9;
499e29b72f5SJohn Crispin } else {
50095135bfaSHauke Mehrtens clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE);
501e29b72f5SJohn Crispin }
502287e3f3fSJohn Crispin
50344a374c0SMartin Schiller if (!of_machine_is_compatible("lantiq,ase"))
504287e3f3fSJohn Crispin clkdev_add_pci();
505287e3f3fSJohn Crispin
506d0b991e3SHauke Mehrtens if (of_machine_is_compatible("lantiq,grx390") ||
507d0b991e3SHauke Mehrtens of_machine_is_compatible("lantiq,ar10")) {
50858c9e247SAleksander Jan Bajkowski clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY0);
50958c9e247SAleksander Jan Bajkowski clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY1);
51058c9e247SAleksander Jan Bajkowski clkdev_add_pmu("1e108000.switch", "gphy2", 0, 0, PMU_GPHY2);
511dea54fbaSHauke Mehrtens clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB0_P);
512dea54fbaSHauke Mehrtens clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB1_P);
513d0b991e3SHauke Mehrtens /* rc 0 */
514ed90302bSMartin Blumenstingl clkdev_add_pmu("1f106800.phy", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
515d0b991e3SHauke Mehrtens clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
516ed90302bSMartin Blumenstingl clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI);
517d0b991e3SHauke Mehrtens clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
518d0b991e3SHauke Mehrtens /* rc 1 */
519ed90302bSMartin Blumenstingl clkdev_add_pmu("1f700400.phy", "phy", 1, 2, PMU_ANALOG_PCIE1_P);
520d0b991e3SHauke Mehrtens clkdev_add_pmu("19000000.pcie", "msi", 1, 1, PMU1_PCIE1_MSI);
521ed90302bSMartin Blumenstingl clkdev_add_pmu("1f700400.phy", "pdi", 1, 1, PMU1_PCIE1_PDI);
522d0b991e3SHauke Mehrtens clkdev_add_pmu("19000000.pcie", "ctl", 1, 1, PMU1_PCIE1_CTL);
523d0b991e3SHauke Mehrtens }
524d0b991e3SHauke Mehrtens
525287e3f3fSJohn Crispin if (of_machine_is_compatible("lantiq,ase")) {
526287e3f3fSJohn Crispin if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
527740c606eSJohn Crispin clkdev_add_static(CLOCK_266M, CLOCK_133M,
528740c606eSJohn Crispin CLOCK_133M, CLOCK_266M);
529287e3f3fSJohn Crispin else
530740c606eSJohn Crispin clkdev_add_static(CLOCK_133M, CLOCK_133M,
531740c606eSJohn Crispin CLOCK_133M, CLOCK_133M);
532dea54fbaSHauke Mehrtens clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
533dea54fbaSHauke Mehrtens clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
534e182c98aSHauke Mehrtens clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
535e182c98aSHauke Mehrtens clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
53695135bfaSHauke Mehrtens clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
537e182c98aSHauke Mehrtens clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_ASE_SDIO);
538a3a68534SHauke Mehrtens clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
539d0b991e3SHauke Mehrtens } else if (of_machine_is_compatible("lantiq,grx390")) {
540d0b991e3SHauke Mehrtens clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(),
541d0b991e3SHauke Mehrtens ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz());
54258c9e247SAleksander Jan Bajkowski clkdev_add_pmu("1e108000.switch", "gphy3", 0, 0, PMU_GPHY3);
543dea54fbaSHauke Mehrtens clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
544dea54fbaSHauke Mehrtens clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
545d0b991e3SHauke Mehrtens /* rc 2 */
546ed90302bSMartin Blumenstingl clkdev_add_pmu("1f106a00.pcie", "phy", 1, 2, PMU_ANALOG_PCIE2_P);
547d0b991e3SHauke Mehrtens clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
548ed90302bSMartin Blumenstingl clkdev_add_pmu("1f106a00.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
549d0b991e3SHauke Mehrtens clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
550fe1a5642SHauke Mehrtens clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
551d0b991e3SHauke Mehrtens clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
552e71f6d35SHauke Mehrtens clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
553d0b991e3SHauke Mehrtens } else if (of_machine_is_compatible("lantiq,ar10")) {
554d0b991e3SHauke Mehrtens clkdev_add_static(ltq_ar10_cpu_hz(), ltq_ar10_fpi_hz(),
555d0b991e3SHauke Mehrtens ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
556dea54fbaSHauke Mehrtens clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
557dea54fbaSHauke Mehrtens clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
558fe1a5642SHauke Mehrtens clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH |
559d0b991e3SHauke Mehrtens PMU_PPE_DP | PMU_PPE_TC);
560d0b991e3SHauke Mehrtens clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
561e71f6d35SHauke Mehrtens clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
562a3a68534SHauke Mehrtens clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
563a3a68534SHauke Mehrtens clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
564287e3f3fSJohn Crispin } else if (of_machine_is_compatible("lantiq,vr9")) {
565287e3f3fSJohn Crispin clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
566740c606eSJohn Crispin ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
567dea54fbaSHauke Mehrtens clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
568dea54fbaSHauke Mehrtens clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
569dea54fbaSHauke Mehrtens clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
570dea54fbaSHauke Mehrtens clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
571ed90302bSMartin Blumenstingl clkdev_add_pmu("1f106800.phy", "phy", 1, 1, PMU1_PCIE_PHY);
57295135bfaSHauke Mehrtens clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
57395135bfaSHauke Mehrtens clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
574ed90302bSMartin Blumenstingl clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI);
57595135bfaSHauke Mehrtens clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
5765072d814SHauke Mehrtens clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
577e182c98aSHauke Mehrtens
578e182c98aSHauke Mehrtens clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
579fe1a5642SHauke Mehrtens clkdev_add_pmu("1e10b308.eth", NULL, 0, 0,
580f2bbe41cSJohn Crispin PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
581f2bbe41cSJohn Crispin PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
582f2bbe41cSJohn Crispin PMU_PPE_QSB | PMU_PPE_TOP);
58303e62fd6SMartin Blumenstingl clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY);
58403e62fd6SMartin Blumenstingl clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY);
585e182c98aSHauke Mehrtens clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
586e71f6d35SHauke Mehrtens clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
587a3a68534SHauke Mehrtens clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
588287e3f3fSJohn Crispin } else if (of_machine_is_compatible("lantiq,ar9")) {
589287e3f3fSJohn Crispin clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
590740c606eSJohn Crispin ltq_ar9_fpi_hz(), CLOCK_250M);
591dea54fbaSHauke Mehrtens clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
5923223a5a7SMathias Kresin clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
593dea54fbaSHauke Mehrtens clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
5943223a5a7SMathias Kresin clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
59595135bfaSHauke Mehrtens clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
596e182c98aSHauke Mehrtens clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
597e71f6d35SHauke Mehrtens clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
598a3a68534SHauke Mehrtens clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
5995072d814SHauke Mehrtens clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
600287e3f3fSJohn Crispin } else {
601287e3f3fSJohn Crispin clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
602740c606eSJohn Crispin ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
6033223a5a7SMathias Kresin clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
604dea54fbaSHauke Mehrtens clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
605e182c98aSHauke Mehrtens clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
606e71f6d35SHauke Mehrtens clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
607a3a68534SHauke Mehrtens clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
6085072d814SHauke Mehrtens clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
609287e3f3fSJohn Crispin }
610*9c7a86c9SHauke Mehrtens usb_set_clock();
611287e3f3fSJohn Crispin }
612