Home
last modified time | relevance | path

Searched refs:cfgr (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/rtc/
H A Drtc-stm32.c146 u16 cfgr; member
256 unsigned int cfgr = readl_relaxed(rtc->base + regs.cfgr); in stm32_rtc_pinmux_action_alarm() local
270 cfgr &= ~STM32_RTC_CFGR_OUT2_RMP; in stm32_rtc_pinmux_action_alarm()
274 cfgr &= ~STM32_RTC_CFGR_OUT2_RMP; in stm32_rtc_pinmux_action_alarm()
278 cfgr |= STM32_RTC_CFGR_OUT2_RMP; in stm32_rtc_pinmux_action_alarm()
286 writel_relaxed(cfgr, rtc->base + regs.cfgr); in stm32_rtc_pinmux_action_alarm()
297 unsigned int cfgr = readl_relaxed(rtc->base + regs.cfgr); in stm32_rtc_pinmux_lsco_available() local
310 (cfgr & STM32_RTC_CFGR_OUT2_RMP) && in stm32_rtc_pinmux_lsco_available()
343 rtc->base + regs.cfgr, lscoen, 0, NULL); in stm32_rtc_pinmux_action_lsco()
822 .cfgr = UNDEF_REG,
[all …]
/linux/drivers/pwm/
H A Dpwm-stm32-lp.c96 u32 cfgr, presc; in stm32_pwm_lp_compare_channel_apply() local
108 ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); in stm32_pwm_lp_compare_channel_apply()
111 presc = FIELD_GET(STM32_LPTIM_PRESC, cfgr); in stm32_pwm_lp_compare_channel_apply()
128 u32 arr, val, mask, cfgr, presc = 0; in stm32_pwm_lp_apply() local
189 ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); in stm32_pwm_lp_apply()
202 if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || (arr != prd - 1)) in stm32_pwm_lp_apply()
213 if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || in stm32_pwm_lp_apply()
214 ((FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity) && !priv->num_cc_chans)) { in stm32_pwm_lp_apply()
/linux/drivers/irqchip/
H A Dirq-gic-v5-irs.c68 u32 n, cfgr; in gicv5_irs_init_ist_linear() local
102 cfgr = FIELD_PREP(GICV5_IRS_IST_CFGR_STRUCTURE, in gicv5_irs_init_ist_linear()
108 irs_writel_relaxed(irs_data, cfgr, GICV5_IRS_IST_CFGR); in gicv5_irs_init_ist_linear()
132 u32 cfgr, n; in gicv5_irs_init_ist_two_level() local
152 cfgr = FIELD_PREP(GICV5_IRS_IST_CFGR_STRUCTURE, in gicv5_irs_init_ist_two_level()
157 irs_writel_relaxed(irs_data, cfgr, GICV5_IRS_IST_CFGR); in gicv5_irs_init_ist_two_level()
448 u32 selr, cfgr; in gicv5_spi_irq_set_type() local
478 cfgr = FIELD_PREP(GICV5_IRS_SPI_CFGR_TM, level); in gicv5_spi_irq_set_type()
479 irs_writel_relaxed(irs_data, cfgr, GICV5_IRS_SPI_CFGR); in gicv5_spi_irq_set_type()
H A Dirq-gic-v5-its.c81 FIELD_GET(GICV5_ITS_DT_CFGR_##f, (its)->devtab_cfgr.cfgr)
576 u32 cfgr; in gicv5_its_alloc_devtab_linear() local
600 cfgr = FIELD_PREP(GICV5_ITS_DT_CFGR_STRUCTURE, in gicv5_its_alloc_devtab_linear()
604 its_writel_relaxed(its, cfgr, GICV5_ITS_DT_CFGR); in gicv5_its_alloc_devtab_linear()
609 its->devtab_cfgr.cfgr = cfgr; in gicv5_its_alloc_devtab_linear()
627 u32 cfgr; in gicv5_its_alloc_devtab_two_level() local
665 cfgr = FIELD_PREP(GICV5_ITS_DT_CFGR_STRUCTURE, in gicv5_its_alloc_devtab_two_level()
669 its_writel_relaxed(its, cfgr, GICV5_ITS_DT_CFGR); in gicv5_its_alloc_devtab_two_level()
674 its->devtab_cfgr.cfgr = cfgr; in gicv5_its_alloc_devtab_two_level()
/linux/drivers/mmc/host/
H A Dmmci_stm32_sdmmc.c490 u32 cfgr; in sdmmc_dlyb_mp15_set_cfg() local
494 cfgr = FIELD_PREP(DLYB_CFGR_UNIT_MASK, unit) | in sdmmc_dlyb_mp15_set_cfg()
496 writel_relaxed(cfgr, dlyb->base + DLYB_CFGR); in sdmmc_dlyb_mp15_set_cfg()
507 u32 cfgr; in sdmmc_dlyb_mp15_prepare() local
513 ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr, in sdmmc_dlyb_mp15_prepare()
514 (cfgr & DLYB_CFGR_LNGF), in sdmmc_dlyb_mp15_prepare()
519 i, cfgr); in sdmmc_dlyb_mp15_prepare()
523 lng = FIELD_GET(DLYB_CFGR_LNG_MASK, cfgr); in sdmmc_dlyb_mp15_prepare()
/linux/drivers/memory/
H A Dstm32-fmc2-ebi.c206 u32 cfgr; member
306 u32 cfgr; in stm32_fmc2_ebi_mp25_check_clk_period() local
309 ret = regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); in stm32_fmc2_ebi_mp25_check_clk_period()
313 if (cfgr & FMC2_CFGR_CCLKEN && !ebi->access_granted) in stm32_fmc2_ebi_mp25_check_clk_period()
449 u32 cfgr, btr, clk_period; in stm32_fmc2_ebi_mp25_ns_to_clk_period() local
452 ret = regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); in stm32_fmc2_ebi_mp25_ns_to_clk_period()
456 if (cfgr & FMC2_CFGR_CCLKEN) { in stm32_fmc2_ebi_mp25_ns_to_clk_period()
457 clk_period = FIELD_GET(FMC2_CFGR_CLKDIV, cfgr) + 1; in stm32_fmc2_ebi_mp25_ns_to_clk_period()
837 u32 val, cfgr; in stm32_fmc2_ebi_mp25_set_clk_period() local
840 ret = regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); in stm32_fmc2_ebi_mp25_set_clk_period()
[all …]
/linux/drivers/perf/
H A Darm_smmuv3_pmu.c851 u32 cfgr, reg_size; in smmu_pmu_probe() local
884 cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR); in smmu_pmu_probe()
887 if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) { in smmu_pmu_probe()
904 smmu_pmu->num_counters = FIELD_GET(SMMU_PMCG_CFGR_NCTR, cfgr) + 1; in smmu_pmu_probe()
906 smmu_pmu->global_filter = !!(cfgr & SMMU_PMCG_CFGR_SID_FILTER_TYPE); in smmu_pmu_probe()
908 reg_size = FIELD_GET(SMMU_PMCG_CFGR_SIZE, cfgr); in smmu_pmu_probe()
/linux/sound/soc/stm/
H A Dstm32_i2s.c862 u32 cfgr, cfgr_mask, cfg1; in stm32_i2s_configure() local
868 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16); in stm32_i2s_configure()
872 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) | in stm32_i2s_configure()
882 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE); in stm32_i2s_configure()
885 cfgr |= I2S_CGFR_FIXCH; in stm32_i2s_configure()
888 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER); in stm32_i2s_configure()
893 cfgr_mask, cfgr); in stm32_i2s_configure()
/linux/drivers/net/ethernet/freescale/enetc/
H A Denetc_pf.c284 u32 cfgr; in enetc_pf_set_vf_spoofchk() local
289 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1)); in enetc_pf_set_vf_spoofchk()
290 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0); in enetc_pf_set_vf_spoofchk()
291 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr); in enetc_pf_set_vf_spoofchk()
/linux/include/linux/irqchip/
H A Darm-gic-v5.h367 u32 cfgr; member
/linux/arch/arc/boot/dts/
H A Dhsdk.dts332 clock-names = "core-clk", "cfgr-clk";
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi331 clock-names = "core-clk", "cfgr-clk";
349 clock-names = "core-clk", "cfgr-clk";
/linux/arch/riscv/boot/dts/sophgo/
H A Dcv180x.dtsi424 clock-names = "core-clk", "cfgr-clk";
H A Dsg2044.dtsi249 clock-names = "core-clk", "cfgr-clk";
/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi158 clock-names = "core-clk", "cfgr-clk";
/linux/drivers/net/ethernet/freescale/
H A Dfec_main.c1230 u32 cfgr; in fec_restart() local
1241 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) in fec_restart()
1244 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; in fec_restart()
1245 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); in fec_restart()
/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi593 clock-names = "core-clk", "cfgr-clk";