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Searched refs:cfg2 (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/usb/typec/mux/
H A Dps883x.c147 int cfg1, int cfg2, bool reset) in ps883x_configure() argument
181 ret = regmap_write(retimer->regmap, REG_USB_PORT_CONN_STATUS_2, cfg2); in ps883x_configure()
196 int cfg2 = 0x00; in ps883x_set() local
224 cfg2 |= CONN_STATUS_2_TBT_CONNECTED; in ps883x_set()
230 cfg2 |= CONN_STATUS_2_TBT_UNIDIR_LSRX_ACT_LT; in ps883x_set()
254 cfg2 |= CONN_STATUS_2_USB4_CONNECTED; in ps883x_set()
266 return ps883x_configure(retimer, cfg0, cfg1, cfg2, reset); in ps883x_set()
/linux/drivers/clk/ultrarisc/
H A Dclk-ultrarisc.c45 u32 cfg1, cfg2; in ultrarisc_pll_recalc_rate() local
48 cfg2 = readl_relaxed(pll->base + layout->cfg2_offset); in ultrarisc_pll_recalc_rate()
51 m = field_get(layout->m_mask, cfg2); in ultrarisc_pll_recalc_rate()
52 n = field_get(layout->n_mask, cfg2); in ultrarisc_pll_recalc_rate()
56 oddiv1_div = 1U << field_get(layout->oddiv1_mask, cfg2); in ultrarisc_pll_recalc_rate()
57 oddiv2_div = 1U << field_get(layout->oddiv2_mask, cfg2); in ultrarisc_pll_recalc_rate()
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_panel.c478 u32 cfg, cfg2, misc; in msm_dp_panel_enable_vsc_sdp() local
481 cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2); in msm_dp_panel_enable_vsc_sdp()
487 cfg2 |= GENERIC0_SDPSIZE_VALID; in msm_dp_panel_enable_vsc_sdp()
488 msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2); in msm_dp_panel_enable_vsc_sdp()
507 u32 cfg, cfg2, misc; in msm_dp_panel_disable_vsc_sdp() local
510 cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2); in msm_dp_panel_disable_vsc_sdp()
516 cfg2 &= ~GENERIC0_SDPSIZE_VALID; in msm_dp_panel_disable_vsc_sdp()
517 msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2); in msm_dp_panel_disable_vsc_sdp()
/linux/drivers/perf/
H A Dfsl_imx8_ddr_perf.c602 int cfg2 = event->attr.config2; in ddr_perf_event_add() local
634 cfg2 ^= READ_CHANNEL_REVERT; in ddr_perf_event_add()
635 cfg2 |= FIELD_PREP(READ_PORT_MASK, cfg2); in ddr_perf_event_add()
638 cfg2 ^= WRITE_CHANNEL_REVERT; in ddr_perf_event_add()
639 cfg2 |= FIELD_PREP(WRITE_PORT_MASK, cfg2); in ddr_perf_event_add()
642 writel(cfg2, pmu->base + COUNTER_MUX_CNTL + ((counter - 1) << 4)); in ddr_perf_event_add()
H A Dfsl_imx9_ddr_perf.c635 int cfg2 = event->attr.config2; in ddr_perf_event_add() local
654 imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); in ddr_perf_event_add()
658 imx95_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); in ddr_perf_event_add()
/linux/drivers/iio/adc/
H A Dimx7d_adc.c236 u32 cfg2; in imx7d_adc_channel_set() local
258 cfg2 = readl(info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel + in imx7d_adc_channel_set()
261 cfg2 |= imx7d_adc_average_num[info->adc_feature.avg_num]; in imx7d_adc_channel_set()
267 writel(cfg2, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel + in imx7d_adc_channel_set()
H A Dad7173.c652 * @cfg2: Second channel configuration
660 const struct ad7173_channel_config *cfg2) in ad7173_is_setup_equal() argument
676 return cfg1->bipolar == cfg2->bipolar && in ad7173_is_setup_equal()
677 cfg1->input_buf == cfg2->input_buf && in ad7173_is_setup_equal()
678 cfg1->sinc3_odr_div == cfg2->sinc3_odr_div && in ad7173_is_setup_equal()
679 cfg1->sinc5_odr_index == cfg2->sinc5_odr_index && in ad7173_is_setup_equal()
680 cfg1->ref_sel == cfg2->ref_sel && in ad7173_is_setup_equal()
681 cfg1->filter_type == cfg2->filter_type; in ad7173_is_setup_equal()
1435 const struct ad7173_channel_config *cfg1, *cfg2; in ad7173_update_scan_mode() local
1440 cfg2 in ad7173_update_scan_mode()
[all...]
/linux/sound/pci/
H A Dals4000.c685 u32 cfg2 = 0; in snd_als4000_set_addr() local
688 cfg2 |= (mpu_io | 1) << 16; in snd_als4000_set_addr()
690 cfg2 |= (sb_io | 1); in snd_als4000_set_addr()
696 snd_als4k_gcr_write_addr(iobase, ALS4K_GCRA9_LEGACY_CFG2, cfg2); in snd_als4000_set_addr()
/linux/drivers/net/ethernet/agere/
H A Det131x.c870 u32 cfg2; in et1310_config_mac_regs2() local
876 cfg2 = readl(&mac->cfg2); in et1310_config_mac_regs2()
880 cfg2 &= ~ET_MAC_CFG2_IFMODE_MASK; in et1310_config_mac_regs2()
882 cfg2 |= ET_MAC_CFG2_IFMODE_1000; in et1310_config_mac_regs2()
885 cfg2 |= ET_MAC_CFG2_IFMODE_100; in et1310_config_mac_regs2()
901 cfg2 |= 0x7 << ET_MAC_CFG2_PREAMBLE_SHIFT; in et1310_config_mac_regs2()
902 cfg2 |= ET_MAC_CFG2_IFMODE_LEN_CHECK; in et1310_config_mac_regs2()
903 cfg2 |= ET_MAC_CFG2_IFMODE_PAD_CRC; in et1310_config_mac_regs2()
904 cfg2 |= ET_MAC_CFG2_IFMODE_CRC_ENABLE; in et1310_config_mac_regs2()
905 cfg2 &= ~ET_MAC_CFG2_IFMODE_HUGE_FRAME; in et1310_config_mac_regs2()
[all …]
H A Det131x.h1048 u32 cfg2; /* 0x5004 */ member
/linux/drivers/mmc/host/
H A Drtsx_pci_sdmmc.c435 u8 cfg2 = 0; in sd_read_long_data() local
448 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; in sd_read_long_data()
467 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type); in sd_read_long_data()
493 u8 cfg2; in sd_write_long_data() local
504 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | in sd_write_long_data()
508 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; in sd_write_long_data()
526 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); in sd_write_long_data()
/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_fimc.c419 u32 cfg1, cfg2; in fimc_src_set_transf() local
427 cfg2 = fimc_read(ctx, EXYNOS_CITRGFMT); in fimc_src_set_transf()
428 cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE; in fimc_src_set_transf()
438 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE; in fimc_src_set_transf()
455 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE; in fimc_src_set_transf()
464 fimc_write(ctx, cfg2, EXYNOS_CITRGFMT); in fimc_src_set_transf()
/linux/drivers/net/ethernet/atheros/
H A Dag71xx.c1022 u32 cfg1, cfg2; in ag71xx_mac_link_up() local
1026 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2); in ag71xx_mac_link_up()
1027 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX); in ag71xx_mac_link_up()
1028 cfg2 |= duplex ? MAC_CFG2_FDX : 0; in ag71xx_mac_link_up()
1038 cfg2 |= MAC_CFG2_IF_1000; in ag71xx_mac_link_up()
1042 cfg2 |= MAC_CFG2_IF_10_100; in ag71xx_mac_link_up()
1046 cfg2 |= MAC_CFG2_IF_10_100; in ag71xx_mac_link_up()
1052 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); in ag71xx_mac_link_up()
/linux/net/ipv4/
H A Dfib_semantics.c1024 struct fib_config cfg2; in fib_nh_match()
1026 err = fib_gw_from_via(&cfg2, nlav, extack); in fib_nh_match()
1032 if (cfg2.fc_gw_family != AF_INET || in fib_nh_match()
1033 cfg2.fc_gw4 != nh->fib_nh_gw4) in fib_nh_match()
1037 if (cfg2.fc_gw_family != AF_INET6 || in fib_nh_match()
1038 ipv6_addr_cmp(&cfg2.fc_gw6, in fib_nh_match()
1021 struct fib_config cfg2; fib_nh_match() local
/linux/arch/mips/kernel/
H A Dcpu-probe.c1661 u32 cfg2 = read_cpucfg(LOONGSON_CFG2); in decode_cpucfg() local
1667 if (cfg2 & LOONGSON_CFG2_LEXT1) in decode_cpucfg()
1670 if (cfg2 & LOONGSON_CFG2_LEXT2) in decode_cpucfg()
1673 if (cfg2 & LOONGSON_CFG2_LSPW) { in decode_cpucfg()
/linux/drivers/hwmon/
H A Dadt7462.c207 u8 cfg2; member
768 data->cfg2 = i2c_smbus_read_byte_data(client, ADT7462_REG_CFG2); in adt7462_update_device()
1056 return sprintf(buf, "%d\n", (data->cfg2 & ADT7462_FSPD_MASK ? 1 : 0)); in force_pwm_max_show()
1077 data->cfg2 = reg; in force_pwm_max_store()
/linux/drivers/infiniband/hw/erdma/
H A Derdma_verbs.c59 req.cfg2 = FIELD_PREP(ERDMA_CMD_CREATE_QP_TYPE_MASK, in create_qp_cmd()
62 req.cfg2 = FIELD_PREP(ERDMA_CMD_CREATE_QP_TYPE_MASK, in create_qp_cmd()
166 req.cfg2 = FIELD_PREP(ERDMA_CMD_REGMR_PAGESIZE_MASK, in regmr_cmd()
181 req.cfg2 |= FIELD_PREP(ERDMA_CMD_REGMR_MTT_PAGESIZE_MASK, in regmr_cmd()
246 req.cfg2 = FIELD_PREP(ERDMA_CMD_CREATE_CQ_DB_CFG_MASK, in create_cq_cmd()
/linux/drivers/spi/
H A Dspi-stm32.c2199 u32 cr1 = 0, cfg2 = 0; in stm32h7_spi_config() local
2209 cfg2 &= ~STM32H7_SPI_CFG2_SSM; in stm32h7_spi_config()
2224 cfg2 |= STM32H7_SPI_CFG2_MASTER | STM32H7_SPI_CFG2_SSM | STM32H7_SPI_CFG2_AFCNTR; in stm32h7_spi_config()
2228 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, cfg2); in stm32h7_spi_config()
/linux/drivers/net/wireless/ath/ath12k/
H A Ddp_htt.h1509 u32 cfg2; member
H A Ddp_htt.c1162 cmd->cfg_param2 = cpu_to_le32(cfg_params->cfg2); in ath12k_dp_tx_htt_h2t_ext_stats_req()
/linux/drivers/pinctrl/nuvoton/
H A Dpinctrl-wpcm450.c77 u8 cfg0, cfg1, cfg2; member
/linux/tools/perf/Documentation/
H A Dperf-record.txt89 perf record -e some_event/@cfg1,@cfg2=config/ ...
91 will see 'cfg1' and 'cfg2=config' pushed to the PMU driver associated
/linux/drivers/net/ethernet/broadcom/
H A Dtg3.c15253 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0; in tg3_get_eeprom_hw_cfg() local
15266 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); in tg3_get_eeprom_hw_cfg()
15300 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | in tg3_get_eeprom_hw_cfg()
15394 if (cfg2 & (1 << 17)) in tg3_get_eeprom_hw_cfg()
15399 if (cfg2 & (1 << 18)) in tg3_get_eeprom_hw_cfg()
15405 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) in tg3_get_eeprom_hw_cfg()