1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 #ifndef ATH12K_RX_DESC_H 7 #define ATH12K_RX_DESC_H 8 9 enum rx_desc_decrypt_status_code { 10 RX_DESC_DECRYPT_STATUS_CODE_OK, 11 RX_DESC_DECRYPT_STATUS_CODE_UNPROTECTED_FRAME, 12 RX_DESC_DECRYPT_STATUS_CODE_DATA_ERR, 13 RX_DESC_DECRYPT_STATUS_CODE_KEY_INVALID, 14 RX_DESC_DECRYPT_STATUS_CODE_PEER_ENTRY_INVALID, 15 RX_DESC_DECRYPT_STATUS_CODE_OTHER, 16 }; 17 18 #define RX_MPDU_START_INFO0_REO_DEST_IND GENMASK(4, 0) 19 #define RX_MPDU_START_INFO0_LMAC_PEER_ID_MSB GENMASK(6, 5) 20 #define RX_MPDU_START_INFO0_FLOW_ID_TOEPLITZ BIT(7) 21 #define RX_MPDU_START_INFO0_PKT_SEL_FP_UCAST_DATA BIT(8) 22 #define RX_MPDU_START_INFO0_PKT_SEL_FP_MCAST_DATA BIT(9) 23 #define RX_MPDU_START_INFO0_PKT_SEL_FP_CTRL_BAR BIT(10) 24 #define RX_MPDU_START_INFO0_RXDMA0_SRC_RING_SEL GENMASK(13, 11) 25 #define RX_MPDU_START_INFO0_RXDMA0_DST_RING_SEL GENMASK(16, 14) 26 #define RX_MPDU_START_INFO0_MCAST_ECHO_DROP_EN BIT(17) 27 #define RX_MPDU_START_INFO0_WDS_LEARN_DETECT_EN BIT(18) 28 #define RX_MPDU_START_INFO0_INTRA_BSS_CHECK_EN BIT(19) 29 #define RX_MPDU_START_INFO0_USE_PPE BIT(20) 30 #define RX_MPDU_START_INFO0_PPE_ROUTING_EN BIT(21) 31 32 #define RX_MPDU_START_INFO1_REO_QUEUE_DESC_HI GENMASK(7, 0) 33 #define RX_MPDU_START_INFO1_RECV_QUEUE_NUM GENMASK(23, 8) 34 #define RX_MPDU_START_INFO1_PRE_DELIM_ERR_WARN BIT(24) 35 #define RX_MPDU_START_INFO1_FIRST_DELIM_ERR BIT(25) 36 37 #define RX_MPDU_START_INFO2_EPD_EN BIT(0) 38 #define RX_MPDU_START_INFO2_ALL_FRAME_ENCPD BIT(1) 39 #define RX_MPDU_START_INFO2_ENC_TYPE GENMASK(5, 2) 40 #define RX_MPDU_START_INFO2_VAR_WEP_KEY_WIDTH GENMASK(7, 6) 41 #define RX_MPDU_START_INFO2_MESH_STA GENMASK(9, 8) 42 #define RX_MPDU_START_INFO2_BSSID_HIT BIT(10) 43 #define RX_MPDU_START_INFO2_BSSID_NUM GENMASK(14, 11) 44 #define RX_MPDU_START_INFO2_TID GENMASK(18, 15) 45 46 #define RX_MPDU_START_INFO3_RXPCU_MPDU_FLTR GENMASK(1, 0) 47 #define RX_MPDU_START_INFO3_SW_FRAME_GRP_ID GENMASK(8, 2) 48 #define RX_MPDU_START_INFO3_NDP_FRAME BIT(9) 49 #define RX_MPDU_START_INFO3_PHY_ERR BIT(10) 50 #define RX_MPDU_START_INFO3_PHY_ERR_MPDU_HDR BIT(11) 51 #define RX_MPDU_START_INFO3_PROTO_VER_ERR BIT(12) 52 #define RX_MPDU_START_INFO3_AST_LOOKUP_VALID BIT(13) 53 #define RX_MPDU_START_INFO3_RANGING BIT(14) 54 55 #define RX_MPDU_START_INFO4_MPDU_FCTRL_VALID BIT(0) 56 #define RX_MPDU_START_INFO4_MPDU_DUR_VALID BIT(1) 57 #define RX_MPDU_START_INFO4_MAC_ADDR1_VALID BIT(2) 58 #define RX_MPDU_START_INFO4_MAC_ADDR2_VALID BIT(3) 59 #define RX_MPDU_START_INFO4_MAC_ADDR3_VALID BIT(4) 60 #define RX_MPDU_START_INFO4_MAC_ADDR4_VALID BIT(5) 61 #define RX_MPDU_START_INFO4_MPDU_SEQ_CTRL_VALID BIT(6) 62 #define RX_MPDU_START_INFO4_MPDU_QOS_CTRL_VALID BIT(7) 63 #define RX_MPDU_START_INFO4_MPDU_HT_CTRL_VALID BIT(8) 64 #define RX_MPDU_START_INFO4_ENCRYPT_INFO_VALID BIT(9) 65 #define RX_MPDU_START_INFO4_MPDU_FRAG_NUMBER GENMASK(13, 10) 66 #define RX_MPDU_START_INFO4_MORE_FRAG_FLAG BIT(14) 67 #define RX_MPDU_START_INFO4_FROM_DS BIT(16) 68 #define RX_MPDU_START_INFO4_TO_DS BIT(17) 69 #define RX_MPDU_START_INFO4_ENCRYPTED BIT(18) 70 #define RX_MPDU_START_INFO4_MPDU_RETRY BIT(19) 71 #define RX_MPDU_START_INFO4_MPDU_SEQ_NUM GENMASK(31, 20) 72 73 #define RX_MPDU_START_INFO5_KEY_ID GENMASK(7, 0) 74 #define RX_MPDU_START_INFO5_NEW_PEER_ENTRY BIT(8) 75 #define RX_MPDU_START_INFO5_DECRYPT_NEEDED BIT(9) 76 #define RX_MPDU_START_INFO5_DECAP_TYPE GENMASK(11, 10) 77 #define RX_MPDU_START_INFO5_VLAN_TAG_C_PADDING BIT(12) 78 #define RX_MPDU_START_INFO5_VLAN_TAG_S_PADDING BIT(13) 79 #define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_C BIT(14) 80 #define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_S BIT(15) 81 #define RX_MPDU_START_INFO5_PRE_DELIM_COUNT GENMASK(27, 16) 82 #define RX_MPDU_START_INFO5_AMPDU_FLAG BIT(28) 83 #define RX_MPDU_START_INFO5_BAR_FRAME BIT(29) 84 #define RX_MPDU_START_INFO5_RAW_MPDU BIT(30) 85 86 #define RX_MPDU_START_INFO6_MPDU_LEN GENMASK(13, 0) 87 #define RX_MPDU_START_INFO6_FIRST_MPDU BIT(14) 88 #define RX_MPDU_START_INFO6_MCAST_BCAST BIT(15) 89 #define RX_MPDU_START_INFO6_AST_IDX_NOT_FOUND BIT(16) 90 #define RX_MPDU_START_INFO6_AST_IDX_TIMEOUT BIT(17) 91 #define RX_MPDU_START_INFO6_POWER_MGMT BIT(18) 92 #define RX_MPDU_START_INFO6_NON_QOS BIT(19) 93 #define RX_MPDU_START_INFO6_NULL_DATA BIT(20) 94 #define RX_MPDU_START_INFO6_MGMT_TYPE BIT(21) 95 #define RX_MPDU_START_INFO6_CTRL_TYPE BIT(22) 96 #define RX_MPDU_START_INFO6_MORE_DATA BIT(23) 97 #define RX_MPDU_START_INFO6_EOSP BIT(24) 98 #define RX_MPDU_START_INFO6_FRAGMENT BIT(25) 99 #define RX_MPDU_START_INFO6_ORDER BIT(26) 100 #define RX_MPDU_START_INFO6_UAPSD_TRIGGER BIT(27) 101 #define RX_MPDU_START_INFO6_ENCRYPT_REQUIRED BIT(28) 102 #define RX_MPDU_START_INFO6_DIRECTED BIT(29) 103 #define RX_MPDU_START_INFO6_AMSDU_PRESENT BIT(30) 104 105 #define RX_MPDU_START_INFO7_VDEV_ID GENMASK(7, 0) 106 #define RX_MPDU_START_INFO7_SERVICE_CODE GENMASK(16, 8) 107 #define RX_MPDU_START_INFO7_PRIORITY_VALID BIT(17) 108 #define RX_MPDU_START_INFO7_SRC_INFO GENMASK(29, 18) 109 110 #define RX_MPDU_START_INFO8_AUTH_TO_SEND_WDS BIT(0) 111 112 struct rx_mpdu_start_qcn9274 { 113 __le32 info0; 114 __le32 reo_queue_desc_lo; 115 __le32 info1; 116 __le32 pn[4]; 117 __le32 info2; 118 __le32 peer_meta_data; 119 __le16 info3; 120 __le16 phy_ppdu_id; 121 __le16 ast_index; 122 __le16 sw_peer_id; 123 __le32 info4; 124 __le32 info5; 125 __le32 info6; 126 __le16 frame_ctrl; 127 __le16 duration; 128 u8 addr1[ETH_ALEN]; 129 u8 addr2[ETH_ALEN]; 130 u8 addr3[ETH_ALEN]; 131 __le16 seq_ctrl; 132 u8 addr4[ETH_ALEN]; 133 __le16 qos_ctrl; 134 __le32 ht_ctrl; 135 __le32 info7; 136 u8 multi_link_addr1[ETH_ALEN]; 137 u8 multi_link_addr2[ETH_ALEN]; 138 __le32 info8; 139 __le32 res0; 140 __le32 res1; 141 } __packed; 142 143 struct rx_mpdu_start_qcc2072 { 144 __le32 info0; 145 __le32 info2; 146 __le32 reo_queue_desc_lo; 147 __le32 info1; 148 __le32 pn[4]; 149 __le32 info4; 150 __le32 peer_meta_data; 151 __le16 ast_index; 152 __le16 sw_peer_id; 153 __le16 info3; 154 __le16 phy_ppdu_id; 155 __le32 info5; 156 __le32 info6; 157 __le16 frame_ctrl; 158 __le16 duration; 159 u8 addr1[ETH_ALEN]; 160 u8 addr2[ETH_ALEN]; 161 u8 addr3[ETH_ALEN]; 162 __le16 seq_ctrl; 163 u8 addr4[ETH_ALEN]; 164 __le16 qos_ctrl; 165 __le32 ht_ctrl; 166 __le32 info7; 167 __le32 res0; 168 __le32 res1; 169 __le32 res2; 170 __le32 info8; 171 __le32 res3; 172 __le32 res4; 173 } __packed; 174 175 #define QCN9274_MPDU_START_SELECT_MPDU_START_TAG BIT(0) 176 #define QCN9274_MPDU_START_SELECT_INFO0_REO_QUEUE_DESC_LO BIT(1) 177 #define QCN9274_MPDU_START_SELECT_INFO1_PN_31_0 BIT(2) 178 #define QCN9274_MPDU_START_SELECT_PN_95_32 BIT(3) 179 #define QCN9274_MPDU_START_SELECT_PN_127_96_INFO2 BIT(4) 180 #define QCN9274_MPDU_START_SELECT_PEER_MDATA_INFO3_PHY_PPDU_ID BIT(5) 181 #define QCN9274_MPDU_START_SELECT_AST_IDX_SW_PEER_ID_INFO4 BIT(6) 182 #define QCN9274_MPDU_START_SELECT_INFO5_INFO6 BIT(7) 183 #define QCN9274_MPDU_START_SELECT_FRAME_CTRL_DURATION_ADDR1_31_0 BIT(8) 184 #define QCN9274_MPDU_START_SELECT_ADDR2_47_0_ADDR1_47_32 BIT(9) 185 #define QCN9274_MPDU_START_SELECT_ADDR3_47_0_SEQ_CTRL BIT(10) 186 #define QCN9274_MPDU_START_SELECT_ADDR4_47_0_QOS_CTRL BIT(11) 187 #define QCN9274_MPDU_START_SELECT_HT_CTRL_INFO7 BIT(12) 188 #define QCN9274_MPDU_START_SELECT_ML_ADDR1_47_0_ML_ADDR2_15_0 BIT(13) 189 #define QCN9274_MPDU_START_SELECT_ML_ADDR2_47_16_INFO8 BIT(14) 190 #define QCN9274_MPDU_START_SELECT_RES_0_RES_1 BIT(15) 191 192 #define QCN9274_MPDU_START_WMASK (QCN9274_MPDU_START_SELECT_INFO1_PN_31_0 | \ 193 QCN9274_MPDU_START_SELECT_PN_95_32 | \ 194 QCN9274_MPDU_START_SELECT_PN_127_96_INFO2 | \ 195 QCN9274_MPDU_START_SELECT_PEER_MDATA_INFO3_PHY_PPDU_ID | \ 196 QCN9274_MPDU_START_SELECT_AST_IDX_SW_PEER_ID_INFO4 | \ 197 QCN9274_MPDU_START_SELECT_INFO5_INFO6 | \ 198 QCN9274_MPDU_START_SELECT_FRAME_CTRL_DURATION_ADDR1_31_0 | \ 199 QCN9274_MPDU_START_SELECT_ADDR2_47_0_ADDR1_47_32 | \ 200 QCN9274_MPDU_START_SELECT_ADDR3_47_0_SEQ_CTRL | \ 201 QCN9274_MPDU_START_SELECT_ADDR4_47_0_QOS_CTRL) 202 203 /* The below rx_mpdu_start_qcn9274_compact structure is tied with the mask 204 * value QCN9274_MPDU_START_WMASK. If the mask value changes the structure 205 * will also change. 206 */ 207 208 struct rx_mpdu_start_qcn9274_compact { 209 __le32 info1; 210 __le32 pn[4]; 211 __le32 info2; 212 __le32 peer_meta_data; 213 __le16 info3; 214 __le16 phy_ppdu_id; 215 __le16 ast_index; 216 __le16 sw_peer_id; 217 __le32 info4; 218 __le32 info5; 219 __le32 info6; 220 __le16 frame_ctrl; 221 __le16 duration; 222 u8 addr1[ETH_ALEN]; 223 u8 addr2[ETH_ALEN]; 224 u8 addr3[ETH_ALEN]; 225 __le16 seq_ctrl; 226 u8 addr4[ETH_ALEN]; 227 __le16 qos_ctrl; 228 } __packed; 229 230 /* rx_mpdu_start 231 * 232 * reo_destination_indication 233 * The id of the reo exit ring where the msdu frame shall push 234 * after (MPDU level) reordering has finished. Values are defined 235 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 236 * 237 * lmac_peer_id_msb 238 * 239 * If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb 240 * is 2'b00, Rx OLE uses a REO destination indicati'n of {1'b1, 241 * hash[3:0]} using the chosen Toeplitz hash from Common Parser 242 * if flow search fails. 243 * If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb 244 * 's not 2'b00, Rx OLE uses a REO destination indication of 245 * {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz 246 * hash from Common Parser if flow search fails. 247 * 248 * use_flow_id_toeplitz_clfy 249 * Indication to Rx OLE to enable REO destination routing based 250 * on the chosen Toeplitz hash from Common Parser, in case 251 * flow search fails 252 * 253 * pkt_selection_fp_ucast_data 254 * Filter pass Unicast data frame (matching rxpcu_filter_pass 255 * and sw_frame_group_Unicast_data) routing selection 256 * 257 * pkt_selection_fp_mcast_data 258 * Filter pass Multicast data frame (matching rxpcu_filter_pass 259 * and sw_frame_group_Multicast_data) routing selection 260 * 261 * pkt_selection_fp_ctrl_bar 262 * Filter pass BAR frame (matching rxpcu_filter_pass 263 * and sw_frame_group_ctrl_1000) routing selection 264 * 265 * rxdma0_src_ring_selection 266 * Field only valid when for the received frame type the corresponding 267 * pkt_selection_fp_... bit is set 268 * 269 * rxdma0_dst_ring_selection 270 * Field only valid when for the received frame type the corresponding 271 * pkt_selection_fp_... bit is set 272 * 273 * mcast_echo_drop_enable 274 * If set, for multicast packets, multicast echo check (i.e. 275 * SA search with mcast_echo_check = 1) shall be performed 276 * by RXOLE, and any multicast echo packets should be indicated 277 * to RXDMA for release to WBM 278 * 279 * wds_learning_detect_en 280 * If set, WDS learning detection based on SA search and notification 281 * to FW (using RXDMA0 status ring) is enabled and the "timestamp" 282 * field in address search failure cache-only entry should 283 * be used to avoid multiple WDS learning notifications. 284 * 285 * intrabss_check_en 286 * If set, intra-BSS routing detection is enabled 287 * 288 * use_ppe 289 * Indicates to RXDMA to ignore the REO_destination_indication 290 * and use a programmed value corresponding to the REO2PPE 291 * ring 292 * This override to REO2PPE for packets requiring multiple 293 * buffers shall be disabled based on an RXDMA configuration, 294 * as PPE may not support such packets. 295 * 296 * Supported only in full AP chips, not in client/soft 297 * chips 298 * 299 * ppe_routing_enable 300 * Global enable/disable bit for routing to PPE, used to disable 301 * PPE routing even if RXOLE CCE or flow search indicate 'Use_PPE' 302 * This is set by SW for peers which are being handled by a 303 * host SW/accelerator subsystem that also handles packet 304 * buffer management for WiFi-to-PPE routing. 305 * 306 * This is cleared by SW for peers which are being handled 307 * by a different subsystem, completely disabling WiFi-to-PPE 308 * routing for such peers. 309 * 310 * rx_reo_queue_desc_addr_lo 311 * Address (lower 32 bits) of the REO queue descriptor. 312 * 313 * rx_reo_queue_desc_addr_hi 314 * Address (upper 8 bits) of the REO queue descriptor. 315 * 316 * receive_queue_number 317 * Indicates the MPDU queue ID to which this MPDU link 318 * descriptor belongs. 319 * 320 * pre_delim_err_warning 321 * Indicates that a delimiter FCS error was found in between the 322 * previous MPDU and this MPDU. Note that this is just a warning, 323 * and does not mean that this MPDU is corrupted in any way. If 324 * it is, there will be other errors indicated such as FCS or 325 * decrypt errors. 326 * 327 * first_delim_err 328 * Indicates that the first delimiter had a FCS failure. 329 * 330 * pn 331 * The PN number. 332 * 333 * epd_en 334 * Field only valid when AST_based_lookup_valid == 1. 335 * In case of ndp or phy_err or AST_based_lookup_valid == 0, 336 * this field will be set to 0 337 * If set to one use EPD instead of LPD 338 * In case of ndp or phy_err, this field will never be set. 339 * 340 * all_frames_shall_be_encrypted 341 * In case of ndp or phy_err or AST_based_lookup_valid == 0, 342 * this field will be set to 0 343 * 344 * When set, all frames (data only ?) shall be encrypted. If 345 * not, RX CRYPTO shall set an error flag. 346 * 347 * 348 * encrypt_type 349 * In case of ndp or phy_err or AST_based_lookup_valid == 0, 350 * this field will be set to 0 351 * 352 * Indicates type of decrypt cipher used (as defined in the 353 * peer entry) 354 * 355 * wep_key_width_for_variable_key 356 * 357 * Field only valid when key_type is set to wep_varied_width. 358 * 359 * mesh_sta 360 * 361 * bssid_hit 362 * When set, the BSSID of the incoming frame matched one of 363 * the 8 BSSID register values 364 * bssid_number 365 * Field only valid when bssid_hit is set. 366 * This number indicates which one out of the 8 BSSID register 367 * values matched the incoming frame 368 * 369 * tid 370 * Field only valid when mpdu_qos_control_valid is set 371 * The TID field in the QoS control field 372 * 373 * peer_meta_data 374 * Meta data that SW has programmed in the Peer table entry 375 * of the transmitting STA. 376 * 377 * rxpcu_mpdu_filter_in_category 378 * Field indicates what the reason was that this mpdu frame 379 * was allowed to come into the receive path by rxpcu. Values 380 * are defined in enum %RX_DESC_RXPCU_FILTER_*. 381 * 382 * sw_frame_group_id 383 * SW processes frames based on certain classifications. Values 384 * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 385 * 386 * ndp_frame 387 * When set, the received frame was an NDP frame, and thus 388 * there will be no MPDU data. 389 * phy_err 390 * When set, a PHY error was received before MAC received any 391 * data, and thus there will be no MPDU data. 392 * 393 * phy_err_during_mpdu_header 394 * When set, a PHY error was received before MAC received the 395 * complete MPDU header which was needed for proper decoding 396 * 397 * protocol_version_err 398 * Set when RXPCU detected a version error in the Frame control 399 * field 400 * 401 * ast_based_lookup_valid 402 * When set, AST based lookup for this frame has found a valid 403 * result. 404 * 405 * ranging 406 * When set, a ranging NDPA or a ranging NDP was received. 407 * 408 * phy_ppdu_id 409 * A ppdu counter value that PHY increments for every PPDU 410 * received. The counter value wraps around. 411 * 412 * ast_index 413 * 414 * This field indicates the index of the AST entry corresponding 415 * to this MPDU. It is provided by the GSE module instantiated 416 * in RXPCU. 417 * A value of 0xFFFF indicates an invalid AST index, meaning 418 * that No AST entry was found or NO AST search was performed 419 * 420 * sw_peer_id 421 * In case of ndp or phy_err or AST_based_lookup_valid == 0, 422 * this field will be set to 0 423 * This field indicates a unique peer identifier. It is set 424 * equal to field 'sw_peer_id' from the AST entry 425 * 426 * frame_control_valid 427 * When set, the field Mpdu_Frame_control_field has valid information 428 * 429 * frame_duration_valid 430 * When set, the field Mpdu_duration_field has valid information 431 * 432 * mac_addr_ad1..4_valid 433 * When set, the fields mac_addr_adx_..... have valid information 434 * 435 * mpdu_seq_ctrl_valid 436 * 437 * When set, the fields mpdu_sequence_control_field and mpdu_sequence_number 438 * have valid information as well as field 439 * For MPDUs without a sequence control field, this field will 440 * not be set. 441 * 442 * mpdu_qos_ctrl_valid, mpdu_ht_ctrl_valid 443 * 444 * When set, the field mpdu_qos_control_field, mpdu_ht_control has valid 445 * information, For MPDUs without a QoS,HT control field, this field 446 * will not be set. 447 * 448 * frame_encryption_info_valid 449 * 450 * When set, the encryption related info fields, like IV and 451 * PN are valid 452 * For MPDUs that are not encrypted, this will not be set. 453 * 454 * mpdu_fragment_number 455 * 456 * Field only valid when Mpdu_sequence_control_valid is set 457 * AND Fragment_flag is set. The fragment number from the 802.11 header 458 * 459 * more_fragment_flag 460 * 461 * The More Fragment bit setting from the MPDU header of the 462 * received frame 463 * 464 * fr_ds 465 * 466 * Field only valid when Mpdu_frame_control_valid is set 467 * Set if the from DS bit is set in the frame control. 468 * 469 * to_ds 470 * 471 * Field only valid when Mpdu_frame_control_valid is set 472 * Set if the to DS bit is set in the frame control. 473 * 474 * encrypted 475 * 476 * Field only valid when Mpdu_frame_control_valid is set. 477 * Protected bit from the frame control. 478 * 479 * mpdu_retry 480 * Field only valid when Mpdu_frame_control_valid is set. 481 * Retry bit from the frame control. Only valid when first_msdu is set 482 * 483 * mpdu_sequence_number 484 * Field only valid when Mpdu_sequence_control_valid is set. 485 * 486 * The sequence number from the 802.11 header. 487 * key_id 488 * The key ID octet from the IV. 489 * Field only valid when Frame_encryption_info_valid is set 490 * 491 * new_peer_entry 492 * Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY 493 * doesn't follow so RX DECRYPTION module either uses old peer 494 * entry or not decrypt. 495 * 496 * decrypt_needed 497 * When RXPCU sets bit 'ast_index_not_found or ast_index_timeout', 498 * RXPCU will also ensure that this bit is NOT set. CRYPTO for that 499 * reason only needs to evaluate this bit and non of the other ones 500 * 501 * decap_type 502 * Used by the OLE during decapsulation. Values are defined in 503 * enum %MPDU_START_DECAP_TYPE_*. 504 * 505 * rx_insert_vlan_c_tag_padding 506 * rx_insert_vlan_s_tag_padding 507 * Insert 4 byte of all zeros as VLAN tag or double VLAN tag if 508 * the rx payload does not have VLAN. 509 * 510 * strip_vlan_c_tag_decap 511 * strip_vlan_s_tag_decap 512 * Strip VLAN or double VLAN during decapsulation. 513 * 514 * pre_delim_count 515 * The number of delimiters before this MPDU. Note that this 516 * number is cleared at PPDU start. If this MPDU is the first 517 * received MPDU in the PPDU and this MPDU gets filtered-in, 518 * this field will indicate the number of delimiters located 519 * after the last MPDU in the previous PPDU. 520 * 521 * If this MPDU is located after the first received MPDU in 522 * an PPDU, this field will indicate the number of delimiters 523 * located between the previous MPDU and this MPDU. 524 * 525 * ampdu_flag 526 * Received frame was part of an A-MPDU. 527 * 528 * bar_frame 529 * Received frame is a BAR frame 530 * 531 * raw_mpdu 532 * Set when no 802.11 to nwifi/ethernet hdr conversion is done 533 * 534 * mpdu_length 535 * MPDU length before decapsulation. 536 * 537 * first_mpdu 538 * Indicates the first MSDU of the PPDU. If both first_mpdu 539 * and last_mpdu are set in the MSDU then this is a not an 540 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an 541 * A-MPDU shall have both first_mpdu and last_mpdu bits set to 542 * 0. The PPDU start status will only be valid when this bit 543 * is set. 544 * 545 * mcast_bcast 546 * Multicast / broadcast indicator. Only set when the MAC 547 * address 1 bit 0 is set indicating mcast/bcast and the BSSID 548 * matches one of the 4 BSSID registers. Only set when 549 * first_msdu is set. 550 * 551 * ast_index_not_found 552 * Only valid when first_msdu is set. Indicates no AST matching 553 * entries within the max search count. 554 * 555 * ast_index_timeout 556 * Only valid when first_msdu is set. Indicates an unsuccessful 557 * search in the address search table due to timeout. 558 * 559 * power_mgmt 560 * Power management bit set in the 802.11 header. Only set 561 * when first_msdu is set. 562 * 563 * non_qos 564 * Set if packet is not a non-QoS data frame. Only set when 565 * first_msdu is set. 566 * 567 * null_data 568 * Set if frame type indicates either null data or QoS null 569 * data format. Only set when first_msdu is set. 570 * 571 * mgmt_type 572 * Set if packet is a management packet. Only set when 573 * first_msdu is set. 574 * 575 * ctrl_type 576 * Set if packet is a control packet. Only set when first_msdu 577 * is set. 578 * 579 * more_data 580 * Set if more bit in frame control is set. Only set when 581 * first_msdu is set. 582 * 583 * eosp 584 * Set if the EOSP (end of service period) bit in the QoS 585 * control field is set. Only set when first_msdu is set. 586 * 587 * 588 * fragment_flag 589 * Fragment indication 590 * 591 * order 592 * Set if the order bit in the frame control is set. Only 593 * set when first_msdu is set. 594 * 595 * u_apsd_trigger 596 * U-APSD trigger frame 597 * 598 * encrypt_required 599 * Indicates that this data type frame is not encrypted even if 600 * the policy for this MPDU requires encryption as indicated in 601 * the peer table key type. 602 * 603 * directed 604 * MPDU is a directed packet which means that the RA matched 605 * our STA addresses. In proxySTA it means that the TA matched 606 * an entry in our address search table with the corresponding 607 * 'no_ack' bit is the address search entry cleared. 608 * amsdu_present 609 * AMSDU present 610 * 611 * mpdu_frame_control_field 612 * Frame control field in header. Only valid when the field is marked valid. 613 * 614 * mpdu_duration_field 615 * Duration field in header. Only valid when the field is marked valid. 616 * 617 * mac_addr_adx 618 * MAC addresses in the received frame. Only valid when corresponding 619 * address valid bit is set 620 * 621 * mpdu_qos_control_field, mpdu_ht_control_field 622 * QoS/HT control fields from header. Valid only when corresponding fields 623 * are marked valid 624 * 625 * vdev_id 626 * Virtual device associated with this peer 627 * RXOLE uses this to determine intra-BSS routing. 628 * 629 * service_code 630 * Opaque service code between PPE and Wi-Fi 631 * This field gets passed on by REO to PPE in the EDMA descriptor 632 * ('REO_TO_PPE_RING'). 633 * 634 * priority_valid 635 * This field gets passed on by REO to PPE in the EDMA descriptor 636 * ('REO_TO_PPE_RING'). 637 * 638 * src_info 639 * Source (virtual) device/interface info. associated with 640 * this peer 641 * This field gets passed on by REO to PPE in the EDMA descriptor 642 * ('REO_TO_PPE_RING'). 643 * 644 * multi_link_addr_ad1_ad2_valid 645 * If set, Rx OLE shall convert Address1 and Address2 of received 646 * data frames to multi-link addresses during decapsulation to eth/nwifi 647 * 648 * multi_link_addr_ad1,ad2 649 * Multi-link receiver address1,2. Only valid when corresponding 650 * valid bit is set 651 * 652 * authorize_to_send_wds 653 * If not set, RXDMA shall perform error-routing for WDS packets 654 * as the sender is not authorized and might misuse WDS frame 655 * format to inject packets with arbitrary DA/SA. 656 * 657 */ 658 659 #define RX_MSDU_END_64_TLV_SRC_LINK_ID GENMASK(24, 22) 660 661 #define RX_MSDU_END_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0) 662 #define RX_MSDU_END_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2) 663 664 #define RX_MSDU_END_INFO1_REPORTED_MPDU_LENGTH GENMASK(13, 0) 665 666 #define RX_MSDU_END_INFO2_CCE_SUPER_RULE GENMASK(13, 8) 667 #define RX_MSDU_END_INFO2_CCND_TRUNCATE BIT(14) 668 #define RX_MSDU_END_INFO2_CCND_CCE_DIS BIT(15) 669 670 #define RX_MSDU_END_INFO3_DA_OFFSET GENMASK(5, 0) 671 #define RX_MSDU_END_INFO3_SA_OFFSET GENMASK(11, 6) 672 #define RX_MSDU_END_INFO3_DA_OFFSET_VALID BIT(12) 673 #define RX_MSDU_END_INFO3_SA_OFFSET_VALID BIT(13) 674 675 #define RX_MSDU_END_INFO4_TCP_FLAG GENMASK(8, 0) 676 #define RX_MSDU_END_INFO4_LRO_ELIGIBLE BIT(9) 677 678 #define RX_MSDU_END_INFO5_SA_IDX_TIMEOUT BIT(0) 679 #define RX_MSDU_END_INFO5_DA_IDX_TIMEOUT BIT(1) 680 #define RX_MSDU_END_INFO5_TO_DS BIT(2) 681 #define RX_MSDU_END_INFO5_TID GENMASK(6, 3) 682 #define RX_MSDU_END_INFO5_SA_IS_VALID BIT(7) 683 #define RX_MSDU_END_INFO5_DA_IS_VALID BIT(8) 684 #define RX_MSDU_END_INFO5_DA_IS_MCBC BIT(9) 685 #define RX_MSDU_END_INFO5_L3_HDR_PADDING GENMASK(11, 10) 686 #define RX_MSDU_END_INFO5_FIRST_MSDU BIT(12) 687 #define RX_MSDU_END_INFO5_LAST_MSDU BIT(13) 688 #define RX_MSDU_END_INFO5_FROM_DS BIT(14) 689 #define RX_MSDU_END_INFO5_IP_CHKSUM_FAIL_COPY BIT(15) 690 691 #define RX_MSDU_END_INFO6_MSDU_DROP BIT(0) 692 #define RX_MSDU_END_INFO6_REO_DEST_IND GENMASK(5, 1) 693 #define RX_MSDU_END_INFO6_FLOW_IDX GENMASK(25, 6) 694 #define RX_MSDU_END_INFO6_USE_PPE BIT(26) 695 #define RX_MSDU_END_INFO6_MESH_STA GENMASK(28, 27) 696 #define RX_MSDU_END_INFO6_VLAN_CTAG_STRIPPED BIT(29) 697 #define RX_MSDU_END_INFO6_VLAN_STAG_STRIPPED BIT(30) 698 #define RX_MSDU_END_INFO6_FRAGMENT_FLAG BIT(31) 699 700 #define RX_MSDU_END_INFO7_AGGR_COUNT GENMASK(7, 0) 701 #define RX_MSDU_END_INFO7_FLOW_AGGR_CONTN BIT(8) 702 #define RX_MSDU_END_INFO7_FISA_TIMEOUT BIT(9) 703 704 #define RX_MSDU_END_INFO7_TCPUDP_CSUM_FAIL_CPY BIT(10) 705 #define RX_MSDU_END_INFO7_MSDU_LIMIT_ERROR BIT(11) 706 #define RX_MSDU_END_INFO7_FLOW_IDX_TIMEOUT BIT(12) 707 #define RX_MSDU_END_INFO7_FLOW_IDX_INVALID BIT(13) 708 #define RX_MSDU_END_INFO7_CCE_MATCH BIT(14) 709 #define RX_MSDU_END_INFO7_AMSDU_PARSER_ERR BIT(15) 710 711 #define RX_MSDU_END_INFO8_KEY_ID GENMASK(7, 0) 712 713 #define RX_MSDU_END_INFO9_SERVICE_CODE GENMASK(14, 6) 714 #define RX_MSDU_END_INFO9_PRIORITY_VALID BIT(15) 715 #define RX_MSDU_END_INFO9_INRA_BSS BIT(16) 716 #define RX_MSDU_END_INFO9_DEST_CHIP_ID GENMASK(18, 17) 717 #define RX_MSDU_END_INFO9_MCAST_ECHO BIT(19) 718 #define RX_MSDU_END_INFO9_WDS_LEARN_EVENT BIT(20) 719 #define RX_MSDU_END_INFO9_WDS_ROAM_EVENT BIT(21) 720 #define RX_MSDU_END_INFO9_WDS_KEEP_ALIVE_EVENT BIT(22) 721 722 #define RX_MSDU_END_INFO10_MSDU_LENGTH GENMASK(13, 0) 723 #define RX_MSDU_END_INFO10_STBC BIT(14) 724 #define RX_MSDU_END_INFO10_IPSEC_ESP BIT(15) 725 #define RX_MSDU_END_INFO10_L3_OFFSET GENMASK(22, 16) 726 #define RX_MSDU_END_INFO10_IPSEC_AH BIT(23) 727 #define RX_MSDU_END_INFO10_L4_OFFSET GENMASK(31, 24) 728 729 #define RX_MSDU_END_INFO11_MSDU_NUMBER GENMASK(7, 0) 730 #define RX_MSDU_END_INFO11_DECAP_FORMAT GENMASK(9, 8) 731 #define RX_MSDU_END_INFO11_IPV4 BIT(10) 732 #define RX_MSDU_END_INFO11_IPV6 BIT(11) 733 #define RX_MSDU_END_INFO11_TCP BIT(12) 734 #define RX_MSDU_END_INFO11_UDP BIT(13) 735 #define RX_MSDU_END_INFO11_IP_FRAG BIT(14) 736 #define RX_MSDU_END_INFO11_TCP_ONLY_ACK BIT(15) 737 #define RX_MSDU_END_INFO11_DA_IS_BCAST_MCAST BIT(16) 738 #define RX_MSDU_END_INFO11_SEL_TOEPLITZ_HASH GENMASK(18, 17) 739 #define RX_MSDU_END_INFO11_IP_FIXED_HDR_VALID BIT(19) 740 #define RX_MSDU_END_INFO11_IP_EXTN_HDR_VALID BIT(20) 741 #define RX_MSDU_END_INFO11_IP_TCP_UDP_HDR_VALID BIT(21) 742 #define RX_MSDU_END_INFO11_MESH_CTRL_PRESENT BIT(22) 743 #define RX_MSDU_END_INFO11_LDPC BIT(23) 744 #define RX_MSDU_END_INFO11_IP4_IP6_NXT_HDR GENMASK(31, 24) 745 746 #define RX_MSDU_END_INFO12_USER_RSSI GENMASK(7, 0) 747 #define RX_MSDU_END_INFO12_PKT_TYPE GENMASK(11, 8) 748 #define RX_MSDU_END_INFO12_SGI GENMASK(13, 12) 749 #define RX_MSDU_END_INFO12_RATE_MCS GENMASK(17, 14) 750 #define RX_MSDU_END_INFO12_RECV_BW GENMASK(20, 18) 751 #define RX_MSDU_END_INFO12_RECEPTION_TYPE GENMASK(23, 21) 752 753 #define RX_MSDU_END_INFO12_MIMO_SS_BITMAP GENMASK(30, 24) 754 #define RX_MSDU_END_INFO12_MIMO_DONE_COPY BIT(31) 755 756 #define RX_MSDU_END_INFO13_FIRST_MPDU BIT(0) 757 #define RX_MSDU_END_INFO13_MCAST_BCAST BIT(2) 758 #define RX_MSDU_END_INFO13_AST_IDX_NOT_FOUND BIT(3) 759 #define RX_MSDU_END_INFO13_AST_IDX_TIMEDOUT BIT(4) 760 #define RX_MSDU_END_INFO13_POWER_MGMT BIT(5) 761 #define RX_MSDU_END_INFO13_NON_QOS BIT(6) 762 #define RX_MSDU_END_INFO13_NULL_DATA BIT(7) 763 #define RX_MSDU_END_INFO13_MGMT_TYPE BIT(8) 764 #define RX_MSDU_END_INFO13_CTRL_TYPE BIT(9) 765 #define RX_MSDU_END_INFO13_MORE_DATA BIT(10) 766 #define RX_MSDU_END_INFO13_EOSP BIT(11) 767 #define RX_MSDU_END_INFO13_A_MSDU_ERROR BIT(12) 768 #define RX_MSDU_END_INFO13_ORDER BIT(14) 769 #define RX_MSDU_END_INFO13_OVERFLOW_ERR BIT(16) 770 #define RX_MSDU_END_INFO13_MSDU_LEN_ERR BIT(17) 771 #define RX_MSDU_END_INFO13_TCP_UDP_CKSUM_FAIL BIT(18) 772 #define RX_MSDU_END_INFO13_IP_CKSUM_FAIL BIT(19) 773 #define RX_MSDU_END_INFO13_SA_IDX_INVALID BIT(20) 774 #define RX_MSDU_END_INFO13_DA_IDX_INVALID BIT(21) 775 #define RX_MSDU_END_INFO13_AMSDU_ADDR_MISMATCH BIT(22) 776 #define RX_MSDU_END_INFO13_RX_IN_TX_DECRYPT_BYP BIT(23) 777 #define RX_MSDU_END_INFO13_ENCRYPT_REQUIRED BIT(24) 778 #define RX_MSDU_END_INFO13_DIRECTED BIT(25) 779 #define RX_MSDU_END_INFO13_BUFFER_FRAGMENT BIT(26) 780 #define RX_MSDU_END_INFO13_MPDU_LEN_ERR BIT(27) 781 #define RX_MSDU_END_INFO13_TKIP_MIC_ERR BIT(28) 782 #define RX_MSDU_END_INFO13_DECRYPT_ERR BIT(29) 783 #define RX_MSDU_END_INFO13_UNDECRYPT_FRAME_ERR BIT(30) 784 #define RX_MSDU_END_INFO13_FCS_ERR BIT(31) 785 786 #define RX_MSDU_END_INFO13_WIFI_PARSER_ERR BIT(15) 787 788 #define RX_MSDU_END_INFO14_DECRYPT_STATUS_CODE GENMASK(12, 10) 789 #define RX_MSDU_END_INFO14_RX_BITMAP_NOT_UPDED BIT(13) 790 #define RX_MSDU_END_INFO14_MSDU_DONE BIT(31) 791 792 struct rx_msdu_end_qcn9274 { 793 __le16 info0; 794 __le16 phy_ppdu_id; 795 __le16 ip_hdr_cksum; 796 __le16 info1; 797 __le16 info2; 798 __le16 cumulative_l3_checksum; 799 __le32 rule_indication0; 800 __le32 ipv6_options_crc; 801 __le16 info3; 802 __le16 l3_type; 803 __le32 rule_indication1; 804 __le32 tcp_seq_num; 805 __le32 tcp_ack_num; 806 __le16 info4; 807 __le16 window_size; 808 __le16 sa_sw_peer_id; 809 __le16 info5; 810 __le16 sa_idx; 811 __le16 da_idx_or_sw_peer_id; 812 __le32 info6; 813 __le32 fse_metadata; 814 __le16 cce_metadata; 815 __le16 tcp_udp_cksum; 816 __le16 info7; 817 __le16 cumulative_ip_length; 818 __le32 info8; 819 __le32 info9; 820 __le32 info10; 821 __le32 info11; 822 __le16 vlan_ctag_ci; 823 __le16 vlan_stag_ci; 824 __le32 peer_meta_data; 825 __le32 info12; 826 __le32 flow_id_toeplitz; 827 __le32 ppdu_start_timestamp_63_32; 828 __le32 phy_meta_data; 829 __le32 ppdu_start_timestamp_31_0; 830 __le32 toeplitz_hash_2_or_4; 831 __le16 res0; 832 __le16 sa_15_0; 833 __le32 sa_47_16; 834 __le32 info13; 835 __le32 info14; 836 } __packed; 837 838 #define QCN9274_MSDU_END_SELECT_MSDU_END_TAG BIT(0) 839 #define QCN9274_MSDU_END_SELECT_INFO0_PHY_PPDUID_IP_HDR_CSUM_INFO1 BIT(1) 840 #define QCN9274_MSDU_END_SELECT_INFO2_CUMULATIVE_CSUM_RULE_IND_0 BIT(2) 841 #define QCN9274_MSDU_END_SELECT_IPV6_OP_CRC_INFO3_TYPE13 BIT(3) 842 #define QCN9274_MSDU_END_SELECT_RULE_IND_1_TCP_SEQ_NUM BIT(4) 843 #define QCN9274_MSDU_END_SELECT_TCP_ACK_NUM_INFO4_WINDOW_SIZE BIT(5) 844 #define QCN9274_MSDU_END_SELECT_SA_SW_PER_ID_INFO5_SA_DA_ID BIT(6) 845 #define QCN9274_MSDU_END_SELECT_INFO6_FSE_METADATA BIT(7) 846 #define QCN9274_MSDU_END_SELECT_CCE_MDATA_TCP_UDP_CSUM_INFO7_IP_LEN BIT(8) 847 #define QCN9274_MSDU_END_SELECT_INFO8_INFO9 BIT(9) 848 #define QCN9274_MSDU_END_SELECT_INFO10_INFO11 BIT(10) 849 #define QCN9274_MSDU_END_SELECT_VLAN_CTAG_STAG_CI_PEER_MDATA BIT(11) 850 #define QCN9274_MSDU_END_SELECT_INFO12_AND_FLOW_ID_TOEPLITZ BIT(12) 851 #define QCN9274_MSDU_END_SELECT_PPDU_START_TS_63_32_PHY_MDATA BIT(13) 852 #define QCN9274_MSDU_END_SELECT_PPDU_START_TS_31_0_TOEPLITZ_HASH_2_4 BIT(14) 853 #define QCN9274_MSDU_END_SELECT_RES0_SA_47_0 BIT(15) 854 #define QCN9274_MSDU_END_SELECT_INFO13_INFO14 BIT(16) 855 856 #define QCN9274_MSDU_END_WMASK (QCN9274_MSDU_END_SELECT_MSDU_END_TAG | \ 857 QCN9274_MSDU_END_SELECT_SA_SW_PER_ID_INFO5_SA_DA_ID | \ 858 QCN9274_MSDU_END_SELECT_INFO10_INFO11 | \ 859 QCN9274_MSDU_END_SELECT_INFO12_AND_FLOW_ID_TOEPLITZ | \ 860 QCN9274_MSDU_END_SELECT_PPDU_START_TS_63_32_PHY_MDATA | \ 861 QCN9274_MSDU_END_SELECT_INFO13_INFO14) 862 863 /* The below rx_msdu_end_qcn9274_compact structure is tied with the mask value 864 * QCN9274_MSDU_END_WMASK. If the mask value changes the structure will also 865 * change. 866 */ 867 868 struct rx_msdu_end_qcn9274_compact { 869 __le64 msdu_end_tag; 870 __le16 sa_sw_peer_id; 871 __le16 info5; 872 __le16 sa_idx; 873 __le16 da_idx_or_sw_peer_id; 874 __le32 info10; 875 __le32 info11; 876 __le32 info12; 877 __le32 flow_id_toeplitz; 878 __le32 ppdu_start_timestamp_63_32; 879 __le32 phy_meta_data; 880 __le32 info13; 881 __le32 info14; 882 } __packed; 883 884 /* rx_msdu_end 885 * 886 * rxpcu_mpdu_filter_in_category 887 * Field indicates what the reason was that this mpdu frame 888 * was allowed to come into the receive path by rxpcu. Values 889 * are defined in enum %RX_DESC_RXPCU_FILTER_*. 890 * 891 * sw_frame_group_id 892 * SW processes frames based on certain classifications. Values 893 * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 894 * 895 * phy_ppdu_id 896 * A ppdu counter value that PHY increments for every PPDU 897 * received. The counter value wraps around. 898 * 899 * ip_hdr_cksum 900 * This can include the IP header checksum or the pseudo 901 * header checksum used by TCP/UDP checksum. 902 * 903 * reported_mpdu_length 904 * MPDU length before decapsulation. Only valid when first_msdu is 905 * set. This field is taken directly from the length field of the 906 * A-MPDU delimiter or the preamble length field for non-A-MPDU 907 * frames. 908 * 909 * cce_super_rule 910 * Indicates the super filter rule. 911 * 912 * cce_classify_not_done_truncate 913 * Classification failed due to truncated frame. 914 * 915 * cce_classify_not_done_cce_dis 916 * Classification failed due to CCE global disable 917 * 918 * cumulative_l3_checksum 919 * FISA: IP header checksum including the total MSDU length 920 * that is part of this flow aggregated so far, reported if 921 * 'RXOLE_R0_FISA_CTRL. CHKSUM_CUM_IP_LEN_EN' is set 922 * 923 * rule_indication 924 * Bitmap indicating which of rules have matched. 925 * 926 * ipv6_options_crc 927 * 32 bit CRC computed out of IP v6 extension headers. 928 * 929 * da_offset 930 * Offset into MSDU buffer for DA. 931 * 932 * sa_offset 933 * Offset into MSDU buffer for SA. 934 * 935 * da_offset_valid 936 * da_offset field is valid. This will be set to 0 in case 937 * of a dynamic A-MSDU when DA is compressed. 938 * 939 * sa_offset_valid 940 * sa_offset field is valid. This will be set to 0 in case 941 * of a dynamic A-MSDU when SA is compressed. 942 * 943 * l3_type 944 * The 16-bit type value indicating the type of L3 later 945 * extracted from LLC/SNAP, set to zero if SNAP is not 946 * available. 947 * 948 * tcp_seq_number 949 * TCP sequence number. 950 * 951 * tcp_ack_number 952 * TCP acknowledge number. 953 * 954 * tcp_flag 955 * TCP flags {NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN}. 956 * 957 * lro_eligible 958 * Computed out of TCP and IP fields to indicate that this 959 * MSDU is eligible for LRO. 960 * 961 * window_size 962 * TCP receive window size. 963 * 964 * sa_sw_peer_id 965 * sw_peer_id from the address search entry corresponding to the 966 * source address of the MSDU. 967 * 968 * sa_idx_timeout 969 * Indicates an unsuccessful MAC source address search due to the 970 * expiring of the search timer. 971 * 972 * da_idx_timeout 973 * Indicates an unsuccessful MAC destination address search due to 974 * the expiring of the search timer. 975 * 976 * to_ds 977 * Set if the to DS bit is set in the frame control. 978 * 979 * tid 980 * TID field in the QoS control field 981 * 982 * sa_is_valid 983 * Indicates that OLE found a valid SA entry. 984 * 985 * da_is_valid 986 * Indicates that OLE found a valid DA entry. 987 * 988 * da_is_mcbc 989 * Field Only valid if da_is_valid is set. Indicates the DA address 990 * was a Multicast of Broadcast address. 991 * 992 * l3_header_padding 993 * Number of bytes padded to make sure that the L3 header will 994 * always start of a Dword boundary. 995 * 996 * first_msdu 997 * Indicates the first MSDU of A-MSDU. If both first_msdu and 998 * last_msdu are set in the MSDU then this is a non-aggregated MSDU 999 * frame: normal MPDU. Interior MSDU in an A-MSDU shall have both 1000 * first_mpdu and last_mpdu bits set to 0. 1001 * 1002 * last_msdu 1003 * Indicates the last MSDU of the A-MSDU. MPDU end status is only 1004 * valid when last_msdu is set. 1005 * 1006 * fr_ds 1007 * Set if the from DS bit is set in the frame control. 1008 * 1009 * ip_chksum_fail_copy 1010 * Indicates that the computed checksum did not match the 1011 * checksum in the IP header. 1012 * 1013 * sa_idx 1014 * The offset in the address table which matches the MAC source 1015 * address. 1016 * 1017 * da_idx_or_sw_peer_id 1018 * Based on a register configuration in RXOLE, this field will 1019 * contain: 1020 * The offset in the address table which matches the MAC destination 1021 * address 1022 * OR: 1023 * sw_peer_id from the address search entry corresponding to 1024 * the destination address of the MSDU 1025 * 1026 * msdu_drop 1027 * REO shall drop this MSDU and not forward it to any other ring. 1028 * 1029 * The id of the reo exit ring where the msdu frame shall push 1030 * after (MPDU level) reordering has finished. Values are defined 1031 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 1032 * 1033 * flow_idx 1034 * Flow table index. 1035 * 1036 * use_ppe 1037 * Indicates to RXDMA to ignore the REO_destination_indication 1038 * and use a programmed value corresponding to the REO2PPE 1039 * ring 1040 * 1041 * mesh_sta 1042 * When set, this is a Mesh (11s) STA. 1043 * 1044 * vlan_ctag_stripped 1045 * Set by RXOLE if it stripped 4-bytes of C-VLAN Tag from the 1046 * packet 1047 * 1048 * vlan_stag_stripped 1049 * Set by RXOLE if it stripped 4-bytes of S-VLAN Tag from the 1050 * packet 1051 * 1052 * fragment_flag 1053 * Indicates that this is an 802.11 fragment frame. This is 1054 * set when either the more_frag bit is set in the frame control 1055 * or the fragment number is not zero. Only set when first_msdu 1056 * is set. 1057 * 1058 * fse_metadata 1059 * FSE related meta data. 1060 * 1061 * cce_metadata 1062 * CCE related meta data. 1063 * 1064 * tcp_udp_chksum 1065 * The value of the computed TCP/UDP checksum. A mode bit 1066 * selects whether this checksum is the full checksum or the 1067 * partial checksum which does not include the pseudo header. 1068 * 1069 * aggregation_count 1070 * Number of MSDU's aggregated so far 1071 * 1072 * flow_aggregation_continuation 1073 * To indicate that this MSDU can be aggregated with 1074 * the previous packet with the same flow id 1075 * 1076 * fisa_timeout 1077 * To indicate that the aggregation has restarted for 1078 * this flow due to timeout 1079 * 1080 * tcp_udp_chksum_fail 1081 * Indicates that the computed checksum (tcp_udp_chksum) did 1082 * not match the checksum in the TCP/UDP header. 1083 * 1084 * msdu_limit_error 1085 * Indicates that the MSDU threshold was exceeded and thus all the 1086 * rest of the MSDUs will not be scattered and will not be 1087 * decapsulated but will be DMA'ed in RAW format as a single MSDU. 1088 * 1089 * flow_idx_timeout 1090 * Indicates an unsuccessful flow search due to the expiring of 1091 * the search timer. 1092 * 1093 * flow_idx_invalid 1094 * flow id is not valid. 1095 * 1096 * cce_match 1097 * Indicates that this status has a corresponding MSDU that 1098 * requires FW processing. The OLE will have classification 1099 * ring mask registers which will indicate the ring(s) for 1100 * packets and descriptors which need FW attention. 1101 * 1102 * amsdu_parser_error 1103 * A-MSDU could not be properly de-agregated. 1104 * 1105 * cumulative_ip_length 1106 * Total MSDU length that is part of this flow aggregated 1107 * so far 1108 * 1109 * key_id 1110 * The key ID octet from the IV. Only valid when first_msdu is set. 1111 * 1112 * service_code 1113 * Opaque service code between PPE and Wi-Fi 1114 * 1115 * priority_valid 1116 * This field gets passed on by REO to PPE in the EDMA descriptor 1117 * 1118 * intra_bss 1119 * This packet needs intra-BSS routing by SW as the 'vdev_id' 1120 * for the destination is the same as 'vdev_id' (from 'RX_MPDU_PCU_START') 1121 * that this MSDU was got in. 1122 * 1123 * dest_chip_id 1124 * If intra_bss is set, copied by RXOLE from 'ADDR_SEARCH_ENTRY' 1125 * to support intra-BSS routing with multi-chip multi-link 1126 * operation. This indicates into which chip's TCL the packet should be 1127 * queueued 1128 * 1129 * multicast_echo 1130 * If set, this packet is a multicast echo, i.e. the DA is 1131 * multicast and Rx OLE SA search with mcast_echo_check = 1 1132 * passed. RXDMA should release such packets to WBM. 1133 * 1134 * wds_learning_event 1135 * If set, this packet has an SA search failure with WDS learning 1136 * enabled for the peer. RXOLE should route this TLV to the 1137 * RXDMA0 status ring to notify FW. 1138 * 1139 * wds_roaming_event 1140 * If set, this packet's SA 'Sw_peer_id' mismatches the 'Sw_peer_id' 1141 * of the peer through which the packet was got, indicating 1142 * the SA node has roamed. RXOLE should route this TLV to 1143 * the RXDMA0 status ring to notify FW. 1144 * 1145 * wds_keep_alive_event 1146 * If set, the AST timestamp for this packet's SA is older 1147 * than the current timestamp by more than a threshold programmed 1148 * in RXOLE. RXOLE should route this TLV to the RXDMA0 status 1149 * ring to notify FW to keep the AST entry for the SA alive. 1150 * 1151 * msdu_length 1152 * MSDU length in bytes after decapsulation. 1153 * This field is still valid for MPDU frames without A-MSDU. 1154 * It still represents MSDU length after decapsulation 1155 * 1156 * stbc 1157 * When set, use STBC transmission rates. 1158 * 1159 * ipsec_esp 1160 * Set if IPv4/v6 packet is using IPsec ESP. 1161 * 1162 * l3_offset 1163 * Depending upon mode bit, this field either indicates the 1164 * L3 offset in bytes from the start of the RX_HEADER or the IP 1165 * offset in bytes from the start of the packet after 1166 * decapsulation. The latter is only valid if ipv4_proto or 1167 * ipv6_proto is set. 1168 * 1169 * ipsec_ah 1170 * Set if IPv4/v6 packet is using IPsec AH 1171 * 1172 * l4_offset 1173 * Depending upon mode bit, this field either indicates the 1174 * L4 offset in bytes from the start of RX_HEADER (only valid 1175 * if either ipv4_proto or ipv6_proto is set to 1) or indicates 1176 * the offset in bytes to the start of TCP or UDP header from 1177 * the start of the IP header after decapsulation (Only valid if 1178 * tcp_proto or udp_proto is set). The value 0 indicates that 1179 * the offset is longer than 127 bytes. 1180 * 1181 * msdu_number 1182 * Indicates the MSDU number within a MPDU. This value is 1183 * reset to zero at the start of each MPDU. If the number of 1184 * MSDU exceeds 255 this number will wrap using modulo 256. 1185 * 1186 * decap_type 1187 * Indicates the format after decapsulation. Values are defined in 1188 * enum %MPDU_START_DECAP_TYPE_*. 1189 * 1190 * ipv4_proto 1191 * Set if L2 layer indicates IPv4 protocol. 1192 * 1193 * ipv6_proto 1194 * Set if L2 layer indicates IPv6 protocol. 1195 * 1196 * tcp_proto 1197 * Set if the ipv4_proto or ipv6_proto are set and the IP protocol 1198 * indicates TCP. 1199 * 1200 * udp_proto 1201 * Set if the ipv4_proto or ipv6_proto are set and the IP protocol 1202 * indicates UDP. 1203 * 1204 * ip_frag 1205 * Indicates that either the IP More frag bit is set or IP frag 1206 * number is non-zero. If set indicates that this is a fragmented 1207 * IP packet. 1208 * 1209 * tcp_only_ack 1210 * Set if only the TCP Ack bit is set in the TCP flags and if 1211 * the TCP payload is 0. 1212 * 1213 * da_is_bcast_mcast 1214 * The destination address is broadcast or multicast. 1215 * 1216 * toeplitz_hash 1217 * Actual chosen Hash. 1218 * 0 - Toeplitz hash of 2-tuple (IP source address, IP 1219 * destination address) 1220 * 1 - Toeplitz hash of 4-tuple (IP source address, 1221 * IP destination address, L4 (TCP/UDP) source port, 1222 * L4 (TCP/UDP) destination port) 1223 * 2 - Toeplitz of flow_id 1224 * 3 - Zero is used 1225 * 1226 * ip_fixed_header_valid 1227 * Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed 1228 * fully within first 256 bytes of the packet 1229 * 1230 * ip_extn_header_valid 1231 * IPv6/IPv6 header, including IPv4 options and 1232 * recognizable extension headers parsed fully within first 256 1233 * bytes of the packet 1234 * 1235 * tcp_udp_header_valid 1236 * Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP 1237 * header parsed fully within first 256 bytes of the packet 1238 * 1239 * mesh_control_present 1240 * When set, this MSDU includes the 'Mesh Control' field 1241 * 1242 * ldpc 1243 * 1244 * ip4_protocol_ip6_next_header 1245 * For IPv4, this is the 8 bit protocol field set). For IPv6 this 1246 * is the 8 bit next_header field. 1247 * 1248 * 1249 * vlan_ctag_ci 1250 * 2 bytes of C-VLAN Tag Control Information from WHO_L2_LLC 1251 * 1252 * vlan_stag_ci 1253 * 2 bytes of S-VLAN Tag Control Information from WHO_L2_LLC 1254 * in case of double VLAN 1255 * 1256 * peer_meta_data 1257 * Meta data that SW has programmed in the Peer table entry 1258 * of the transmitting STA. 1259 * 1260 * user_rssi 1261 * RSSI for this user 1262 * 1263 * pkt_type 1264 * Values are defined in enum %RX_MSDU_START_PKT_TYPE_*. 1265 * 1266 * sgi 1267 * Field only valid when pkt type is HT, VHT or HE. Values are 1268 * defined in enum %RX_MSDU_START_SGI_*. 1269 * 1270 * rate_mcs 1271 * MCS Rate used. 1272 * 1273 * receive_bandwidth 1274 * Full receive Bandwidth. Values are defined in enum 1275 * %RX_MSDU_START_RECV_*. 1276 * 1277 * reception_type 1278 * Indicates what type of reception this is and defined in enum 1279 * %RX_MSDU_START_RECEPTION_TYPE_*. 1280 * 1281 * mimo_ss_bitmap 1282 * Field only valid when 1283 * Reception_type is RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO or 1284 * RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO. 1285 * 1286 * Bitmap, with each bit indicating if the related spatial 1287 * stream is used for this STA 1288 * 1289 * LSB related to SS 0 1290 * 1291 * 0 - spatial stream not used for this reception 1292 * 1 - spatial stream used for this reception 1293 * 1294 * msdu_done_copy 1295 * If set indicates that the RX packet data, RX header data, 1296 * RX PPDU start descriptor, RX MPDU start/end descriptor, 1297 * RX MSDU start/end descriptors and RX Attention descriptor 1298 * are all valid. This bit is in the last 64-bit of the descriptor 1299 * expected to be subscribed in future hardware. 1300 * 1301 * flow_id_toeplitz 1302 * Toeplitz hash of 5-tuple 1303 * {IP source address, IP destination address, IP source port, IP 1304 * destination port, L4 protocol} in case of non-IPSec. 1305 * 1306 * In case of IPSec - Toeplitz hash of 4-tuple 1307 * {IP source address, IP destination address, SPI, L4 protocol} 1308 * 1309 * The relevant Toeplitz key registers are provided in RxOLE's 1310 * instance of common parser module. These registers are separate 1311 * from the Toeplitz keys used by ASE/FSE modules inside RxOLE. 1312 * The actual value will be passed on from common parser module 1313 * to RxOLE in one of the WHO_* TLVs. 1314 * 1315 * ppdu_start_timestamp 1316 * Timestamp that indicates when the PPDU that contained this MPDU 1317 * started on the medium. 1318 * 1319 * phy_meta_data 1320 * SW programmed Meta data provided by the PHY. Can be used for SW 1321 * to indicate the channel the device is on. 1322 * 1323 * toeplitz_hash_2_or_4 1324 * Controlled by multiple RxOLE registers for TCP/UDP over 1325 * IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple 1326 * IPv4 or IPv6 src/dest addresses is reported; or, Toeplitz 1327 * hash computed over 4-tuple IPv4 or IPv6 src/dest addresses 1328 * and src/dest ports is reported. The Flow_id_toeplitz hash 1329 * can also be reported here. Usually the hash reported here 1330 * is the one used for hash-based REO routing (see use_flow_id_toeplitz_clfy 1331 * in 'RXPT_CLASSIFY_INFO'). 1332 * 1333 * sa 1334 * Source MAC address 1335 * 1336 * first_mpdu 1337 * Indicates the first MSDU of the PPDU. If both first_mpdu 1338 * and last_mpdu are set in the MSDU then this is a not an 1339 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an 1340 * A-MPDU shall have both first_mpdu and last_mpdu bits set to 1341 * 0. The PPDU start status will only be valid when this bit 1342 * is set. 1343 * 1344 * mcast_bcast 1345 * Multicast / broadcast indicator. Only set when the MAC 1346 * address 1 bit 0 is set indicating mcast/bcast and the BSSID 1347 * matches one of the 4 BSSID registers. Only set when 1348 * first_msdu is set. 1349 * 1350 * ast_index_not_found 1351 * Only valid when first_msdu is set. Indicates no AST matching 1352 * entries within the max search count. 1353 * 1354 * ast_index_timeout 1355 * Only valid when first_msdu is set. Indicates an unsuccessful 1356 * search in the address search table due to timeout. 1357 * 1358 * power_mgmt 1359 * Power management bit set in the 802.11 header. Only set 1360 * when first_msdu is set. 1361 * 1362 * non_qos 1363 * Set if packet is not a non-QoS data frame. Only set when 1364 * first_msdu is set. 1365 * 1366 * null_data 1367 * Set if frame type indicates either null data or QoS null 1368 * data format. Only set when first_msdu is set. 1369 * 1370 * mgmt_type 1371 * Set if packet is a management packet. Only set when 1372 * first_msdu is set. 1373 * 1374 * ctrl_type 1375 * Set if packet is a control packet. Only set when first_msdu 1376 * is set. 1377 * 1378 * more_data 1379 * Set if more bit in frame control is set. Only set when 1380 * first_msdu is set. 1381 * 1382 * eosp 1383 * Set if the EOSP (end of service period) bit in the QoS 1384 * control field is set. Only set when first_msdu is set. 1385 * 1386 * a_msdu_error 1387 * Set if number of MSDUs in A-MSDU is above a threshold or if the 1388 * size of the MSDU is invalid. This receive buffer will contain 1389 * all of the remainder of MSDUs in this MPDU w/o decapsulation. 1390 * 1391 * order 1392 * Set if the order bit in the frame control is set. Only 1393 * set when first_msdu is set. 1394 * 1395 * wifi_parser_error 1396 * Indicates that the WiFi frame has one of the following errors 1397 * 1398 * overflow_err 1399 * RXPCU Receive FIFO ran out of space to receive the full MPDU. 1400 * Therefore this MPDU is terminated early and is thus corrupted. 1401 * 1402 * This MPDU will not be ACKed. 1403 * 1404 * RXPCU might still be able to correctly receive the following 1405 * MPDUs in the PPDU if enough fifo space became available in time. 1406 * 1407 * mpdu_length_err 1408 * Set by RXPCU if the expected MPDU length does not correspond 1409 * with the actually received number of bytes in the MPDU. 1410 * 1411 * tcp_udp_chksum_fail 1412 * Indicates that the computed checksum (tcp_udp_chksum) did 1413 * not match the checksum in the TCP/UDP header. 1414 * 1415 * ip_chksum_fail 1416 * Indicates that the computed checksum did not match the 1417 * checksum in the IP header. 1418 * 1419 * sa_idx_invalid 1420 * Indicates no matching entry was found in the address search 1421 * table for the source MAC address. 1422 * 1423 * da_idx_invalid 1424 * Indicates no matching entry was found in the address search 1425 * table for the destination MAC address. 1426 * 1427 * amsdu_addr_mismatch 1428 * Indicates that an A-MSDU with 'from DS = 0' had an SA mismatching 1429 * TA or an A-MDU with 'to DS = 0' had a DA mismatching RA 1430 * 1431 * rx_in_tx_decrypt_byp 1432 * Indicates that RX packet is not decrypted as Crypto is busy 1433 * with TX packet processing. 1434 * 1435 * encrypt_required 1436 * Indicates that this data type frame is not encrypted even if 1437 * the policy for this MPDU requires encryption as indicated in 1438 * the peer table key type. 1439 * 1440 * directed 1441 * MPDU is a directed packet which means that the RA matched 1442 * our STA addresses. In proxySTA it means that the TA matched 1443 * an entry in our address search table with the corresponding 1444 * 'no_ack' bit is the address search entry cleared. 1445 * 1446 * buffer_fragment 1447 * Indicates that at least one of the rx buffers has been 1448 * fragmented. If set the FW should look at the rx_frag_info 1449 * descriptor described below. 1450 * 1451 * mpdu_length_err 1452 * Indicates that the MPDU was pre-maturely terminated 1453 * resulting in a truncated MPDU. Don't trust the MPDU length 1454 * field. 1455 * 1456 * tkip_mic_err 1457 * Indicates that the MPDU Michael integrity check failed 1458 * 1459 * decrypt_err 1460 * Indicates that the MPDU decrypt integrity check failed 1461 * 1462 * fcs_err 1463 * Indicates that the MPDU FCS check failed 1464 * 1465 * flow_idx_timeout 1466 * Indicates an unsuccessful flow search due to the expiring of 1467 * the search timer. 1468 * 1469 * flow_idx_invalid 1470 * flow id is not valid. 1471 * 1472 * decrypt_status_code 1473 * Field provides insight into the decryption performed. Values 1474 * are defined in enum %RX_DESC_DECRYPT_STATUS_CODE_*. 1475 * 1476 * rx_bitmap_not_updated 1477 * Frame is received, but RXPCU could not update the receive bitmap 1478 * due to (temporary) fifo constraints. 1479 * 1480 * msdu_done 1481 * If set indicates that the RX packet data, RX header data, RX 1482 * PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU 1483 * start/end descriptors and RX Attention descriptor are all 1484 * valid. This bit must be in the last octet of the 1485 * descriptor. 1486 * 1487 */ 1488 1489 struct hal_rx_desc_qcn9274_compact { 1490 struct rx_msdu_end_qcn9274_compact msdu_end; 1491 struct rx_mpdu_start_qcn9274_compact mpdu_start; 1492 u8 msdu_payload[]; 1493 } __packed; 1494 1495 #define RX_BE_PADDING0_BYTES 8 1496 #define RX_BE_PADDING1_BYTES 8 1497 1498 #define HAL_RX_BE_PKT_HDR_TLV_LEN 112 1499 1500 struct rx_pkt_hdr_tlv { 1501 __le64 tag; 1502 __le64 phy_ppdu_id; 1503 u8 rx_pkt_hdr[HAL_RX_BE_PKT_HDR_TLV_LEN]; 1504 }; 1505 1506 struct hal_rx_desc_wcn7850 { 1507 __le64 msdu_end_tag; 1508 struct rx_msdu_end_qcn9274 msdu_end; 1509 u8 rx_padding0[RX_BE_PADDING0_BYTES]; 1510 __le64 mpdu_start_tag; 1511 struct rx_mpdu_start_qcn9274 mpdu_start; 1512 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 1513 u8 msdu_payload[]; 1514 }; 1515 1516 struct rx_pkt_hdr_tlv_qcc2072 { 1517 __le32 tag; 1518 __le64 phy_ppdu_id; 1519 u8 rx_pkt_hdr[HAL_RX_BE_PKT_HDR_TLV_LEN]; 1520 }; 1521 1522 struct hal_rx_desc_qcc2072 { 1523 __le32 msdu_end_tag; 1524 struct rx_msdu_end_qcn9274 msdu_end; 1525 u8 rx_padding0[RX_BE_PADDING0_BYTES]; 1526 __le32 mpdu_start_tag; 1527 struct rx_mpdu_start_qcc2072 mpdu_start; 1528 struct rx_pkt_hdr_tlv_qcc2072 pkt_hdr_tlv; 1529 u8 msdu_payload[]; 1530 }; 1531 1532 struct hal_rx_desc { 1533 union { 1534 struct hal_rx_desc_qcn9274_compact qcn9274_compact; 1535 struct hal_rx_desc_wcn7850 wcn7850; 1536 struct hal_rx_desc_qcc2072 qcc2072; 1537 } u; 1538 } __packed; 1539 1540 #endif /* ATH12K_RX_DESC_H */ 1541