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Searched refs:bw_params (Results 1 – 25 of 34) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c194 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()
195 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
203 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_… in dcn32_build_wm_range_table_fpu()
205 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_pa… in dcn32_build_wm_range_table_fpu()
207 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) in dcn32_build_wm_range_table_fpu()
208 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; in dcn32_build_wm_range_table_fpu()
211 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn32_build_wm_range_table_fpu()
212 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn32_build_wm_range_table_fpu()
213 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_… in dcn32_build_wm_range_table_fpu()
214 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn32_build_wm_range_table_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/
H A Ddcn42_clk_mgr.c635 void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_watermarks *table) in dcn42_build_watermark_ranges() argument
643 if (!bw_params->wm_table.entries[i].valid) in dcn42_build_watermark_ranges()
646 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn42_build_watermark_ranges()
647 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn42_build_watermark_ranges()
658 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn42_build_watermark_ranges()
661 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn42_build_watermark_ranges()
701 if (clk_mgr_base->bw_params->wm_table.entries[WM_A].valid == true) in dcn42_notify_wm_ranges()
719 clk_mgr_base->bw_params->wm_table.entries[i].wm_inst = i; in dcn42_notify_wm_ranges()
721 if (i >= clk_mgr_base->bw_params->clk_table.num_entries) { in dcn42_notify_wm_ranges()
722 clk_mgr_base->bw_params->wm_table.entries[i].valid = false; in dcn42_notify_wm_ranges()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
459 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
460 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
461 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
469 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn315_update_soc_for_wm_a()
474 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()
476 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; in dcn315_update_soc_for_wm_a()
478 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; in dcn315_update_soc_for_wm_a()
590 void dcn31_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) in dcn31_update_bw_bounding_box_fpu() argument
593 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn31_update_bw_bounding_box_fpu()
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H A Ddcn31_fpu.h47 void dcn31_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
48 void dcn315_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
49 void dcn316_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
/linux/drivers/media/tuners/
H A Dtda18212.c36 static const u8 bw_params[][3] = { in tda18212_set_params() local
115 ret = regmap_write(dev->regmap, 0x23, bw_params[i][2]); in tda18212_set_params()
123 ret = regmap_write(dev->regmap, 0x0f, bw_params[i][0]); in tda18212_set_params()
128 buf[1] = bw_params[i][1]; in tda18212_set_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.h81 void dcn21_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
83 void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params);
H A Ddcn20_fpu.c2182 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = in patch_bounding_box()
2189 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = in patch_bounding_box()
2200 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = in patch_bounding_box()
2246 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; in dcn21_calculate_wm() local
2248 ASSERT(bw_params); in dcn21_calculate_wm()
2291 vlevel_max = bw_params->clk_table.num_entries - 1; in dcn21_calculate_wm()
2295 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn21_calculate_wm()
2303 table_entry = &bw_params->wm_table.entries[WM_C]; in dcn21_calculate_wm()
2308 table_entry = &bw_params->wm_table.entries[WM_B]; in dcn21_calculate_wm()
2314 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn21_calculate_wm()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c2134 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn30_update_bw_bounding_box() argument
2159 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn30_update_bw_bounding_box()
2162 if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz) in dcn30_update_bw_bounding_box()
2163 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2164 if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz) in dcn30_update_bw_bounding_box()
2165 dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn30_update_bw_bounding_box()
2166 if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz) in dcn30_update_bw_bounding_box()
2167 dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn30_update_bw_bounding_box()
2168 if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz) in dcn30_update_bw_bounding_box()
2169 dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn30_update_bw_bounding_box()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.h32 void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.h29 void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.h30 void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.h36 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
H A Ddcn302_resource.c1159 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn302_update_bw_bounding_box() argument
1162 dcn302_fpu_update_bw_bounding_box(dc, bw_params); in dcn302_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.h36 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
H A Ddcn303_resource.c1108 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn303_update_bw_bounding_box() argument
1111 dcn303_fpu_update_bw_bounding_box(dc, bw_params); in dcn303_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.h30 void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
/linux/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/
H A Ddcn42_soc_and_ip_translator.c156 dc->clk_mgr->bw_params); in dcn42_update_soc_bb_with_values_from_clk_mgr()
159 if (dc->clk_mgr->bw_params->vram_type == Ddr5MemType) { in dcn42_update_soc_bb_with_values_from_clk_mgr()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c63 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
64 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
65 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn401_initialize_min_clocks()
66 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; in dcn401_initialize_min_clocks()
68 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; in dcn401_initialize_min_clocks()
81 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn401_initialize_min_clocks()
369 dc->clk_mgr && dc->clk_mgr->bw_params) { in dcn401_init_hw()
372 dc->clk_mgr->bw_params); in dcn401_init_hw()
1302 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && in dcn401_prepare_bandwidth()
1303 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn401_prepare_bandwidth()
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/linux/drivers/media/dvb-frontends/
H A Drtl2832.c411 static u8 bw_params[3][32] = { in rtl2832_set_frontend() local
477 for (j = 0; j < sizeof(bw_params[0]); j++) { in rtl2832_set_frontend()
479 0x11c + j, &bw_params[i][j], 1); in rtl2832_set_frontend()
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.h506 struct bnx2x_ets_bw_params bw_params; member
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_helpers.c1437 clk_mgr->bw_params->dc_mode_softmax_memclk : clk_mgr->bw_params->max_memclk_mhz; in dm_helpers_dp_handle_test_pattern_request()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c1397 static void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn21_update_bw_bounding_box() argument
1400 dcn21_update_bw_bounding_box_fpu(dc, bw_params); in dcn21_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c1400 static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn301_update_bw_bounding_box() argument
1403 dcn301_fpu_update_bw_bounding_box(dc, bw_params); in dcn301_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_wrapper_fpu.c436 copy_dummy_pstate_table(s->dummy_pstate_table, in_dc->clk_mgr->bw_params->dummy_pstate_table, 4); in dml2_validate_and_build_resource()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c1719 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn314_update_bw_bounding_box() argument
1722 dcn314_update_bw_bounding_box_fpu(dc, bw_params); in dcn314_update_bw_bounding_box()

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