Home
last modified time | relevance | path

Searched refs:bw_params (Results 1 – 25 of 36) sorted by relevance

12

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c497 static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn314_watermarks… in dcn314_build_watermark_ranges() argument
505 if (!bw_params->wm_table.entries[i].valid) in dcn314_build_watermark_ranges()
509 (uint8_t)bw_params->wm_table.entries[i].wm_inst; in dcn314_build_watermark_ranges()
511 (uint8_t)bw_params->wm_table.entries[i].wm_type; in dcn314_build_watermark_ranges()
522 (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); in dcn314_build_watermark_ranges()
525 (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; in dcn314_build_watermark_ranges()
568 dcn314_build_watermark_ranges(clk_mgr_base->bw_params, table); in dcn314_notify_wm_ranges()
634 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in dcn314_clk_mgr_helper_populate_bw_params() local
635 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn314_clk_mgr_helper_populate_bw_params()
677 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--) in dcn314_clk_mgr_helper_populate_bw_params()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c883 static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *… in dcn35_build_watermark_ranges() argument
891 if (!bw_params->wm_table.entries[i].valid) in dcn35_build_watermark_ranges()
895 (uint8_t)bw_params->wm_table.entries[i].wm_inst; in dcn35_build_watermark_ranges()
897 (uint8_t)bw_params->wm_table.entries[i].wm_type; in dcn35_build_watermark_ranges()
908 (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); in dcn35_build_watermark_ranges()
911 (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; in dcn35_build_watermark_ranges()
954 dcn35_build_watermark_ranges(clk_mgr_base->bw_params, table); in dcn35_notify_wm_ranges()
1043 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in dcn35_clk_mgr_helper_populate_bw_params() local
1044 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn35_clk_mgr_helper_populate_bw_params()
1105 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--) in dcn35_clk_mgr_helper_populate_bw_params()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c426 static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *… in dcn31_build_watermark_ranges() argument
434 if (!bw_params->wm_table.entries[i].valid) in dcn31_build_watermark_ranges()
438 (uint8_t)bw_params->wm_table.entries[i].wm_inst; in dcn31_build_watermark_ranges()
440 (uint8_t)bw_params->wm_table.entries[i].wm_type; in dcn31_build_watermark_ranges()
451 (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); in dcn31_build_watermark_ranges()
454 (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; in dcn31_build_watermark_ranges()
497 dcn31_build_watermark_ranges(clk_mgr_base->bw_params, table); in dcn31_notify_wm_ranges()
568 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in dcn31_clk_mgr_helper_populate_bw_params() local
591 bw_params->clk_table.num_entries = j + 1; in dcn31_clk_mgr_helper_populate_bw_params()
602 for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries; entry_idx++, j--) { in dcn31_clk_mgr_helper_populate_bw_params()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/
H A Ddcn60_clk_mgr.c129 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_socclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
133 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_memclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
137 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
141 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
145 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
152 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
156 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels > 1; in dcn60_is_ppclk_dpm_enabled()
319 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn60_build_update_display_clocks_sequence()
342 (uint16_t)clk_mgr_base->bw_params->clk_table.entries[ in dcn60_build_update_display_clocks_sequence()
343 clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels - 1].dtbclk_mhz; in dcn60_build_update_display_clocks_sequence()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.h47 void dcn31_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
48 void dcn315_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
49 void dcn316_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.h81 void dcn21_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
83 void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params);
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.h32 void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c2262 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn30_update_bw_bounding_box() argument
2287 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn30_update_bw_bounding_box()
2290 if (bw_params->clk_table.entries[i].dcfclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) in dcn30_update_bw_bounding_box()
2291 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2292 if (bw_params->clk_table.entries[i].dispclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dispclk_mhz) in dcn30_update_bw_bounding_box()
2293 dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn30_update_bw_bounding_box()
2294 if (bw_params->clk_table.entries[i].dppclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dppclk_mhz) in dcn30_update_bw_bounding_box()
2295 dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn30_update_bw_bounding_box()
2296 if (bw_params->clk_table.entries[i].phyclk_mhz > (unsigned int)dcn30_bb_max_clk.max_phyclk_mhz) in dcn30_update_bw_bounding_box()
2297 dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn30_update_bw_bounding_box()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.h29 void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.h30 void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.h36 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
H A Ddcn302_resource.c1267 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn302_update_bw_bounding_box() argument
1270 dcn302_fpu_update_bw_bounding_box(dc, bw_params); in dcn302_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.h36 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
H A Ddcn303_resource.c1216 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn303_update_bw_bounding_box() argument
1219 dcn303_fpu_update_bw_bounding_box(dc, bw_params); in dcn303_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.h30 void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn50/
H A Ddcn50_hwseq.c58 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn50_initialize_min_clocks()
59 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn50_initialize_min_clocks()
60 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn50_initialize_min_clocks()
61 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; in dcn50_initialize_min_clocks()
63 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; in dcn50_initialize_min_clocks()
73 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn50_initialize_min_clocks()
758 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); in dcn50_init_hw()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c1780 static void dcn401_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) in dcn401_update_bw_bounding_box_fpu() argument
1785 if (bw_params->num_channels > 0) { in dcn401_update_bw_bounding_box_fpu()
1787 dc, bw_params->num_channels) * in dcn401_update_bw_bounding_box_fpu()
1799 static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn401_update_bw_bounding_box() argument
1802 dcn401_update_bw_bounding_box_fpu(dc, bw_params); in dcn401_update_bw_bounding_box()
1946 …for (unsigned int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk… in dcn401_get_power_profile()
1947 if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 || in dcn401_get_power_profile()
1948 uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) in dcn401_get_power_profile()
1950 if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) in dcn401_get_power_profile()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn60/
H A Ddcn60_resource.c1820 static void dcn60_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) in dcn60_update_bw_bounding_box_fpu() argument
1822 (void)bw_params; in dcn60_update_bw_bounding_box_fpu()
1832 static void dcn60_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn60_update_bw_bounding_box() argument
1835 dcn60_update_bw_bounding_box_fpu(dc, bw_params); in dcn60_update_bw_bounding_box()
1903 …for (unsigned int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk… in dcn60_get_power_profile()
1904 if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 || in dcn60_get_power_profile()
1905 uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) in dcn60_get_power_profile()
1907 if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) in dcn60_get_power_profile()
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.h506 struct bnx2x_ets_bw_params bw_params; member
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c1261 int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000; in dcn30_prepare_bandwidth()
1265 …r->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_pa… in dcn30_prepare_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn42/
H A Ddcn42_resource.c1826 static void dcn42_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) in dcn42_update_bw_bounding_box_fpu() argument
1828 (void)bw_params; in dcn42_update_bw_bounding_box_fpu()
1835 static void dcn42_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn42_update_bw_bounding_box() argument
1838 dcn42_update_bw_bounding_box_fpu(dc, bw_params); in dcn42_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn42b/
H A Ddcn42b_resource.c1815 static void dcn42b_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) in dcn42b_update_bw_bounding_box_fpu() argument
1817 (void)bw_params; in dcn42b_update_bw_bounding_box_fpu()
1824 static void dcn42b_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn42b_update_bw_bounding_box() argument
1827 dcn42b_update_bw_bounding_box_fpu(dc, bw_params); in dcn42b_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_helpers.c1602 clk_mgr->bw_params->dc_mode_softmax_memclk : clk_mgr->bw_params->max_memclk_mhz; in dm_helpers_dp_handle_test_pattern_request()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_wrapper_fpu.c436 copy_dummy_pstate_table(s->dummy_pstate_table, in_dc->clk_mgr->bw_params->dummy_pstate_table, 4); in dml2_validate_and_build_resource()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c1856 static void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn316_update_bw_bounding_box() argument
1859 dcn316_update_bw_bounding_box_fpu(dc, bw_params); in dcn316_update_bw_bounding_box()

12