| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 194 uint16_t min_uclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()
195 uint16_t min_dcfclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
204 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = in dcn32_build_wm_range_table_fpu()
207 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = in dcn32_build_wm_range_table_fpu()
208 (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
210 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) in dcn32_build_wm_range_table_fpu()
211 setb_min_uclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; in dcn32_build_wm_range_table_fpu()
214 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn32_build_wm_range_table_fpu()
215 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn32_build_wm_range_table_fpu()
216 clk_mgr->base.bw_params in dcn32_build_wm_range_table_fpu()
2633 dcn32_patch_dpm_table(struct clk_bw_params * bw_params) dcn32_patch_dpm_table() argument
2765 build_synthetic_soc_states(bool disable_dc_mode_overwrite,struct clk_bw_params * bw_params,struct _vcs_dpi_voltage_scaling_st * table,unsigned int * num_entries) build_synthetic_soc_states() argument
3014 dcn32_update_bw_bounding_box_fpu(struct dc * dc,struct clk_bw_params * bw_params) dcn32_update_bw_bounding_box_fpu() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/ |
| H A D | dcn42_clk_mgr.c | 641 void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_watermarks *table) in dcn42_build_watermark_ranges()
649 if (!bw_params->wm_table.entries[i].valid) in dcn42_build_watermark_ranges()
653 (uint8_t)bw_params->wm_table.entries[i].wm_inst; in dcn42_build_watermark_ranges()
655 (uint8_t)bw_params->wm_table.entries[i].wm_type; in dcn42_build_watermark_ranges()
666 (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); in dcn42_build_watermark_ranges()
669 (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; in dcn42_build_watermark_ranges()
709 if (clk_mgr_base->bw_params->wm_table.entries[WM_A].valid == true) in dcn42_notify_wm_ranges()
727 clk_mgr_base->bw_params->wm_table.entries[i].wm_inst = i; in dcn42_notify_wm_ranges()
729 if (i >= clk_mgr_base->bw_params->clk_table.num_entries) { in dcn42_notify_wm_ranges()
730 clk_mgr_base->bw_params in dcn42_notify_wm_ranges()
635 dcn42_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn42_watermarks * table) dcn42_build_watermark_ranges() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
459 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; in dcn31_update_soc_for_wm_a()
460 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; in dcn31_update_soc_for_wm_a()
461 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; in dcn31_update_soc_for_wm_a()
469 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn315_update_soc_for_wm_a()
474 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; in dcn315_update_soc_for_wm_a()
476 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; in dcn315_update_soc_for_wm_a()
478 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; in dcn315_update_soc_for_wm_a()
593 void dcn31_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) in dcn31_update_bw_bounding_box_fpu()
596 struct clk_limit_table *clk_table = &bw_params in dcn31_update_bw_bounding_box_fpu()
590 dcn31_update_bw_bounding_box_fpu(struct dc * dc,struct clk_bw_params * bw_params) dcn31_update_bw_bounding_box_fpu() argument
668 dcn315_update_bw_bounding_box_fpu(struct dc * dc,struct clk_bw_params * bw_params) dcn315_update_bw_bounding_box_fpu() argument
729 dcn316_update_bw_bounding_box_fpu(struct dc * dc,struct clk_bw_params * bw_params) dcn316_update_bw_bounding_box_fpu() argument
[all...] |
| H A D | dcn31_fpu.h | 47 void dcn31_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
48 void dcn315_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
49 void dcn316_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
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| /linux/drivers/media/tuners/ |
| H A D | tda18212.c | 36 static const u8 bw_params[][3] = { in tda18212_set_params() local
115 ret = regmap_write(dev->regmap, 0x23, bw_params[i][2]); in tda18212_set_params()
123 ret = regmap_write(dev->regmap, 0x0f, bw_params[i][0]); in tda18212_set_params()
128 buf[1] = bw_params[i][1]; in tda18212_set_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.h | 81 void dcn21_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
83 void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params);
|
| H A D | dcn20_fpu.c | 2192 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = in patch_bounding_box()
2199 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = in patch_bounding_box()
2210 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = in calculate_wm_set_for_vlevel()
2257 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; in dcn21_calculate_wm()
2259 ASSERT(bw_params); in dcn21_calculate_wm()
2302 vlevel_max = bw_params->clk_table.num_entries - 1; in dcn21_calculate_wm()
2306 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn21_calculate_wm()
2314 table_entry = &bw_params->wm_table.entries[WM_C]; in dcn21_calculate_wm()
2319 table_entry = &bw_params in dcn21_calculate_wm()
2246 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; dcn21_calculate_wm() local
2402 dcn21_update_bw_bounding_box_fpu(struct dc * dc,struct clk_bw_params * bw_params) dcn21_update_bw_bounding_box_fpu() argument
2465 dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params * bw_params) dcn21_clk_mgr_set_bw_params_wm_table() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 2260 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn30_update_bw_bounding_box()
2285 if (bw_params->clk_table.entries[0].memclk_mhz) {
2288 if (bw_params->clk_table.entries[i].dcfclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz)
2289 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2290 if (bw_params->clk_table.entries[i].dispclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dispclk_mhz)
2291 dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2292 if (bw_params->clk_table.entries[i].dppclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dppclk_mhz)
2293 dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2294 if (bw_params->clk_table.entries[i].phyclk_mhz > (unsigned int)dcn30_bb_max_clk.max_phyclk_mhz)
2295 dcn30_bb_max_clk.max_phyclk_mhz = bw_params
2134 dcn30_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params) dcn30_update_bw_bounding_box() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.h | 32 void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.h | 29 void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.h | 30 void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.h | 36 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
|
| H A D | dcn302_resource.c | 1265 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn302_resource_construct()
1268 dcn302_fpu_update_bw_bounding_box(dc, bw_params); in dcn302_resource_construct()
1159 dcn302_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params) dcn302_update_bw_bounding_box() argument
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.h | 36 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
|
| H A D | dcn303_resource.c | 1214 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn303_resource_construct()
1217 dcn303_fpu_update_bw_bounding_box(dc, bw_params); in dcn303_resource_construct()
1108 dcn303_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params) dcn303_update_bw_bounding_box() argument
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.h | 30 void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
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| /linux/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/ |
| H A D | dcn42_soc_and_ip_translator.c | 160 dc->clk_mgr->bw_params); in dcn42_update_soc_bb_with_values_from_clk_mgr()
163 if (dc->clk_mgr->bw_params->vram_type == Ddr5MemType) {
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 64 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
65 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
66 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn401_initialize_min_clocks()
67 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; in dcn401_initialize_min_clocks()
69 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; in dcn401_initialize_min_clocks()
82 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn401_initialize_min_clocks()
400 dc->clk_mgr && dc->clk_mgr->bw_params) { in dcn401_set_mcm_luts()
403 dc->clk_mgr->bw_params); in dcn401_set_mcm_luts()
1459 int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000; in update_dsc_for_odm_change()
1463 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params in update_dsc_for_odm_change()
[all...] |
| /linux/drivers/media/dvb-frontends/ |
| H A D | rtl2832.c | 411 static u8 bw_params[3][32] = { in rtl2832_set_frontend() local
477 for (j = 0; j < sizeof(bw_params[0]); j++) { in rtl2832_set_frontend()
479 0x11c + j, &bw_params[i][j], 1); in rtl2832_set_frontend()
|
| /linux/drivers/net/ethernet/broadcom/bnx2x/ |
| H A D | bnx2x_link.h | 506 struct bnx2x_ets_bw_params bw_params; member
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_helpers.c | 1505 clk_mgr->bw_params->dc_mode_softmax_memclk : clk_mgr->bw_params->max_memclk_mhz; in dm_get_adaptive_sync_support_type()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 1398 static void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn21_update_bw_bounding_box()
1401 dcn21_update_bw_bounding_box_fpu(dc, bw_params); in dcn21_update_bw_bounding_box()
1397 dcn21_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params) dcn21_update_bw_bounding_box() argument
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| H A D | dcn301_resource.c | 1401 static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn301_update_bw_bounding_box()
1404 dcn301_fpu_update_bw_bounding_box(dc, bw_params); in dcn301_update_bw_bounding_box()
1400 dcn301_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params) dcn301_update_bw_bounding_box() argument
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_wrapper_fpu.c | 436 copy_dummy_pstate_table(s->dummy_pstate_table, in_dc->clk_mgr->bw_params->dummy_pstate_table, 4); in dml2_validate_and_build_resource()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1844 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn30_clock_source_create()
1847 dcn314_update_bw_bounding_box_fpu(dc, bw_params); in dcn314_resource_construct()
1719 dcn314_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params) dcn314_update_bw_bounding_box() argument
|