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Searched refs:apbc (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/clk/mmp/
H A Dclk-apbc.c34 struct clk_apbc *apbc = to_clk_apbc(hw); in clk_apbc_prepare() local
42 if (apbc->lock) in clk_apbc_prepare()
43 spin_lock_irqsave(apbc->lock, flags); in clk_apbc_prepare()
45 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
46 if (apbc->flags & APBC_POWER_CTRL) in clk_apbc_prepare()
49 writel_relaxed(data, apbc->base); in clk_apbc_prepare()
51 if (apbc->lock) in clk_apbc_prepare()
52 spin_unlock_irqrestore(apbc->lock, flags); in clk_apbc_prepare()
54 udelay(apbc->delay); in clk_apbc_prepare()
56 if (apbc->lock) in clk_apbc_prepare()
[all …]
H A DMakefile6 obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
14 obj-$(CONFIG_COMMON_CLK_PXA1908) += clk-pxa1908-apbc.o clk-pxa1908-apbcp.o \
/linux/arch/arm64/boot/dts/marvell/mmp/
H A Dpxa1908.dtsi134 clocks = <&apbc PXA1908_CLK_TWSI1>;
145 clocks = <&apbc PXA1908_CLK_TWSI0>;
156 clocks = <&apbc PXA1908_CLK_TWSI3>;
161 apbc: clock-controller@15000 { label
162 compatible = "marvell,pxa1908-apbc";
171 clocks = <&apbc PXA1908_CLK_UART0>;
179 clocks = <&apbc PXA1908_CLK_UART1>;
190 clocks = <&apbc PXA1908_CLK_GPIO>;
217 clocks = <&apbc PXA1908_CLK_PWM0>;
225 clocks = <&apbc PXA1908_CLK_PWM1>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dmarvell,pxa910.txt13 "mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined.
H A Dmarvell,pxa168.txt13 "mpmu", "apmu", "apbc". So three reg spaces need to be defined.
H A Dmarvell,pxa1928.txt12 - "marvell,pxa1928-apbc" - APBC controller compatible
/linux/arch/arm/boot/dts/marvell/
H A Dpxa910.dtsi172 reg-names = "mpmu", "apmu", "apbc", "apbcp";
H A Dpxa168.dtsi161 reg-names = "mpmu", "apmu", "apbc";
H A Dmmp2.dtsi510 reg-names = "mpmu", "apmu", "apbc";
H A Dmmp3.dtsi575 reg-names = "mpmu", "apmu", "apbc";
/linux/arch/riscv/boot/dts/spacemit/
H A Dk1.dtsi427 compatible = "spacemit,k1-syscon-apbc";