1*ab08aefcSChao Xie* Marvell PXA168 Clock Controller 2*ab08aefcSChao Xie 3*ab08aefcSChao XieThe PXA168 clock subsystem generates and supplies clock to various 4*ab08aefcSChao Xiecontrollers within the PXA168 SoC. 5*ab08aefcSChao Xie 6*ab08aefcSChao XieRequired Properties: 7*ab08aefcSChao Xie 8*ab08aefcSChao Xie- compatible: should be one of the following. 9*ab08aefcSChao Xie - "marvell,pxa168-clock" - controller compatible with PXA168 SoC. 10*ab08aefcSChao Xie 11*ab08aefcSChao Xie- reg: physical base address of the clock subsystem and length of memory mapped 12*ab08aefcSChao Xie region. There are 3 places in SOC has clock control logic: 13*ab08aefcSChao Xie "mpmu", "apmu", "apbc". So three reg spaces need to be defined. 14*ab08aefcSChao Xie 15*ab08aefcSChao Xie- #clock-cells: should be 1. 16*ab08aefcSChao Xie- #reset-cells: should be 1. 17*ab08aefcSChao Xie 18*ab08aefcSChao XieEach clock is assigned an identifier and client nodes use this identifier 19*ab08aefcSChao Xieto specify the clock which they consume. 20*ab08aefcSChao Xie 21*ab08aefcSChao XieAll these identifier could be found in <dt-bindings/clock/marvell,pxa168.h>. 22