1*8a3d9c16SRob Herring* Marvell PXA1928 Clock Controllers 2*8a3d9c16SRob Herring 3*8a3d9c16SRob HerringThe PXA1928 clock subsystem generates and supplies clock to various 4*8a3d9c16SRob Herringcontrollers within the PXA1928 SoC. The PXA1928 contains 3 clock controller 5*8a3d9c16SRob Herringblocks called APMU, MPMU, and APBC roughly corresponding to internal buses. 6*8a3d9c16SRob Herring 7*8a3d9c16SRob HerringRequired Properties: 8*8a3d9c16SRob Herring 9*8a3d9c16SRob Herring- compatible: should be one of the following. 10*8a3d9c16SRob Herring - "marvell,pxa1928-apmu" - APMU controller compatible 11*8a3d9c16SRob Herring - "marvell,pxa1928-mpmu" - MPMU controller compatible 12*8a3d9c16SRob Herring - "marvell,pxa1928-apbc" - APBC controller compatible 13*8a3d9c16SRob Herring- reg: physical base address of the clock controller and length of memory mapped 14*8a3d9c16SRob Herring region. 15*8a3d9c16SRob Herring- #clock-cells: should be 1. 16*8a3d9c16SRob Herring- #reset-cells: should be 1. 17*8a3d9c16SRob Herring 18*8a3d9c16SRob HerringEach clock is assigned an identifier and client nodes use the clock controller 19*8a3d9c16SRob Herringphandle and this identifier to specify the clock which they consume. 20*8a3d9c16SRob Herring 21*8a3d9c16SRob HerringAll these identifiers can be found in <dt-bindings/clock/marvell,pxa1928.h>. 22