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Searched refs:amdgpu_ip_version (Results 1 – 25 of 71) sorted by relevance

123

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dhdp_v4_0.c42 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0) || in hdp_v4_0_invalidate_hdp()
43 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) || in hdp_v4_0_invalidate_hdp()
44 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 5)) in hdp_v4_0_invalidate_hdp()
76 if (amdgpu_ip_version(adev, HDP_HWIP, 0) >= IP_VERSION(4, 4, 0)) in hdp_v4_0_reset_ras_error_count()
88 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 0, 0) || in hdp_v4_0_update_clock_gating()
89 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 0, 1) || in hdp_v4_0_update_clock_gating()
90 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 1, 1) || in hdp_v4_0_update_clock_gating()
91 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 1, 0)) { in hdp_v4_0_update_clock_gating()
125 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) || in hdp_v4_0_get_clockgating_state()
126 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 5)) { in hdp_v4_0_get_clockgating_state()
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H A Dnbif_v6_3_1.c99 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) { in nbif_v6_3_1_remap_hdp_registers()
116 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) in nbif_v6_3_1_get_rev_id()
118 else if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) in nbif_v6_3_1_get_rev_id()
131 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) { in nbif_v6_3_1_mc_access_enable()
160 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) in nbif_v6_3_1_sdma_doorbell_range()
194 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) in nbif_v6_3_1_sdma_doorbell_range()
208 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) in nbif_v6_3_1_vcn_doorbell_range()
242 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) in nbif_v6_3_1_vcn_doorbell_range()
291 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4) || in nbif_v6_3_1_vpe_doorbell_range()
292 amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) { in nbif_v6_3_1_vpe_doorbell_range()
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H A Dathub_v4_1_0.c34 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v4_1_0_get_cg_cntl()
47 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v4_1_0_set_cg_cntl()
96 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v4_1_0_set_clockgating()
H A Damdgpu_discovery.c503 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && in amdgpu_discovery_harvest_config_quirk()
504 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { in amdgpu_discovery_harvest_config_quirk()
1202 if (!amdgpu_ip_version(adev, VCE_HWIP, 0)) in amdgpu_discovery_get_harvest_info()
1955 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && in amdgpu_discovery_harvest_ip()
2331 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_discovery_set_common_ip_blocks()
2385 amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_discovery_set_common_ip_blocks()
2394 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_discovery_set_gmc_ip_blocks()
2445 amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_discovery_set_gmc_ip_blocks()
2453 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { in amdgpu_discovery_set_ih_ip_blocks()
2493 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); in amdgpu_discovery_set_ih_ip_blocks()
[all …]
H A Dhdp_v6_0.c44 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0)) in hdp_v6_0_update_clock_gating()
54 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0)) in hdp_v6_0_update_clock_gating()
119 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0)) in hdp_v6_0_update_clock_gating()
H A Dpsp_v15_0.c87 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 5)) { in psp_v15_0_0_ring_stop()
145 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 5)) { in psp_v15_0_0_ring_create()
235 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 5)) in psp_v15_0_0_ring_get_wptr()
253 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 5)) in psp_v15_0_0_ring_set_wptr()
H A Dvpe_v6_1.c135 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v6_1_load_microcode()
142 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v6_1_load_microcode()
283 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v_6_1_ring_stop()
290 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) { in vpe_v_6_1_ring_stop()
317 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v6_1_set_trap_irq_state()
325 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v6_1_set_trap_irq_state()
361 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v6_1_set_regs()
H A Dumsch_mm_v4_0.c64 if (amdgpu_ip_version(adev, VCN_HWIP, 0) >= IP_VERSION(4, 0, 5)) { in umsch_mm_v4_0_load_microcode()
258 if (amdgpu_ip_version(adev, VCN_HWIP, 0) >= IP_VERSION(4, 0, 5)) { in umsch_mm_v4_0_ring_stop()
298 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, MMHUB_HWIP, 0)); in umsch_mm_v4_0_set_hw_resources()
303 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); in umsch_mm_v4_0_set_hw_resources()
306 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCN_HWIP, 0)); in umsch_mm_v4_0_set_hw_resources()
308 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0)); in umsch_mm_v4_0_set_hw_resources()
H A Dmmhub_v2_0.c508 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_init_client_info()
583 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_update_medium_grain_clock_gating()
616 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_update_medium_grain_clock_gating()
640 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_update_medium_grain_light_sleep()
666 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_set_clockgating()
691 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_get_clockgating()
H A Dsoc24.c80 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in soc24_query_video_codecs()
186 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc24_asic_reset_method()
348 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc24_common_early_init()
532 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in soc24_common_set_clockgating_state()
552 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { in soc24_common_set_powergating_state()
H A Damdgpu_psp.c117 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_check_pmfw_centralized_cstate_management()
145 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_init_sriov_microcode()
187 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_early_init()
405 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || in psp_get_runtime_db_entry()
406 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || in psp_get_runtime_db_entry()
407 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || in psp_get_runtime_db_entry()
408 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) in psp_get_runtime_db_entry()
487 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); in psp_sw_init()
716 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && in psp_err_warn()
933 u32 ip_version = amdgpu_ip_version(psp->adev, MP0_HWIP, 0); in psp_skip_tmr()
[all …]
H A Damdgpu_mes.c220 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) { in amdgpu_mes_init()
330 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) && in amdgpu_mes_suspend()
783 } else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && in amdgpu_mes_init_microcode()
784 amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0)) { in amdgpu_mes_init_microcode()
868 return ((amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && in amdgpu_mes_suspend_resume_all_supported()
869 amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0) && in amdgpu_mes_suspend_resume_all_supported()
871 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)); in amdgpu_mes_suspend_resume_all_supported()
876 u32 ip_maj = IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_mes_queue_reset_by_mes_supported()
877 u32 ip_min = IP_VERSION_MIN(amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_mes_queue_reset_by_mes_supported()
H A Dgmc_v11_0.c554 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { in gmc_v11_0_set_umc_funcs()
577 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v11_0_set_mmhub_funcs()
599 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v11_0_set_gfxhub_funcs()
663 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 5, 0)) && in gmc_v11_0_vram_gtt_location()
762 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v11_0_sw_init()
770 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v11_0_sw_init()
H A Dgfx_v9_0.c1098 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_init_golden_registers()
1154 if ((amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 1)) && in gfx_v9_0_init_golden_registers()
1155 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 2))) in gfx_v9_0_init_golden_registers()
1298 if ((amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 1)) && in gfx_v9_0_check_fw_write_wait()
1299 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 2)) && in gfx_v9_0_check_fw_write_wait()
1307 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_check_fw_write_wait()
1411 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 3, 0)) && in check_if_enlarge_doorbell_range()
1424 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_check_if_need_gfxoff()
1541 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || in gfx_v9_0_load_mec2_fw_bin_support()
1542 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || in gfx_v9_0_load_mec2_fw_bin_support()
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H A Dathub_v2_1.c73 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v2_1_set_clockgating()
H A Dathub_v2_0.c80 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v2_0_set_clockgating()
H A Dathub_v1_0.c71 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v1_0_set_clockgating()
H A Dsoc21.c176 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in soc21_query_video_codecs()
398 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc21_asic_reset_method()
571 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc21_common_early_init()
1055 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in soc21_common_set_clockgating_state()
1083 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { in soc21_common_set_powergating_state()
H A Damdgpu_vm.h123 …((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_P…
138 …((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGP…
142 …((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_P…
H A Damdgpu_device.c968 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || in amdgpu_device_asic_init()
969 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || in amdgpu_device_asic_init()
970 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0) || in amdgpu_device_asic_init()
971 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) { in amdgpu_device_asic_init()
1275 return amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0); in amdgpu_device_seamless_boot_supported()
2065 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && in amdgpu_device_ip_early_init()
2093 amdgpu_ip_version((adev), GC_HWIP, 0) == IP_VERSION(9, 4, 4); in amdgpu_device_ip_early_init()
2858 if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(9, 0, 0)) in amdgpu_device_smu_fini_early()
2921 amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 0, 0)) { in amdgpu_device_ip_fini_early()
3124 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 0, 0)) in amdgpu_device_ip_suspend_phase2()
[all …]
H A Dgfx_v10_0.c3894 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_init_spm_golden_registers()
3920 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_init_golden_registers()
4144 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_check_fw_write_wait()
4195 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_check_gfxoff_flag()
4217 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) && in gfx_v10_0_init_microcode()
4370 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_init_rlcg_reg_access_ctrl()
4585 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_gpu_early_init()
4624 amdgpu_ip_version(adev, GC_HWIP, 0)); in gfx_v10_0_gpu_early_init()
4763 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_sw_init()
4800 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_sw_init()
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dyellow_carp_ppt.c1020 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1022 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1023 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
1027 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1029 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1030 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
1034 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1036 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1037 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c486 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4)) in amdgpu_dm_init()
507 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { in amdgpu_dm_init()
539 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(2, 0, 3)) in amdgpu_dm_init()
596 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0)) in amdgpu_dm_init()
600 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) in amdgpu_dm_init()
604 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 2, 0)) { in amdgpu_dm_init()
826 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 0, 1)) in amdgpu_dm_init()
997 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { in load_dmcu_fw()
1181 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 6, 0))) in dm_late_init()
1421 amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { in dm_gpureset_toggle_interrupts()
[all …]
H A Damdgpu_dm_crtc.c298 if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) { in amdgpu_dm_crtc_set_vblank()
328 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { in amdgpu_dm_crtc_set_vblank()
363 if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) { in amdgpu_dm_crtc_set_vblank()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0_0_ppt.c877 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(15, 0, 5)) in smu_v15_0_common_get_dpm_freq_by_index()
1137 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(15, 0, 5)) in smu_v15_0_common_get_dpm_ultimate_freq()
1240 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(15, 0, 5)) in smu_v15_0_common_get_dpm_level_count()
1429 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(15, 0, 0) || in smu_v15_0_common_get_dpm_profile_freq()
1430 amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(15, 0, 9)) in smu_v15_0_common_get_dpm_profile_freq()
1629 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(15, 0, 5)) in smu_v15_0_common_set_fine_grain_gfx_freq_parameters()
1698 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(15, 0, 5)) in smu_v15_0_common_get_dpm_table()

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