1*53edf771SHawking Zhang /*
2*53edf771SHawking Zhang * Copyright 2023 Advanced Micro Devices, Inc.
3*53edf771SHawking Zhang *
4*53edf771SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a
5*53edf771SHawking Zhang * copy of this software and associated documentation files (the "Software"),
6*53edf771SHawking Zhang * to deal in the Software without restriction, including without limitation
7*53edf771SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*53edf771SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the
9*53edf771SHawking Zhang * Software is furnished to do so, subject to the following conditions:
10*53edf771SHawking Zhang *
11*53edf771SHawking Zhang * The above copyright notice and this permission notice shall be included in
12*53edf771SHawking Zhang * all copies or substantial portions of the Software.
13*53edf771SHawking Zhang *
14*53edf771SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*53edf771SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*53edf771SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*53edf771SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*53edf771SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*53edf771SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*53edf771SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE.
21*53edf771SHawking Zhang *
22*53edf771SHawking Zhang */
23*53edf771SHawking Zhang
24*53edf771SHawking Zhang #include "amdgpu.h"
25*53edf771SHawking Zhang #include "athub_v4_1_0.h"
26*53edf771SHawking Zhang #include "athub/athub_4_1_0_offset.h"
27*53edf771SHawking Zhang #include "athub/athub_4_1_0_sh_mask.h"
28*53edf771SHawking Zhang #include "soc15_common.h"
29*53edf771SHawking Zhang
athub_v4_1_0_get_cg_cntl(struct amdgpu_device * adev)30*53edf771SHawking Zhang static uint32_t athub_v4_1_0_get_cg_cntl(struct amdgpu_device *adev)
31*53edf771SHawking Zhang {
32*53edf771SHawking Zhang uint32_t data;
33*53edf771SHawking Zhang
34*53edf771SHawking Zhang switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) {
35*53edf771SHawking Zhang case IP_VERSION(4, 1, 0):
36*53edf771SHawking Zhang data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);
37*53edf771SHawking Zhang break;
38*53edf771SHawking Zhang default:
39*53edf771SHawking Zhang data = 0;
40*53edf771SHawking Zhang break;
41*53edf771SHawking Zhang }
42*53edf771SHawking Zhang return data;
43*53edf771SHawking Zhang }
44*53edf771SHawking Zhang
athub_v4_1_0_set_cg_cntl(struct amdgpu_device * adev,uint32_t data)45*53edf771SHawking Zhang static void athub_v4_1_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data)
46*53edf771SHawking Zhang {
47*53edf771SHawking Zhang switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) {
48*53edf771SHawking Zhang case IP_VERSION(4, 1, 0):
49*53edf771SHawking Zhang WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data);
50*53edf771SHawking Zhang break;
51*53edf771SHawking Zhang default:
52*53edf771SHawking Zhang break;
53*53edf771SHawking Zhang }
54*53edf771SHawking Zhang }
55*53edf771SHawking Zhang
56*53edf771SHawking Zhang static void
athub_v4_1_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)57*53edf771SHawking Zhang athub_v4_1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
58*53edf771SHawking Zhang bool enable)
59*53edf771SHawking Zhang {
60*53edf771SHawking Zhang uint32_t def, data;
61*53edf771SHawking Zhang
62*53edf771SHawking Zhang def = data = athub_v4_1_0_get_cg_cntl(adev);
63*53edf771SHawking Zhang
64*53edf771SHawking Zhang if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_MGCG))
65*53edf771SHawking Zhang data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
66*53edf771SHawking Zhang else
67*53edf771SHawking Zhang data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
68*53edf771SHawking Zhang
69*53edf771SHawking Zhang if (def != data)
70*53edf771SHawking Zhang athub_v4_1_0_set_cg_cntl(adev, data);
71*53edf771SHawking Zhang }
72*53edf771SHawking Zhang
73*53edf771SHawking Zhang static void
athub_v4_1_0_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)74*53edf771SHawking Zhang athub_v4_1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
75*53edf771SHawking Zhang bool enable)
76*53edf771SHawking Zhang {
77*53edf771SHawking Zhang uint32_t def, data;
78*53edf771SHawking Zhang
79*53edf771SHawking Zhang def = data = athub_v4_1_0_get_cg_cntl(adev);
80*53edf771SHawking Zhang
81*53edf771SHawking Zhang if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_LS))
82*53edf771SHawking Zhang data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
83*53edf771SHawking Zhang else
84*53edf771SHawking Zhang data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
85*53edf771SHawking Zhang
86*53edf771SHawking Zhang if (def != data)
87*53edf771SHawking Zhang athub_v4_1_0_set_cg_cntl(adev, data);
88*53edf771SHawking Zhang }
89*53edf771SHawking Zhang
athub_v4_1_0_set_clockgating(struct amdgpu_device * adev,enum amd_clockgating_state state)90*53edf771SHawking Zhang int athub_v4_1_0_set_clockgating(struct amdgpu_device *adev,
91*53edf771SHawking Zhang enum amd_clockgating_state state)
92*53edf771SHawking Zhang {
93*53edf771SHawking Zhang if (amdgpu_sriov_vf(adev))
94*53edf771SHawking Zhang return 0;
95*53edf771SHawking Zhang
96*53edf771SHawking Zhang switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) {
97*53edf771SHawking Zhang case IP_VERSION(4, 1, 0):
98*53edf771SHawking Zhang athub_v4_1_0_update_medium_grain_clock_gating(adev,
99*53edf771SHawking Zhang state == AMD_CG_STATE_GATE);
100*53edf771SHawking Zhang athub_v4_1_0_update_medium_grain_light_sleep(adev,
101*53edf771SHawking Zhang state == AMD_CG_STATE_GATE);
102*53edf771SHawking Zhang break;
103*53edf771SHawking Zhang default:
104*53edf771SHawking Zhang break;
105*53edf771SHawking Zhang }
106*53edf771SHawking Zhang
107*53edf771SHawking Zhang return 0;
108*53edf771SHawking Zhang }
109*53edf771SHawking Zhang
athub_v4_1_0_get_clockgating(struct amdgpu_device * adev,u64 * flags)110*53edf771SHawking Zhang void athub_v4_1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
111*53edf771SHawking Zhang {
112*53edf771SHawking Zhang int data;
113*53edf771SHawking Zhang
114*53edf771SHawking Zhang /* AMD_CG_SUPPORT_ATHUB_MGCG */
115*53edf771SHawking Zhang data = athub_v4_1_0_get_cg_cntl(adev);
116*53edf771SHawking Zhang if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
117*53edf771SHawking Zhang *flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
118*53edf771SHawking Zhang
119*53edf771SHawking Zhang /* AMD_CG_SUPPORT_ATHUB_LS */
120*53edf771SHawking Zhang if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
121*53edf771SHawking Zhang *flags |= AMD_CG_SUPPORT_ATHUB_LS;
122*53edf771SHawking Zhang }
123