| /linux/arch/loongarch/lib/ |
| H A D | xor_simd.c | 23 #define XOR(dj, k) "vxor.v $vr" #dj ", $vr" #dj ", $vr" #k "\n\t" macro 36 XOR(0, 4) \ 37 XOR(1, 5) \ 38 XOR(2, 6) \ 39 XOR(3, 7) 52 #undef XOR 66 #define XOR(dj, k) "xvxor.v $xr" #dj ", $xr" #dj ", $xr" #k "\n\t" macro 75 XOR(0, 2) \ 76 XOR(1, 3) 87 #undef XOR
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| /linux/arch/powerpc/lib/ |
| H A D | xor_vmx.c | 44 #define XOR(V1, V2) \ macro 63 XOR(v1, v2); in __xor_altivec_2() 85 XOR(v1, v2); in __xor_altivec_3() 86 XOR(v1, v3); in __xor_altivec_3() 112 XOR(v1, v2); in __xor_altivec_4() 113 XOR(v3, v4); in __xor_altivec_4() 114 XOR(v1, v3); in __xor_altivec_4() 144 XOR(v1, v2); in __xor_altivec_5() 145 XOR(v3, v4); in __xor_altivec_5() 146 XOR(v1, v5); in __xor_altivec_5() [all …]
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| /linux/lib/raid6/ |
| H A D | s390vx.uc | 42 #define XOR(x, y, z) fpu_vx(x, y, z) 58 p = dptr[z0 + 1]; /* XOR parity */ 68 XOR(8+$$,8+$$,16+$$); 70 XOR(0+$$,0+$$,16+$$); 71 XOR(8+$$,8+$$,16+$$); 88 p = dptr[disks - 2]; /* XOR parity */ 102 XOR(8+$$,8+$$,16+$$); 104 XOR(0+$$,0+$$,16+$$); 105 XOR(8+$$,8+$$,16+$$); 112 XOR( [all...] |
| H A D | altivec.uc | 81 p = dptr[z0+1]; /* XOR parity */ 126 NULL, /* XOR not yet implemented */
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| H A D | int.uc | 84 p = dptr[z0+1]; /* XOR parity */ 113 p = dptr[disks-2]; /* XOR parity */
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| H A D | neon.uc | 67 p = dptr[z0+1]; /* XOR parity */ 98 p = dptr[disks-2]; /* XOR parity */
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| H A D | vpermxor.uc | 52 p = dptr[z0+1]; /* XOR parity */
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| /linux/Documentation/devicetree/bindings/powerpc/4xx/ |
| H A D | ppc440spe-adma.txt | 1 PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator) 4 are specified hereby. These are I2O/DMA, DMA and XOR nodes 60 iii) XOR Accelerator node 66 - interrupts : <interrupt mapping for XOR interrupt source>
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| /linux/arch/arm64/crypto/ |
| H A D | Kconfig | 85 - XTS (XOR Encrypt XOR with ciphertext stealing) mode (NIST SP800-38E 102 - XTS (XOR Encrypt XOR with ciphertext stealing) mode (NIST SP800-38E 121 - XTS (XOR Encrypt XOR with ciphertext stealing) mode (NIST SP800-38E 151 - XTS (XOR Encrypt XOR with ciphertext stealing) mode (NIST SP800-38E
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| /linux/arch/parisc/math-emu/ |
| H A D | dbl_float.h | 409 result = Dallp1(left) XOR Dallp1(right) 412 Dallp1(result) = left XOR Dallp1(right) 415 Dallp2(left) = Dallp2(left) XOR Dallp2(right); \ 416 Dallp2(right) = Dallp2(left) XOR Dallp2(right); \ 417 Dallp2(left) = Dallp2(left) XOR Dallp2(right) 546 Dextallp2(leftp2) = Dextallp2(leftp2) XOR Dextallp2(rightp2); \ 547 Dextallp2(rightp2) = Dextallp2(leftp2) XOR Dextallp2(rightp2); \ 548 Dextallp2(leftp2) = Dextallp2(leftp2) XOR Dextallp2(rightp2); \ 549 Dextallp3(leftp3) = Dextallp3(leftp3) XOR Dextallp3(rightp3); \ 550 Dextallp3(rightp3) = Dextallp3(leftp3) XOR Dextallp3(rightp3); \ [all …]
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| H A D | sgl_float.h | 236 result = Sall(left) XOR Sall(right); 239 Sall(result) = left XOR Sall(right) 328 Sextallp2(leftp2) = Sextallp2(leftp2) XOR Sextallp2(rightp2); \ 329 Sextallp2(rightp2) = Sextallp2(leftp2) XOR Sextallp2(rightp2); \ 330 Sextallp2(leftp2) = Sextallp2(leftp2) XOR Sextallp2(rightp2)
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| /linux/arch/arm/crypto/ |
| H A D | Kconfig | 66 - XTS (XOR Encrypt XOR with ciphertext stealing) mode (NIST SP800-38E 94 - XTS (XOR Encrypt XOR with ciphertext stealing) mode (NIST SP800-38E
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| /linux/scripts/atomic/kerneldoc/ |
| H A D | xor | 3 * ${class}${atomicname}() - atomic bitwise XOR with ${desc_order} ordering
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| /linux/drivers/crypto/caam/ |
| H A D | desc_constr.h | 429 APPEND_MATH(XOR, desc, dest, src0, src1, len) 457 APPEND_MATH_IMM_u32(XOR, desc, dest, src0, src1, data) 488 APPEND_MATH_IMM_u64(XOR, desc, dest, src0, src1, data)
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| /linux/arch/sparc/net/ |
| H A D | bpf_jit_comp_32.c | 77 #define XOR F3(2, 0x03) macro 425 emit_alu_X(XOR); in bpf_jit_compile() 428 emit_alu_K(XOR, K); in bpf_jit_compile()
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| H A D | bpf_jit_comp_64.c | 145 #define XOR F3(2, 0x03) macro 284 emit(XOR | IMMED | RS1(reg) | S13(lbits) | RD(reg), ctx); in emit_set_const_sext() 575 emit(XOR | IMMED | RS1(dest) | S13(low_bits) | RD(dest), ctx); in emit_loadimm64() 936 emit_alu(XOR, src, dst, ctx); in build_insn() 1091 emit_alu_K(XOR, dst, imm, ctx); in build_insn()
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| /linux/Documentation/staging/ |
| H A D | crc32.rst | 39 and to make the XOR cancel, it's just a copy of bit 32 of the remainder. 109 If the input is a multiple of 32 bits, you can even XOR in a 32-bit 160 final CRC is simply the XOR of the 4 table look-ups.
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| /linux/tools/arch/x86/lib/ |
| H A D | x86-opcode-map.txt | 102 30: XOR Eb,Gb 103 31: XOR Ev,Gv 104 32: XOR Gb,Eb 105 33: XOR Gv,Ev 106 34: XOR AL,Ib 107 35: XOR rAX,Iz 967 30: XOR Eb,Gb (ev) 968 31: XOR Ev,Gv (es) | XOR Ev,Gv (66),(es) 969 32: XOR Gb,Eb (ev) 970 33: XOR Gv,Ev (es) | XOR Gv,Ev (66),(es) [all …]
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| /linux/arch/x86/lib/ |
| H A D | x86-opcode-map.txt | 102 30: XOR Eb,Gb 103 31: XOR Ev,Gv 104 32: XOR Gb,Eb 105 33: XOR Gv,Ev 106 34: XOR AL,Ib 107 35: XOR rAX,Iz 967 30: XOR Eb,Gb (ev) 968 31: XOR Ev,Gv (es) | XOR Ev,Gv (66),(es) 969 32: XOR Gb,Eb (ev) 970 33: XOR Gv,Ev (es) | XOR Gv,Ev (66),(es) [all …]
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| /linux/drivers/dma/ |
| H A D | Kconfig | 485 bool "Marvell XOR engine support" 491 Enable support for the Marvell XOR engine. 494 bool "Marvell XOR engine version 2 support " 501 Enable support for the Marvell version 2 XOR engine. 503 This engine provides acceleration for copy, XOR and RAID6
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| /linux/net/can/ |
| H A D | Kconfig | 53 They can be modified with AND/OR/XOR/SET operations as configured
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| /linux/Documentation/driver-api/md/ |
| H A D | raid5-ppl.rst | 15 Partial parity for a write operation is the XOR of stripe data chunks not
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| /linux/Documentation/filesystems/ |
| H A D | omfs.rst | 65 u8 h_check_xor; /* XOR of header bytes before this */
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| /linux/Documentation/driver-api/dmaengine/ |
| H A D | provider.rst | 88 async TX API, to offload operations such as memory copy, XOR, 180 - The device is able to perform XOR operations on memory areas 182 - Used to accelerate XOR intensive tasks, such as RAID5 186 - The device is able to perform parity check using the XOR 192 simple XOR, and Q being a Reed-Solomon algorithm.
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| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | rzg2lc-smarc-som.dtsi | 179 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
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