WREG32_SOC15 (reference) in projects: linux

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched refs:WREG32_SOC15 (Results 1 – 25 of 71) sorted by relevance

12 3

/linux/drivers/gpu/drm/amd/amdgpu/
H A D	mmhub_v2_3.c	140 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v2_3_init_gart_aperture_regs() 142 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v2_3_init_gart_aperture_regs() 145 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v2_3_init_gart_aperture_regs() 147 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v2_3_init_gart_aperture_regs() 157 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); in mmhub_v2_3_init_system_aperture_regs() 158 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v2_3_init_system_aperture_regs() 159 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v2_3_init_system_aperture_regs() 162 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, in mmhub_v2_3_init_system_aperture_regs() 164 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_v2_3_init_system_aperture_regs() 169 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in mmhub_v2_3_init_system_aperture_regs() [all …]
H A D	mmhub_v4_2_0.c	146 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_gart_aperture_regs() 149 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_gart_aperture_regs() 153 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_gart_aperture_regs() 156 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_gart_aperture_regs() 160 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_gart_aperture_regs() 163 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_gart_aperture_regs() 167 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_gart_aperture_regs() 170 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_gart_aperture_regs() 194 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_system_aperture_regs() 196 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_system_aperture_regs() [all …]
H A D	mmhub_v1_0.c	74 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v1_0_init_gart_aperture_regs() 76 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v1_0_init_gart_aperture_regs() 79 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v1_0_init_gart_aperture_regs() 81 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v1_0_init_gart_aperture_regs() 91 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0); in mmhub_v1_0_init_system_aperture_regs() 92 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v1_0_init_system_aperture_regs() 93 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v1_0_init_system_aperture_regs() 96 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, in mmhub_v1_0_init_system_aperture_regs() 108 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_v1_0_init_system_aperture_regs() 112 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_v1_0_init_system_aperture_regs() [all …]
H A D	gfxhub_v11_5_0.c	144 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v11_5_0_init_gart_aperture_regs() 146 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v11_5_0_init_gart_aperture_regs() 149 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v11_5_0_init_gart_aperture_regs() 151 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v11_5_0_init_gart_aperture_regs() 159 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v11_5_0_init_system_aperture_regs() 160 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v11_5_0_init_system_aperture_regs() 161 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v11_5_0_init_system_aperture_regs() 164 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v11_5_0_init_system_aperture_regs() 167 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gfxhub_v11_5_0_init_system_aperture_regs() 172 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in gfxhub_v11_5_0_init_system_aperture_regs() [all …]
H A D	gfxhub_v3_0.c	139 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v3_0_init_gart_aperture_regs() 141 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v3_0_init_gart_aperture_regs() 144 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v3_0_init_gart_aperture_regs() 146 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v3_0_init_gart_aperture_regs() 155 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v3_0_init_system_aperture_regs() 156 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v3_0_init_system_aperture_regs() 157 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v3_0_init_system_aperture_regs() 161 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v3_0_init_system_aperture_regs() 163 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gfxhub_v3_0_init_system_aperture_regs() 168 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in gfxhub_v3_0_init_system_aperture_regs() [all …]
H A D	gfxhub_v12_0.c	147 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v12_0_init_gart_aperture_regs() 149 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v12_0_init_gart_aperture_regs() 152 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v12_0_init_gart_aperture_regs() 154 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v12_0_init_gart_aperture_regs() 163 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v12_0_init_system_aperture_regs() 164 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v12_0_init_system_aperture_regs() 165 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v12_0_init_system_aperture_regs() 168 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v12_0_init_system_aperture_regs() 170 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gfxhub_v12_0_init_system_aperture_regs() 176 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in gfxhub_v12_0_init_system_aperture_regs() [all …]
H A D	mmhub_v3_0.c	157 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v3_0_init_gart_aperture_regs() 159 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v3_0_init_gart_aperture_regs() 162 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v3_0_init_gart_aperture_regs() 164 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v3_0_init_gart_aperture_regs() 182 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); in mmhub_v3_0_init_system_aperture_regs() 183 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_init_system_aperture_regs() 184 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v3_0_init_system_aperture_regs() 187 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, in mmhub_v3_0_init_system_aperture_regs() 189 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_v3_0_init_system_aperture_regs() 194 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in mmhub_v3_0_init_system_aperture_regs() [all …]
H A D	mmhub_v4_1_0.c	149 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v4_1_0_init_gart_aperture_regs() 151 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v4_1_0_init_gart_aperture_regs() 154 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v4_1_0_init_gart_aperture_regs() 156 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v4_1_0_init_gart_aperture_regs() 174 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); in mmhub_v4_1_0_init_system_aperture_regs() 175 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v4_1_0_init_system_aperture_regs() 176 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v4_1_0_init_system_aperture_regs() 179 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, in mmhub_v4_1_0_init_system_aperture_regs() 181 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_v4_1_0_init_system_aperture_regs() 187 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in mmhub_v4_1_0_init_system_aperture_regs() [all …]
H A D	mmhub_v3_0_1.c	166 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v3_0_1_init_gart_aperture_regs() 168 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v3_0_1_init_gart_aperture_regs() 171 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v3_0_1_init_gart_aperture_regs() 173 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v3_0_1_init_gart_aperture_regs() 183 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); in mmhub_v3_0_1_init_system_aperture_regs() 184 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_1_init_system_aperture_regs() 185 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v3_0_1_init_system_aperture_regs() 193 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, in mmhub_v3_0_1_init_system_aperture_regs() 195 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_v3_0_1_init_system_aperture_regs() 200 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in mmhub_v3_0_1_init_system_aperture_regs() [all …]
H A D	lsdma_v7_0.c	47 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_LO, lower_32_bits(src_addr)); in lsdma_v7_0_copy_mem() 48 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_HI, upper_32_bits(src_addr)); in lsdma_v7_0_copy_mem() 50 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr)); in lsdma_v7_0_copy_mem() 51 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr)); in lsdma_v7_0_copy_mem() 53 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONTROL, 0x0); in lsdma_v7_0_copy_mem() 63 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp); in lsdma_v7_0_copy_mem() 80 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONSTFILL_DATA, data); in lsdma_v7_0_fill_mem() 82 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr)); in lsdma_v7_0_fill_mem() 83 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr)); in lsdma_v7_0_fill_mem() 85 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONTROL, 0x0); in lsdma_v7_0_fill_mem() [all …]
H A D	lsdma_v6_0.c	47 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_LO, lower_32_bits(src_addr)); in lsdma_v6_0_copy_mem() 48 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_HI, upper_32_bits(src_addr)); in lsdma_v6_0_copy_mem() 50 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr)); in lsdma_v6_0_copy_mem() 51 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr)); in lsdma_v6_0_copy_mem() 53 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONTROL, 0x0); in lsdma_v6_0_copy_mem() 63 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp); in lsdma_v6_0_copy_mem() 80 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONSTFILL_DATA, data); in lsdma_v6_0_fill_mem() 82 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr)); in lsdma_v6_0_fill_mem() 83 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr)); in lsdma_v6_0_fill_mem() 85 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONTROL, 0x0); in lsdma_v6_0_fill_mem() [all …]
H A D	mmhub_v3_0_2.c	150 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v3_0_2_init_gart_aperture_regs() 152 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v3_0_2_init_gart_aperture_regs() 155 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v3_0_2_init_gart_aperture_regs() 157 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v3_0_2_init_gart_aperture_regs() 167 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); in mmhub_v3_0_2_init_system_aperture_regs() 168 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_2_init_system_aperture_regs() 169 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v3_0_2_init_system_aperture_regs() 178 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, in mmhub_v3_0_2_init_system_aperture_regs() 180 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_v3_0_2_init_system_aperture_regs() 186 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in mmhub_v3_0_2_init_system_aperture_regs() [all …]
H A D	gfxhub_v3_0_3.c	142 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v3_0_3_init_gart_aperture_regs() 144 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v3_0_3_init_gart_aperture_regs() 147 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v3_0_3_init_gart_aperture_regs() 149 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v3_0_3_init_gart_aperture_regs() 161 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v3_0_3_init_system_aperture_regs() 162 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v3_0_3_init_system_aperture_regs() 163 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v3_0_3_init_system_aperture_regs() 166 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v3_0_3_init_system_aperture_regs() 168 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gfxhub_v3_0_3_init_system_aperture_regs() 173 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in gfxhub_v3_0_3_init_system_aperture_regs() [all …]
H A D	gfxhub_v2_0.c	140 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs() 142 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs() 145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs() 147 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs() 157 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_0_init_system_aperture_regs() 158 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v2_0_init_system_aperture_regs() 159 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v2_0_init_system_aperture_regs() 162 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v2_0_init_system_aperture_regs() 164 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gfxhub_v2_0_init_system_aperture_regs() 169 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in gfxhub_v2_0_init_system_aperture_regs() [all …]
H A D	vcn_v5_0_0.c	374 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v5_0_0_mc_resume() 376 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v5_0_0_mc_resume() 378 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v5_0_0_mc_resume() 381 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v5_0_0_mc_resume() 383 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v5_0_0_mc_resume() 386 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v5_0_0_mc_resume() 388 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); in vcn_v5_0_0_mc_resume() 391 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v5_0_0_mc_resume() 393 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v5_0_0_mc_resume() 395 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v5_0_0_mc_resume() [all …]
H A D	vcn_v4_0_5.c	410 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v4_0_5_mc_resume() 412 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v4_0_5_mc_resume() 414 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v4_0_5_mc_resume() 417 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v4_0_5_mc_resume() 419 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v4_0_5_mc_resume() 422 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_5_mc_resume() 424 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); in vcn_v4_0_5_mc_resume() 427 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v4_0_5_mc_resume() 429 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v4_0_5_mc_resume() 431 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v4_0_5_mc_resume() [all …]
H A D	psp_v11_0_8.c	39 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_8_ring_stop() 49 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, in psp_v11_0_8_ring_stop() 79 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); in psp_v11_0_8_ring_create() 82 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); in psp_v11_0_8_ring_create() 85 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_8_ring_create() 108 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); in psp_v11_0_8_ring_create() 111 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); in psp_v11_0_8_ring_create() 114 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); in psp_v11_0_8_ring_create() 118 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); in psp_v11_0_8_ring_create() 168 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); in psp_v11_0_8_ring_set_wptr() [all …]
H A D	psp_v15_0.c	63 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, in psp_v15_0_0_ring_stop() 72 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, in psp_v15_0_0_ring_stop() 101 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg); in psp_v15_0_0_ring_create() 104 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg); in psp_v15_0_0_ring_create() 107 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, in psp_v15_0_0_ring_create() 128 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_69, psp_ring_reg); in psp_v15_0_0_ring_create() 131 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_70, psp_ring_reg); in psp_v15_0_0_ring_create() 134 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_71, psp_ring_reg); in psp_v15_0_0_ring_create() 138 WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, psp_ring_reg); in psp_v15_0_0_ring_create() 187 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value); in psp_v15_0_0_ring_set_wptr() [all …]
H A D	psp_v13_0_4.c	114 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, in psp_v13_0_4_bootloader_load_component() 117 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, in psp_v13_0_4_bootloader_load_component() 177 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, in psp_v13_0_4_bootloader_load_sos() 180 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, in psp_v13_0_4_bootloader_load_sos() 200 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, in psp_v13_0_4_ring_stop() 210 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, in psp_v13_0_4_ring_stop() 240 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); in psp_v13_0_4_ring_create() 243 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); in psp_v13_0_4_ring_create() 246 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, in psp_v13_0_4_ring_create() 269 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); in psp_v13_0_4_ring_create() [all …]
H A D	imu_v12_0.c	102 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0); in imu_v12_0_load_microcode() 105 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v12_0_load_microcode() 107 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v12_0_load_microcode() 114 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0); in imu_v12_0_load_microcode() 117 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v12_0_load_microcode() 119 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v12_0_load_microcode() 148 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff); in imu_v12_0_setup() 149 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff); in imu_v12_0_setup() 154 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val); in imu_v12_0_setup() 158 WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val); in imu_v12_0_setup() [all …]
H A D	mmhub_v2_0.c	233 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, in mmhub_v2_0_init_system_aperture_regs() 235 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_v2_0_init_system_aperture_regs() 241 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in mmhub_v2_0_init_system_aperture_regs() 243 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, in mmhub_v2_0_init_system_aperture_regs() 247 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, in mmhub_v2_0_init_system_aperture_regs() 249 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, in mmhub_v2_0_init_system_aperture_regs() 255 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v2_0_init_system_aperture_regs() 274 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v2_0_init_tlb_regs() 299 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); in mmhub_v2_0_init_cache_regs() 304 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp); in mmhub_v2_0_init_cache_regs() [all …]
H A D	psp_v14_0.c	149 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, in psp_v14_0_bootloader_load_component() 152 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, in psp_v14_0_bootloader_load_component() 223 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, in psp_v14_0_bootloader_load_sos() 226 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, in psp_v14_0_bootloader_load_sos() 247 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, in psp_v14_0_ring_stop() 257 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, in psp_v14_0_ring_stop() 287 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg); in psp_v14_0_ring_create() 290 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg); in psp_v14_0_ring_create() 293 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, in psp_v14_0_ring_create() 316 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg); in psp_v14_0_ring_create() [all …]
H A D	psp_v13_0.c	280 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, in psp_v13_0_bootloader_load_component() 283 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, in psp_v13_0_bootloader_load_component() 362 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, in psp_v13_0_bootloader_load_sos() 365 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, in psp_v13_0_bootloader_load_sos() 388 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, in psp_v13_0_ring_stop() 398 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, in psp_v13_0_ring_stop() 428 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); in psp_v13_0_ring_create() 431 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); in psp_v13_0_ring_create() 434 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, in psp_v13_0_ring_create() 457 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); in psp_v13_0_ring_create() [all …]
H A D	vcn_v2_5.c	601 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume() 603 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume() 605 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_5_mc_resume() 608 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume() 610 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume() 613 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_5_mc_resume() 616 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v2_5_mc_resume() 619 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v2_5_mc_resume() 621 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume() 623 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v2_5_mc_resume() [all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A D	smu9_smumgr.c	99 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_101, msg); in smu9_send_msg_to_smc_without_waiting() 101 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); in smu9_send_msg_to_smc_without_waiting() 121 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103, 0); in smu9_send_msg_to_smc() 123 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu9_send_msg_to_smc() 150 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103, 0); in smu9_send_msg_to_smc_with_parameter() 151 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102, parameter); in smu9_send_msg_to_smc_with_parameter() 153 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu9_send_msg_to_smc_with_parameter() 154 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); in smu9_send_msg_to_smc_with_parameter()

12 3