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Searched refs:WREG32 (Results 1 – 25 of 105) sorted by relevance

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/linux/drivers/accel/habanalabs/goya/
H A Dgoya_security.c23 WREG32(pb_addr, 0); in goya_pb_set_block()
81 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
104 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
128 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
160 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
180 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
194 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
210 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
228 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
251 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
[all …]
H A Dgoya_coresight.c243 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in goya_config_stm()
251 WREG32(base_reg + 0xE80, 0x80004); in goya_config_stm()
252 WREG32(base_reg + 0xD64, 7); in goya_config_stm()
253 WREG32(base_reg + 0xD60, 0); in goya_config_stm()
254 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in goya_config_stm()
255 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask)); in goya_config_stm()
256 WREG32(base_reg + 0xD60, 1); in goya_config_stm()
257 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); in goya_config_stm()
258 WREG32(base_reg + 0xD20, upper_32_bits(input->sp_mask)); in goya_config_stm()
259 WREG32(base_reg + 0xE70, 0x10); in goya_config_stm()
[all …]
H A Dgoya.c732 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED); in goya_qman0_set_security()
734 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED); in goya_qman0_set_security()
893 WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size)); in goya_late_init()
1101 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address)); in goya_init_dma_qman()
1102 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address)); in goya_init_dma_qman()
1104 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH)); in goya_init_dma_qman()
1105 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0); in goya_init_dma_qman()
1106 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0); in goya_init_dma_qman()
1108 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); in goya_init_dma_qman()
1109 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); in goya_init_dma_qman()
[all …]
/linux/drivers/gpu/drm/radeon/
H A Drv515.c137 WREG32(R_000300_VGA_RENDER_CONTROL, in rv515_vga_render_disable()
202 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); in rv515_mc_rreg()
204 WREG32(MC_IND_INDEX, 0); in rv515_mc_rreg()
215 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); in rv515_mc_wreg()
216 WREG32(MC_IND_DATA, (v)); in rv515_mc_wreg()
217 WREG32(MC_IND_INDEX, 0); in rv515_mc_wreg()
277 WREG32(R_000300_VGA_RENDER_CONTROL, 0); in rv515_mc_stop()
286 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in rv515_mc_stop()
288 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()
289 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in rv515_mc_stop()
[all …]
H A Dradeon_bios.c266 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); in ni_read_disabled_bios()
269 WREG32(AVIVO_D1VGA_CONTROL, in ni_read_disabled_bios()
272 WREG32(AVIVO_D2VGA_CONTROL, in ni_read_disabled_bios()
275 WREG32(AVIVO_VGA_RENDER_CONTROL, in ni_read_disabled_bios()
278 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); in ni_read_disabled_bios()
283 WREG32(R600_BUS_CNTL, bus_cntl); in ni_read_disabled_bios()
285 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); in ni_read_disabled_bios()
286 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); in ni_read_disabled_bios()
287 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); in ni_read_disabled_bios()
289 WREG32(R600_ROM_CNTL, rom_cntl); in ni_read_disabled_bios()
[all …]
H A Drv770.c809 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
812 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rv770_page_flip()
815 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, in rv770_page_flip()
819 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
820 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
822 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
823 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
825 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
827 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
840 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
[all …]
H A Dvce_v2_0.c46 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
50 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
54 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
56 WREG32(VCE_CGTT_CLK_OVERRIDE, 0); in vce_v2_0_set_sw_cg()
61 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
66 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
70 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
86 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_dyn_cg()
92 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_dyn_cg()
97 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_dyn_cg()
[all …]
H A Duvd_v1_0.c70 WREG32(UVD_RBC_RB_WPTR, ring->wptr); in uvd_v1_0_set_wptr()
123 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); in uvd_v1_0_resume()
124 WREG32(UVD_VCPU_CACHE_SIZE0, size); in uvd_v1_0_resume()
128 WREG32(UVD_VCPU_CACHE_OFFSET1, addr); in uvd_v1_0_resume()
129 WREG32(UVD_VCPU_CACHE_SIZE1, size); in uvd_v1_0_resume()
134 WREG32(UVD_VCPU_CACHE_OFFSET2, addr); in uvd_v1_0_resume()
135 WREG32(UVD_VCPU_CACHE_SIZE2, size); in uvd_v1_0_resume()
139 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); in uvd_v1_0_resume()
143 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); in uvd_v1_0_resume()
145 WREG32(UVD_FW_START, *((uint32_t *)rdev->uvd.cpu_addr)); in uvd_v1_0_resume()
[all …]
H A Dvce_v1_0.c98 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr()
100 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_set_wptr()
110 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_enable_mgcg()
115 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
119 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
123 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_enable_mgcg()
128 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
132 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
142 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_init_cg()
147 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v1_0_init_cg()
[all …]
H A Dr600.c126 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); in r600_rcu_rreg()
137 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); in r600_rcu_wreg()
138 WREG32(R600_RCU_DATA, (v)); in r600_rcu_wreg()
148 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); in r600_uvd_ctx_rreg()
159 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); in r600_uvd_ctx_wreg()
160 WREG32(R600_UVD_CTX_DATA, (v)); in r600_uvd_ctx_wreg()
346 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
873 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
881 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_hpd_set_polarity()
889 WREG32(DC_HPD3_INT_CONTROL, tmp); in r600_hpd_set_polarity()
[all …]
H A Dradeon_i2c.c112 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | in pre_xfer()
115 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | in pre_xfer()
126 WREG32(rec->mask_clk_reg, temp); in pre_xfer()
131 WREG32(rec->a_clk_reg, temp); in pre_xfer()
134 WREG32(rec->a_data_reg, temp); in pre_xfer()
138 WREG32(rec->en_clk_reg, temp); in pre_xfer()
141 WREG32(rec->en_data_reg, temp); in pre_xfer()
145 WREG32(rec->mask_clk_reg, temp); in pre_xfer()
149 WREG32(rec->mask_data_reg, temp); in pre_xfer()
164 WREG32(rec->mask_clk_reg, temp); in post_xfer()
[all …]
H A Dni.c53 WREG32(TN_SMC_IND_INDEX_0, (reg)); in tn_smc_rreg()
64 WREG32(TN_SMC_IND_INDEX_0, (reg)); in tn_smc_wreg()
65 WREG32(TN_SMC_IND_DATA_0, (v)); in tn_smc_wreg()
657 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ni_mc_load_microcode()
658 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in ni_mc_load_microcode()
662 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); in ni_mc_load_microcode()
663 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); in ni_mc_load_microcode()
668 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); in ni_mc_load_microcode()
671 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ni_mc_load_microcode()
672 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); in ni_mc_load_microcode()
[all …]
H A Devergreen_hdmi.c66 WREG32(AZ_HOT_PLUG_CONTROL, tmp); in dce4_audio_enable()
82 WREG32(HDMI_ACR_PACKET_CONTROL + offset, in evergreen_hdmi_update_acr()
85 WREG32(HDMI_ACR_PACKET_CONTROL + offset, in evergreen_hdmi_update_acr()
89 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); in evergreen_hdmi_update_acr()
90 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); in evergreen_hdmi_update_acr()
92 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); in evergreen_hdmi_update_acr()
93 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); in evergreen_hdmi_update_acr()
95 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); in evergreen_hdmi_update_acr()
96 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); in evergreen_hdmi_update_acr()
215 WREG32(AFMT_AVI_INFO0 + offset, in evergreen_set_avi_packet()
[all …]
H A Devergreen.c63 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_rreg()
74 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_wreg()
75 WREG32(EVERGREEN_CG_IND_DATA, (v)); in eg_cg_wreg()
85 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_rreg()
96 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_wreg()
97 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); in eg_pif_phy0_wreg()
107 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_rreg()
118 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_wreg()
119 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); in eg_pif_phy1_wreg()
1184 WREG32(CG_SCRATCH1, cg_scratch); in sumo_set_uvd_clocks()
[all …]
H A Drs600.c128 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
131 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rs600_page_flip()
134 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, in rs600_page_flip()
137 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
139 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
152 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
212 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp); in avivo_program_fmt()
215 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp); in avivo_program_fmt()
218 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp); in avivo_program_fmt()
221 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp); in avivo_program_fmt()
[all …]
H A Dradeon_cursor.c44 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
51 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
58 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
99 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in radeon_show_cursor()
101 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in radeon_show_cursor()
103 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); in radeon_show_cursor()
104 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | in radeon_show_cursor()
110 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, in radeon_show_cursor()
113 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, in radeon_show_cursor()
117 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in radeon_show_cursor()
[all …]
/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi_coresight.c405 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in gaudi_config_stm()
413 WREG32(base_reg + 0xE80, 0x80004); in gaudi_config_stm()
414 WREG32(base_reg + 0xD64, 7); in gaudi_config_stm()
415 WREG32(base_reg + 0xD60, 0); in gaudi_config_stm()
416 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in gaudi_config_stm()
417 WREG32(base_reg + 0xD60, 1); in gaudi_config_stm()
418 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); in gaudi_config_stm()
419 WREG32(base_reg + 0xE70, 0x10); in gaudi_config_stm()
420 WREG32(base_reg + 0xE60, 0); in gaudi_config_stm()
421 WREG32(base_reg + 0xE00, lower_32_bits(input->sp_mask)); in gaudi_config_stm()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v8_0.c184 WREG32(mmBIF_FB_EN, 0); in gmc_v8_0_mc_stop()
188 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); in gmc_v8_0_mc_stop()
201 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v8_0_mc_resume()
205 WREG32(mmBIF_FB_EN, tmp); in gmc_v8_0_mc_resume()
245 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159); in gmc_v8_0_init_microcode()
313 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
314 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_tonga_mc_load_microcode()
318 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); in gmc_v8_0_tonga_mc_load_microcode()
319 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); in gmc_v8_0_tonga_mc_load_microcode()
323 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); in gmc_v8_0_tonga_mc_load_microcode()
[all …]
H A Dgmc_v6_0.c78 WREG32(mmBIF_FB_EN, 0); in gmc_v6_0_mc_stop()
82 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); in gmc_v6_0_mc_stop()
96 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v6_0_mc_resume()
100 WREG32(mmBIF_FB_EN, tmp); in gmc_v6_0_mc_resume()
173 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v6_0_mc_load_microcode()
174 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v6_0_mc_load_microcode()
178 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in gmc_v6_0_mc_load_microcode()
179 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); in gmc_v6_0_mc_load_microcode()
183 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); in gmc_v6_0_mc_load_microcode()
186 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v6_0_mc_load_microcode()
[all …]
H A Dgmc_v7_0.c102 WREG32(mmBIF_FB_EN, 0); in gmc_v7_0_mc_stop()
106 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); in gmc_v7_0_mc_stop()
119 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v7_0_mc_resume()
123 WREG32(mmBIF_FB_EN, tmp); in gmc_v7_0_mc_resume()
203 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v7_0_mc_load_microcode()
204 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v7_0_mc_load_microcode()
208 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); in gmc_v7_0_mc_load_microcode()
209 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); in gmc_v7_0_mc_load_microcode()
213 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); in gmc_v7_0_mc_load_microcode()
216 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v7_0_mc_load_microcode()
[all …]
H A Damdgpu_amdkfd_gfx_v8.c48 WREG32(mmSRBM_GFX_CNTL, value); in lock_srbm()
53 WREG32(mmSRBM_GFX_CNTL, 0); in unlock_srbm()
79 WREG32(mmSH_MEM_CONFIG, sh_mem_config); in kgd_program_sh_mem_settings()
80 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base); in kgd_program_sh_mem_settings()
81 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit); in kgd_program_sh_mem_settings()
82 WREG32(mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
100 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping); in kgd_set_pasid_vmid_mapping()
104 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); in kgd_set_pasid_vmid_mapping()
107 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping); in kgd_set_pasid_vmid_mapping()
123 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in kgd_init_interrupts()
[all …]
H A Damdgpu_amdkfd_gfx_v7.c54 WREG32(mmSRBM_GFX_CNTL, value); in lock_srbm()
59 WREG32(mmSRBM_GFX_CNTL, 0); in unlock_srbm()
85 WREG32(mmSH_MEM_CONFIG, sh_mem_config); in kgd_program_sh_mem_settings()
86 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base); in kgd_program_sh_mem_settings()
87 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit); in kgd_program_sh_mem_settings()
88 WREG32(mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
105 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping); in kgd_set_pasid_vmid_mapping()
109 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); in kgd_set_pasid_vmid_mapping()
112 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping); in kgd_set_pasid_vmid_mapping()
128 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in kgd_init_interrupts()
[all …]
H A Dsi_ih.c43 WREG32(IH_CNTL, ih_cntl); in si_ih_enable_interrupts()
44 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_enable_interrupts()
55 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_disable_interrupts()
56 WREG32(IH_CNTL, ih_cntl); in si_ih_disable_interrupts()
57 WREG32(IH_RB_RPTR, 0); in si_ih_disable_interrupts()
58 WREG32(IH_RB_WPTR, 0); in si_ih_disable_interrupts()
71 WREG32(INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in si_ih_irq_init()
75 WREG32(INTERRUPT_CNTL, interrupt_cntl); in si_ih_irq_init()
77 WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in si_ih_irq_init()
85 WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in si_ih_irq_init()
[all …]
H A Dvpe_v6_1.c82 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_F32_CNTL), f32_cntl); in vpe_v6_1_halt()
112 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CNTL), vpe_colla_cntl); in vpe_v6_1_set_collaborate_mode()
119 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CFG), vpe_colla_cfg); in vpe_v6_1_set_collaborate_mode()
143 WREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL_6_1_1), ret); in vpe_v6_1_load_microcode()
145 WREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL), ret); in vpe_v6_1_load_microcode()
186 WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), VPE_THREAD1_UCODE_OFFSET); in vpe_v6_1_load_microcode()
188 WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), 0); in vpe_v6_1_load_microcode()
196 WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_DATA), le32_to_cpup(data++)); in vpe_v6_1_load_microcode()
222 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl); in vpe_v6_1_ring_start()
225 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR), 0); in vpe_v6_1_ring_start()
[all …]
H A Dcik_ih.c67 WREG32(mmIH_CNTL, ih_cntl); in cik_ih_enable_interrupts()
68 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_enable_interrupts()
86 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_disable_interrupts()
87 WREG32(mmIH_CNTL, ih_cntl); in cik_ih_disable_interrupts()
89 WREG32(mmIH_RB_RPTR, 0); in cik_ih_disable_interrupts()
90 WREG32(mmIH_RB_WPTR, 0); in cik_ih_disable_interrupts()
116 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in cik_ih_irq_init()
124 WREG32(mmINTERRUPT_CNTL, interrupt_cntl); in cik_ih_irq_init()
126 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in cik_ih_irq_init()
136 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in cik_ih_irq_init()
[all …]

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