76 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));  in uvd_v3_1_ring_set_wptr()
146 	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);  in uvd_v3_1_ring_test_ring()
229 	WREG32(mmUVD_CGC_CTRL, tmp);  in uvd_v3_1_set_dcm()
252 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);  in uvd_v3_1_mc_resume()
253 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);  in uvd_v3_1_mc_resume()
257 	WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);  in uvd_v3_1_mc_resume()
258 	WREG32(mmUVD_VCPU_CACHE_SIZE1, size);  in uvd_v3_1_mc_resume()
263 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);  in uvd_v3_1_mc_resume()
264 	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);  in uvd_v3_1_mc_resume()
268 	WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));  in uvd_v3_1_mc_resume()
272 	WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));  in uvd_v3_1_mc_resume()
274 	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in uvd_v3_1_mc_resume()
275 	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in uvd_v3_1_mc_resume()
276 	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in uvd_v3_1_mc_resume()
297 	WREG32(mmUVD_FW_START, keysel);  in uvd_v3_1_fw_validate()
344 	WREG32(mmUVD_CGC_GATE, 0);  in uvd_v3_1_start()
351 	WREG32(mmUVD_VCPU_CNTL,  1 << 9);  in uvd_v3_1_start()
361 	WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);  in uvd_v3_1_start()
362 	WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);  in uvd_v3_1_start()
365 	WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |  in uvd_v3_1_start()
369 	WREG32(mmUVD_MPC_CNTL, tmp | 0x10);  in uvd_v3_1_start()
371 	WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);  in uvd_v3_1_start()
372 	WREG32(mmUVD_MPC_SET_MUXA1, 0x0);  in uvd_v3_1_start()
373 	WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);  in uvd_v3_1_start()
374 	WREG32(mmUVD_MPC_SET_MUXB1, 0x0);  in uvd_v3_1_start()
375 	WREG32(mmUVD_MPC_SET_ALU, 0);  in uvd_v3_1_start()
376 	WREG32(mmUVD_MPC_SET_MUX, 0x88);  in uvd_v3_1_start()
424 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);  in uvd_v3_1_start()
427 	WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);  in uvd_v3_1_start()
430 	WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |  in uvd_v3_1_start()
434 	WREG32(mmUVD_RBC_RB_RPTR, 0x0);  in uvd_v3_1_start()
437 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));  in uvd_v3_1_start()
440 	WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);  in uvd_v3_1_start()
462 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);  in uvd_v3_1_stop()
505 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |  in uvd_v3_1_stop()
509 	WREG32(mmUVD_STATUS, 0);  in uvd_v3_1_stop()
618 			WREG32(mmUVD_CGC_CTRL, data);  in uvd_v3_1_enable_mgcg()
627 			WREG32(mmUVD_CGC_CTRL, data);  in uvd_v3_1_enable_mgcg()