112 		WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));  in vce_v1_0_ring_set_wptr()
114 		WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));  in vce_v1_0_ring_set_wptr()
164 	WREG32(mmVCE_CLOCK_GATING_A, tmp);  in vce_v1_0_init_cg()
169 	WREG32(mmVCE_CLOCK_GATING_B, tmp);  in vce_v1_0_init_cg()
173 	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);  in vce_v1_0_init_cg()
177 	WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);  in vce_v1_0_init_cg()
257 	WREG32(mmVCE_LMI_FW_START_KEYSEL, adev->vce.keyselect);  in vce_v1_0_wait_for_fw_validation()
309 	WREG32(mmVCE_CLOCK_GATING_B, 0);  in vce_v1_0_mc_resume()
313 	WREG32(mmVCE_LMI_CTRL, 0x00398000);  in vce_v1_0_mc_resume()
316 	WREG32(mmVCE_LMI_SWAP_CNTL, 0);  in vce_v1_0_mc_resume()
317 	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);  in vce_v1_0_mc_resume()
318 	WREG32(mmVCE_LMI_VM_CTRL, 0);  in vce_v1_0_mc_resume()
320 	WREG32(mmVCE_VCPU_SCRATCH7, AMDGPU_MAX_VCE_HANDLES);  in vce_v1_0_mc_resume()
324 	WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset);  in vce_v1_0_mc_resume()
325 	WREG32(mmVCE_VCPU_CACHE_SIZE0, size);  in vce_v1_0_mc_resume()
331 	WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset);  in vce_v1_0_mc_resume()
332 	WREG32(mmVCE_VCPU_CACHE_SIZE1, size);  in vce_v1_0_mc_resume()
339 	WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset);  in vce_v1_0_mc_resume()
340 	WREG32(mmVCE_VCPU_CACHE_SIZE2, size);  in vce_v1_0_mc_resume()
399 	WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));  in vce_v1_0_start()
400 	WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));  in vce_v1_0_start()
401 	WREG32(mmVCE_RB_BASE_LO, lower_32_bits(ring->gpu_addr));  in vce_v1_0_start()
402 	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vce_v1_0_start()
403 	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);  in vce_v1_0_start()
406 	WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));  in vce_v1_0_start()
407 	WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));  in vce_v1_0_start()
408 	WREG32(mmVCE_RB_BASE_LO2, lower_32_bits(ring->gpu_addr));  in vce_v1_0_start()
409 	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vce_v1_0_start()
410 	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);  in vce_v1_0_start()
430 	WREG32(mmVCE_STATUS, 0);  in vce_v1_0_start()
475 	WREG32(mmVCE_STATUS, 0);  in vce_v1_0_stop()
487 		WREG32(mmVCE_CLOCK_GATING_A, tmp);  in vce_v1_0_enable_mgcg()
492 		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);  in vce_v1_0_enable_mgcg()
496 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);  in vce_v1_0_enable_mgcg()
500 		WREG32(mmVCE_CLOCK_GATING_A, tmp);  in vce_v1_0_enable_mgcg()
505 		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);  in vce_v1_0_enable_mgcg()
509 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);  in vce_v1_0_enable_mgcg()