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Searched refs:VM_L2_CNTL2 (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c191 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v1_0_init_cache_regs()
192 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
H A Dgfxhub_v2_1.c552 adev->gmc.VM_L2_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_1_save_regs()
587 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, adev->gmc.VM_L2_CNTL2); in gfxhub_v2_1_restore_regs()
H A Dgfxhub_v1_2.c242 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v1_2_xcc_init_cache_regs()
243 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v1_2_xcc_init_cache_regs()
H A Dmmhub_v1_0.c177 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v1_0_init_cache_regs()
178 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
/linux/drivers/gpu/drm/radeon/
H A Drv770.c910 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_enable()
956 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_disable()
987 WREG32(VM_L2_CNTL2, 0); in rv770_agp_enable()
H A Drv770d.h647 #define VM_L2_CNTL2 0x1404 macro
H A Dnid.h117 #define VM_L2_CNTL2 0x1404 macro
H A Dni.c1274 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cayman_pcie_gart_enable()
1353 WREG32(VM_L2_CNTL2, 0); in cayman_pcie_gart_disable()
H A Dcikd.h496 #define VM_L2_CNTL2 0x1404 macro
H A Devergreend.h1155 #define VM_L2_CNTL2 0x1404 macro
H A Dr600d.h592 #define VM_L2_CNTL2 0x1404 macro
H A Dr600.c1145 WREG32(VM_L2_CNTL2, 0); in r600_pcie_gart_enable()
1237 WREG32(VM_L2_CNTL2, 0); in r600_agp_enable()