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Searched refs:VM_CONTEXT1_CNTL (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c266 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v1_0_setup_vmid_config()
267 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v1_0_setup_vmid_config()
269 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
271 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
274 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
276 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
278 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
280 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
282 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
284 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
[all …]
H A Dgfxhub_v1_2.c336 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v1_2_xcc_setup_vmid_config()
337 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v1_2_xcc_setup_vmid_config()
339 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
341 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
344 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
346 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
348 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
350 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
352 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
354 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
[all …]
H A Dmmhub_v1_8.c349 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_8_setup_vmid_config()
351 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_8_setup_vmid_config()
353 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_8_setup_vmid_config()
355 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_8_setup_vmid_config()
357 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_8_setup_vmid_config()
359 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_8_setup_vmid_config()
361 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_8_setup_vmid_config()
363 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_8_setup_vmid_config()
365 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_8_setup_vmid_config()
367 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_8_setup_vmid_config()
[all …]
H A Dmmhub_v1_7.c278 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_7_setup_vmid_config()
279 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in mmhub_v1_7_setup_vmid_config()
281 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_7_setup_vmid_config()
283 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_7_setup_vmid_config()
286 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_7_setup_vmid_config()
288 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_7_setup_vmid_config()
290 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_7_setup_vmid_config()
292 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_7_setup_vmid_config()
294 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_7_setup_vmid_config()
296 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in mmhub_v1_7_setup_vmid_config()
[all …]
H A Dsid.h409 #define VM_CONTEXT1_CNTL 0x505 macro
/linux/drivers/gpu/drm/radeon/
H A Dni.c1309 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cayman_pcie_gart_enable()
1343 WREG32(VM_CONTEXT1_CNTL, 0); in cayman_pcie_gart_disable()
H A Dnid.h143 #define VM_CONTEXT1_CNTL 0x1414 macro
H A Dsid.h408 #define VM_CONTEXT1_CNTL 0x1414 macro
H A Dcikd.h526 #define VM_CONTEXT1_CNTL 0x1414 macro
H A Devergreen.c2448 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_pcie_gart_enable()
2464 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_pcie_gart_disable()
2514 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_agp_enable()
H A Devergreend.h1140 #define VM_CONTEXT1_CNTL 0x1414 macro
H A Dsi.c4330 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in si_pcie_gart_enable()
4368 WREG32(VM_CONTEXT1_CNTL, 0); in si_pcie_gart_disable()
H A Dcik.c5480 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cik_pcie_gart_enable()
5551 WREG32(VM_CONTEXT1_CNTL, 0); in cik_pcie_gart_disable()