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Searched refs:TIME_STAMP_INT_ENABLE (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dcikd.h1337 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
1369 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dnid.h497 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Devergreend.h1250 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dr600d.h718 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dr600.c3822 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c4774 TIME_STAMP_INT_ENABLE, 0); in gfx_v12_0_set_gfx_eop_interrupt_state()
4782 TIME_STAMP_INT_ENABLE, 1); in gfx_v12_0_set_gfx_eop_interrupt_state()
4825 TIME_STAMP_INT_ENABLE, 0); in gfx_v12_0_set_compute_eop_interrupt_state()
4833 TIME_STAMP_INT_ENABLE, 1); in gfx_v12_0_set_compute_eop_interrupt_state()
H A Dgfx_v11_0.c6431 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_gfx_eop_interrupt_state()
6439 TIME_STAMP_INT_ENABLE, 1); in gfx_v11_0_set_gfx_eop_interrupt_state()
6488 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_compute_eop_interrupt_state()
6496 TIME_STAMP_INT_ENABLE, 1); in gfx_v11_0_set_compute_eop_interrupt_state()
H A Dgfx_v9_4_3.c3207 TIME_STAMP_INT_ENABLE, 0); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3213 TIME_STAMP_INT_ENABLE, 1); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
H A Dgfx_v12_1.c3931 TIME_STAMP_INT_ENABLE, 0); in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
3939 TIME_STAMP_INT_ENABLE, 1); in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
H A Dgfx_v9_0.c6011 TIME_STAMP_INT_ENABLE, in gfx_v9_0_set_gfx_eop_interrupt_state()
6058 TIME_STAMP_INT_ENABLE, 0); in gfx_v9_0_set_compute_eop_interrupt_state()
6064 TIME_STAMP_INT_ENABLE, 1); in gfx_v9_0_set_compute_eop_interrupt_state()
H A Dgfx_v10_0.c9084 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_gfx_eop_interrupt_state()
9090 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_gfx_eop_interrupt_state()
9137 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_compute_eop_interrupt_state()
9143 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_compute_eop_interrupt_state()
H A Dgfx_v8_0.c6294 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, in gfx_v8_0_set_gfx_eop_interrupt_state()