Searched refs:TIME_STAMP_INT_ENABLE (Results 1 – 16 of 16) sorted by relevance
/linux/drivers/gpu/drm/radeon/ |
H A D | cik.c | 7051 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set() 7052 cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set() 7053 cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set() 7054 cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set() 7055 cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set() 7056 cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set() 7057 cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set() 7058 cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set() 7063 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set() 7071 cp_m1p0 |= TIME_STAMP_INT_ENABLE; in cik_irq_set() [all...] |
H A D | cikd.h | 1337 # define TIME_STAMP_INT_ENABLE (1 << 26) macro 1369 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
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H A D | nid.h | 497 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
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H A D | evergreen.c | 4524 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set() 4528 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set() 4532 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set() 4538 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
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H A D | sid.h | 1282 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
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H A D | si.c | 6063 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set() 6067 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in si_irq_set() 6071 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
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H A D | evergreend.h | 1250 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
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H A D | r600d.h | 718 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
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H A D | r600.c | 3822 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
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/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | gfx_v12_0.c | 4653 TIME_STAMP_INT_ENABLE, 0); in gfx_v12_0_set_compute_eop_interrupt_state() 4661 TIME_STAMP_INT_ENABLE, 1); in gfx_v12_0_set_compute_eop_interrupt_state() 4704 TIME_STAMP_INT_ENABLE, 0); in gfx_v12_0_eop_irq() 4712 TIME_STAMP_INT_ENABLE, 1); in gfx_v12_0_eop_irq()
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H A D | sid.h | 1310 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
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H A D | gfx_v11_0.c | 6127 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_eop_interrupt_state() 6135 TIME_STAMP_INT_ENABLE, 1); in gfx_v11_0_set_eop_interrupt_state() 6184 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_eop_irq() 6192 TIME_STAMP_INT_ENABLE, 1); in gfx_v11_0_eop_irq()
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H A D | gfx_v9_4_3.c | 3106 TIME_STAMP_INT_ENABLE, 0); in gfx_v9_4_3_emit_wave_limit_cs() 3112 TIME_STAMP_INT_ENABLE, 1); in gfx_v9_4_3_emit_wave_limit_cs()
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H A D | gfx_v9_0.c | 5948 TIME_STAMP_INT_ENABLE, in gfx_v9_0_set_priv_reg_fault_state() 5995 TIME_STAMP_INT_ENABLE, 0); in gfx_v9_0_set_cp_ecc_error_state() 6001 TIME_STAMP_INT_ENABLE, 1); in gfx_v9_0_set_cp_ecc_error_state()
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H A D | gfx_v10_0.c | 8985 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_compute_eop_interrupt_state() 8991 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_eop_interrupt_state() 9038 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_eop_irq() 9044 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_eop_irq()
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H A D | gfx_v8_0.c | 6428 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, in gfx_v8_0_set_compute_eop_interrupt_state()
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